DE19636054A1 - Semiconductor device, e.g. DRAM - Google Patents

Abstract

Semiconductor device comprises a semiconductor substrate, and a capacitor provided on the substrate. The capacitor has a lower electrode, a dielectric film on the lower electrode, and an upper electrode on the dielectric film. The novelty is that the dielectric film (117) has a thickness of 100 nm or less, and is made of a metal oxide consisting of a perovskite structure of ABO3 type (where A = Sr, Ba or Ca ion; and B = Ti ion), and contains Fe, Mn or Co. Also claimed is a dynamic storage device. Further claimed is the prodn. of the semiconductor device.

Description

The present invention relates to a semiconductor device, and, in particular, a semiconductor device having a Capacitor is provided which is a dielectric film which is made of a metal oxide which has a perovskite crystal structure, and relates to a Process for the production of such Semiconductor device.

When developing a semiconductor memory device as Storage device for an information processor has it given rapid progress. A typical example of one such a semiconductor memory device is a DRAM (dynamic random access memory), the uses a memory cell consisting of a transistor and a capacitor.

Improving the performance of one Semiconductor memory device such as a DRAM can, as in the case of other types of semiconductor devices can be achieved by increasing the integration density  is, so the memory cell is reduced. However it in a semiconductor memory device such as a DRAM required to shrink a memory cell while the Capacity is maintained to an impairment of Prevent reliability by deleting saved Information can be caused.

Usually, a silicon oxide film or a laminate film of a silicon oxide film and a silicon nitride film as dielectric film of a capacitor is used. However, to the capacitance per unit area of a capacitor corresponding to an increasing reduction in size Increasing memory cell in the future must now be done Material used, which is a higher Dielectric constant has as silicon oxide or Silicon nitride.

In view of these requirements, is currently being investigated as Material for the dielectric of a capacitor use ferroelectric material, which a Perovskite crystal structure, for example Strontium titanate, barium titanate or PZT, their Dielectric constant is 50 to 1000 times higher than that of Silicon oxide.

However, one thing occurs with a dielectric film Capacitor made of such a ferroelectric Material with perovskite crystal structure is made that Problem on that with a thinner film formation too the film's dielectric constant drops significantly. It it is believed that reducing the Dielectric constant of the film due to disorder,  Defects or deformations of the crystal structure in the film is caused.

For various reasons, the creation of a electric field (of an inner electric field) in a dielectric film of a capacitor. However, if ferroelectric materials as above mentioned used, and the inner electric field strong that is in a dielectric film of a capacitor is generated, the difficulty arises that the Dielectric constant of the dielectric film reduced becomes.

It should also be borne in mind that the inner electrical Field not just by a trapped electric charge or a fixed electric charge in the dielectric film Capacitor can be caused, but also by the Disorder, defects or deformation of the crystal structure of the film.

If in this way the dielectric constant of a dielectric film of a capacitor is reduced, so this leads to the difficulty that the reliability of a Semiconductor memory device is significantly impaired due to loss of accumulated charges in the Capacitor.

If the atomic ratio of oxygen in one ferroelectric film of this type is reduced, i.e. below the stoichiometric ratio, the generation of a Leakage current more likely. Therefore, if the dielectric Film is becoming thinner to increase its capacity will increase the function of the film as a dielectric film  significantly impaired, which in turn affects the reliability of the resulting semiconductor memory device affected.

Since the prohibited band of a ferroelectric film of this kind is generally narrow, can also be easily large leakage current is generated when an electrical Voltage is applied to the film. If you try this effect to avoid, so with thinner training of the dielectric film to increase its capacitance Function of the film as a dielectric film is essential impaired, which in turn affects the reliability of the resulting semiconductor memory device is impaired.

As discussed above, is currently under investigation to Purpose of further downsizing the memory cell of a DRAM in the future, a ferroelectric material with perovskite Crystal structure as a material for the dielectric film to use a capacitor.

Because a dielectric film of a capacitor made up of a such ferroelectric material with perovskite Crystal structure is made, however, to a Dielectric constant tends to decrease when the Film thickness is reduced, there is a reduction in accumulated charge in the capacitor, resulting in a significant impairment of the reliability of a corresponding semiconductor device leads.

In addition, the ferroelectric film of this type the generation of a leakage current is more likely since the Amount of oxygen in the film tends to be outside of the stoichiometric ratio of the dielectric material lie, and since the dielectric film is a relatively narrow  has prohibited tape. Therefore, if the dielectric film is becoming thinner, the function of the film is as dielectric material significantly affected, which again the reliability of the resulting Semiconductor memory device is affected.

An object of the present invention is therefore that of Providing a semiconductor device with a Capacitor is provided, softer a dielectric film of a capacitor which not only reduces the Dielectric constant can suppress, but also the Generation of a leakage current even if the dielectric Film is formed extremely thin.

Another object of the present invention is to Providing a method for manufacturing a such semiconductor device as above has been described.

According to the present invention, a Semiconductor device provided the one Semiconductor substrate and one on the semiconductor substrate trained capacitor, the capacitor a Has lower electrode, one on a surface of the bottom electrode formed dielectric film, as well an upper electrode provided on the dielectric film; the dielectric film has a film thickness of 100 nm or less, mainly consists of a metal oxide with a perovskite crystal structure of the ABO₃ type (the A is occupied by at least one metal ion, which is selected from the group consisting of Sr, Ba and Ca exists, and place B is occupied by a Ti ion),  and contains at least one element from the group is selected, which consists of Fe, Mn and Co.

According to the present invention, a DRAM is also used Provided, which has a semiconductor substrate; a MOS transistor provided on the semiconductor substrate, and a capacitor provided on the semiconductor substrate; wherein a memory cell-of the memory device by the MOS transistor and the capacitor that is formed Capacitor has a lower electrode, one on a Surface of the lower electrode provided dielectric Film, and an upper one provided on the dielectric film Electrode; the dielectric film has a film thickness of 100 nm or less, consists mainly of one Metal oxide with a perovskite crystal structure of the ABO₃ type (where space A is occupied by at least one metal ion which is selected from the group consisting of Sr, Ba and Ca exists, and place B is occupied by a Ti ion ) and contains at least one element from the group is selected, which consists of Fe, Mn and Co.

According to the present invention, there is further a method for manufacturing a semiconductor device having the following Steps Provided: Training a Lower Electrode on a semiconductor substrate; Training a dielectric film with a film thickness of 100 nm or less, consisting mainly of a metal oxide with ABO₃- Perovskite crystal structure exists (where the A through at least one metal ion is taken from the group is selected, which consists of Sr, Ba and Ca, and the place B is ingested by a Ti ion); Coating one Surface of the dielectric film with a solution that contains at least one element from the group  is selected, which consists of Fe, Mn and Co; Heat treatment of the dielectric film with the at least one element which is selected from the group consisting of Fe, Mn and Co, which means that at least one element in diffuses the dielectric film; and training one top electrode on a surface of the dielectric Film, whereby a capacitor is formed, which the lower electrode, the dielectric film and the upper one Includes electrode.

According to the present invention, there is further a method for manufacturing a semiconductor device having the following Steps Provided: Training a Lower Electrode on a semiconductor substrate; Manufactured by a CVD process or a sputtering process, a dielectric Film with a film thickness of 100 nm or less, the mainly from a metal oxide with ABO₃ perovskite Crystal structure exists (whereby the place A by at least a metal ion is selected that is selected from the group which consists of Sr, Ba and Ca, and the place B by a Ti ion is taken), and contains at least one element, which is selected from the group consisting of Fe, Mn and Co consists; and forming an upper electrode on a Surface of the dielectric film, creating a capacitor is formed, the lower electrode, the dielectric Film and the upper electrode includes.

Further objects and advantages of the invention are described in the given below description, result immediately from the description, or can be used in the implementation of the Find invention in practice. The goals and benefits of Invention can also be seen in the details and their  Achieve combinations, particularly in the attached Claims are specified.

The invention is illustrated below with reference to drawings illustrated embodiments explained in more detail, from which further advantages and features emerge. It shows:

Fig. 1 is a graph showing the relationship between the film thickness of a perovskite dielectric film and the dielectric constant of this film;

Fig. 2 is a diagram of the capacitance / field strength characteristics of a capacitor, for explaining the effects of the present invention;

Fig. 3 is a diagram showing a profile of Fe in a (Ba, Sr) TiO₃ film, measured by SIMS;

FIGS. 4A to 4D are cross-sectional views for explaining manufacturing steps of a DRAM cell according to a first embodiment of the invention;

FIGS. 5A to 5D respective cross-sectional views for explaining manufacturing steps of a DRAM cell according to a second embodiment of the invention;

Figs. 6A to 6D are cross-sectional views for explaining manufacturing steps of a DRAM cell according to a third embodiment of the invention; and

FIGS. 7A to 7E respective cross-sectional views for explaining manufacturing steps of a DRAM cell according to a fourth embodiment of the invention.

A semiconductor device according to the present invention is characterized in that it has a capacitor is provided which has a dielectric film whose Film thickness is 100 nm or less, and mainly from a metal oxide with ABO₃ perovskite crystal structure exists (where the place A by at least one metal ion is taken, which is selected from the group that consists of Sr, Ba and Ca, and place B by a Ti ion is taken), and contains at least one element which is selected from the group consisting of Fe, Mn and Co.

In terms of the concentration of the element or elements, that are selected from the group consisting of Fe, Mn and Co in the dielectric film should include this preferably in the range of 0.01% by weight to less than 10% by weight, particularly preferably in the range of 0.1% by weight to 5% by weight, and most preferably in the range of 1.0 wt% to 5 wt%. If the concentration of the element or the elements in the dielectric film less than Is 0.01 wt%, it may become difficult to obtain the Improve dielectric constant. If, on the other hand, the Concentration of the element or elements in the dielectric film is 10% by weight or more, the Insulation properties of the dielectric film be affected.  

A preferred range for the film thickness of the dielectric Film is 50 nm or less.

The inventors of the present invention have found that if a dielectric film consists mainly of one Metal oxide with an ABO₃ perovskite crystal structure (where space A is occupied by at least one metal ion which is selected from the group consisting of Sr, Ba and Ca exists, and place B is occupied by a Ti ion ) and contains at least one element, which consists of the Group is selected, which consists of Fe, Mn and Ca, as dielectric film of a capacitor is used, it is possible to obtain a capacitor that the Reduction in dielectric constant and generation of leakage currents can be suppressed even if the Capacitor is always formed thinner. The mechanism which is the basis of the present invention explained below.

It is known that a dielectric film with perovskite Crystal structure (hereinafter referred to as dielectric perovskite Film) it allows the metal ions that the Form crystal lattice of the perovskite crystal structure an internal electric field is significantly shifted, which leads to the generation of intense atomic polarization, which results in a high dielectric constant.

However, a dielectric generally occurs Perovskite film the problem on, as already above mentions that the dielectric constant of the film is the more the thinner the film gets, despite the fact that the dielectric perovskite film has a high  Dielectric constant can have if it as Solid or as a film with a large thickness.

Fig. 1 explains the relationship between the dielectric constant and the film thickness of a conventional type perovskite dielectric film and a perovskite dielectric film according to the present invention. The conventional dielectric perovskite film used here consisted of a composition Ba _0.5 , Sr _0.5 , TiO₃, whereas the dielectric perovskite film used here according to the invention consisted of a composition Ba _0.5 , Si _{0, 5} , Ti _0.99 , Fe _0.01 , O₃ consisted.

As is clear from Fig. 1, the conventional dielectric perovskite film showed a marked decrease in dielectric constant as the dielectric film becomes thinner, particularly in an area where the dielectric film is relatively thin. It can be concluded from this that, in the case of the conventional dielectric perovskite film, the advantages of increasing the capacitance of the dielectric film can hardly be expected with a thinning of the dielectric perovskite film even if the film thickness is reduced. In contrast, in the case of the dielectric perovskite film according to the present invention, the reduction in the dielectric constant is very small even if the film thickness is significantly reduced, and therefore a substantial improvement in the capacity increase of the dielectric film can be expected if the dielectric perovskite film is made thinner.

A dielectric perovskite film is generally like this constructed that a tetravalent metal ion, for example Ti,  is located in the center (place B) of the crystal lattice, a divalent metal ion at the top (place A) of the grid, and a two-valued, negative Oxygen ion is in the surface center of the lattice.

If there are any crystal defects, for example that Disappearance of these ions in this perovskite Crystal structure will occur, the balance of their electrical charges locally disrupted, and therefore occurs Generation of an electric field on this unbalanced Section on what training a high Dielectric constant of the dielectric perovskite film with special needs. The most serious problem in this case is a Defect that occur due to the loss of oxygen ions can, since this defect can become a donor site.

The addition of a metal ion, the valence of which varies distinguishes that of the metals which the perovskite Forming crystal structure can be effective in terms of the said imbalance of electrical charges turn off. This addition of a metal ion can the creation of an electric field in the dielectric Film caused by a deviation in the electrical charge is evoked, effectively suppressed so that it has now become possible to use a dielectric film for to provide a capacitor in which the Reduction of a dielectric constant can be prevented can, even if the dielectric film is extremely thin is formed, and which also has a high capacity for collecting electrical charges can maintain.

As described above, the generation of a high one Dielectric constant in the dielectric perovskite film  caused by a strong shift in the metal ions which comes from an internal electric field. However, the size of the shift of the metal ion is not necessarily proportional to the strength of the electrical Field. If the strength of the electric field is one exceeds certain limit, the size of the Displacement of a metal ion is not significantly increased, even when the electric field gets stronger. this leads to to make the value of the dielectric constant fast decreases when the applied voltage increases.

From these effects it is clear that if a electric field inside the dielectric film of the Capacitor is present, the dielectric constant of the dielectric film is significantly reduced overall even if no external voltage is applied to the film becomes. The reason for creating such an interior electrical field can mainly be lattice defects attributed to, for example, the loss of a Oxygen atom (or an oxygen vacancy), or one trapped electric charge.

If a carrier charge is present in the dielectric film carrier charge acts on the external electrical field and thereby causes the creation of an inner electric field via space charge effects. The generation of the Carrier charge in the dielectric film can also be caused loss of oxygen or a lattice defect.

The reason for the creation of this internal electric field can cause deformation at an interface between a Capacitor electrode and a dielectric film of the Capacitor can be attributed. Such a deformation  can easily be generated by damage that leads to Occurs when the capacitor electrode is formed, and it is believed that this damage is one of the reasons represents that the dielectric constant always becomes lower when the dielectric film of the capacitor is formed thinner.

If there is a lattice defect, for example one Oxygen vacancy in the dielectric film goes Electric charge neutrality in most cases lost. However, if an element is a metal ion forms, whose value differs from that of metals which distinguishes the dielectric perovskite film form the dielectric film in sufficient quantity is added, the neutrality of the electrical charge are effectively maintained, and therefore generation an internal electric field can be effectively prevented, while reducing the dielectric constant be effectively suppressed.

As an element that forms a metal ion, the particular is effective to compensate for the loss of oxygen one can be selected from metal elements, the Ion radius close to the ion radius of a tetravalent ion lies, for example Ti, which is located at the place B, and the value of which is +3 or +4. Specific examples of such metal elements are Fe, Mn and Co. In these, Fe and Mn are particularly preferred.

The ionic radius of Ti ⁴⁺ is 0.605 Å (10 Å equal to 1 nm). On the other hand, in the case of Fe, Mn and Co, their radius, measured for an ion with the coordination number 6: 0.645 Å (a state with high spin) or 0.55 Å (a state with low spin) in the case of Fe ³⁺ ; 0.586 Å in the case of Fe ⁴⁺ ; 0.645 Å (a high spin state) or 0.58 Å (a low spin state) in the case of Mn ³⁺ ; 0.53 Å in the case of Mn ⁴⁺ ; 0.61 Å (a high spin state) or 0.545 Å (a low spin state) in the case of Co ³⁺ ; and 0.535 Å in the case of Co ⁴⁺ . Therefore, the radius of each of these metal ions is close to the ion radius of Ti ⁴⁺ . If the ion radius of these metal ions is close to the value for Ti⁴, as explained above, these metal ions can simply serve as a replacement for the place of Ti.

If any of these elements in place from Ti to one becomes trivalent ion, so there is an electrical charge according to the value -1 at the place, so that the Loss of an oxygen atom through two atoms of these elements can be compensated. If there is no deviation from the electrical charge as in the event of loss of one Oxygen atom occurs, a tetravalent ion on this Space should be maintained so that the balance of the electrical charge can be maintained.

Fig. 2 shows the capacitance / voltage characteristic of a sample (present invention) in which Fe a thin film made of (Ba, Sr) TiO₃ was added, and a sample (prior art) in which such a thin film made of (Ba, SR) No Fe was added to TiO₃. As is clear from Fig. 2, when Fe is added to a thin film of (Ba, Sr) TiO₃, the dielectric constant of the film can be extremely improved.

As explained above, the addition of an ion which has a different value than that Metals that form the perovskite crystal structure  effective, the neutrality of an electrical charge To maintain crystal lattices. It also resulted in the studies carried out by the present inventors were carried out that such an ion preferably in an average concentration of 0.01 wt% or more should be added, particularly preferably 0.1% by weight or more about crystal defects such as the loss of a Oxygen atom in the dielectric film sufficiently compensate.

Since the additives according to the present invention have a Have a value of +3 or +4, it is possible that everyone additional additive in place B becomes quadrivalent, which in With regard to maintaining the balance of the electrical charges is advantageous. Furthermore you can think about any excess additive to fail is caused at the grain boundary, and so for stabilization contributes to a polycrystalline structure.

When a dielectric perovskite film is made a so-called remain in the dielectric film inner tension resulting from film making, and a thermal stress remaining from a difference of thermal expansion coefficient between the dielectric film and the underlying layer resulting in deformation in the crystal lattice is generated as a result of these tensions, and the Dielectric constant of the dielectric film reduced becomes.

However, as explained above, it is a trivalent one Ion such as an Fe ion is effective in causing deformation  to decrease in the grating, and the dielectric constant to increase.

If these additional substances in too large an amount added, there are negative effects. Therefore the present inventors have found that these Ions in an average concentration of 10% by weight or less should be added, particularly preferred 5% by weight or less. Because with most crystal defects, for example an oxygen loss, the generation at a Interface between the dielectric film and the Electrodes are more likely to like an additive Fe can be added in such a way that the concentration of the additives near the interface between the dielectric film and the electrodes gets bigger to this Make the best use of additives.

On the other hand, the problem of leakage current can also be solved because the cause of this problem, namely the Loss of oxygen atoms due to the trivalent ion can be compensated.

Fig. 3 shows a diagram showing the profile of Fe in a film of (Ba, Sr) TiO₃, as measured by SIMS (secondary ion mass spectrometry), the (Ba, Sr) TiO₃- film has a thickness of 70 nm, and is deposited on a Pt film. As is apparent from Fig. 3, the density of Fe is concentrated in an area near the surface of the (Ba, Sr) TiO₃ film compared to other areas. Since a defect such as the loss of an oxygen atom is more concentrated at an interface between the dielectric film and the electrodes, the profile shown in FIG. 3 can be considered desirable.

As explained above, it is according to the present Invention possible reducing the Suppress dielectric constants, as well as the generation a leakage current by adding one Metal element, which is a trivalent or tetravalent Metal ion in a perovskite-type metal oxide film Can provide so that this trivalent or tetravalent metal ion the tetravalent metal ion at place B replaced. Therefore, according to the invention it is now possible to to provide a semiconductor device which maintains high reliability even if the dielectric film of each capacitor is made extremely thin becomes.

The invention is described below with reference to various examples explained further.

(Example 1)

FIGS. 4A to 4D are sectional views illustrating steps for fabricating a DRAM cell according to a first embodiment of the invention. The DRAM cell obtained in this manufacturing process was constructed so that a capacitor was placed higher than a MOS transistor (a switching transistor), a word line and a bit line, with a (Ba, Sr) TiO₃ film with a small amount of Fe was used as the dielectric film of the capacitor.

As shown in Fig. 4A, a predetermined surface portion of a p-type monocrystalline silicon substrate having a main surface (a (100) crystal surface) and a resistivity of 10 Ω x cm was etched away, thereby forming a groove which an element insulation film 102 was then filled in so as to form an element insulation region. As an alternative to this, this element isolation area can also be produced using a LOCOS process.

Then, a silicon oxide with a thickness of 10 nm was produced by thermal oxidation, and then a tungsten silicide film was deposited thereon. These films were patterned by photolithography and reactive ion etching to form a gate insulating film 103 and a gate electrode 104 . Then, ion implantation was performed using this gate electrode 104 as a mask, thereby self-aligning forming a source / drain region formed by n⁻-type diffusion regions 105 and 106, respectively, thereby forming an n-channel MOSFET as a switching transistor.

Then, as shown in FIG. 4B, a silicon oxide film 107 was deposited by a CVD method in a thickness of 100 nm over the entire upper surface of the MOSFET, and a contact hole 108 was formed in the silicon oxide film 107 by means of photolithography and reactive ion etching.

Then, a titanium silicide film 109 was selectively formed on the n⁻-type diffusion regions 105 located at the bottom of the contact hole 108 , and a tungsten silicide film to be used as the bit line 110 was deposited over the entire upper surface of the device. Then, the tungsten silicide film was patterned using photolithography and reactive ion etching, thereby forming a bit line 110 .

Then, after a CVD oxide film 111 was deposited over the entire surface of the resulting device, as shown in FIG. 4C, the surface of the CVD oxide film 111 was flattened. A via 112 was then made photolithographically, and a first n⁺-type polycrystalline silicon film to be used as the lead-out electrode 113 was deposited over the entire upper surface of the resulting device. Then, a flattening method such as etching back was used so that only the portion of the first n⁺-type polycrystalline silicon film disposed in the contact hole 112 remained, thereby forming the lead-out electrode 113 .

Then, a Ti film 114 and a TiN film 115 as underlying layers for a lower capacitor electrode 116 and a Pt film as a lower capacitor electrode 116 were successively deposited over the entire surface of the device.

Then, these films 114 , 115 and 116 were patterned photolithographically to obtain the lower capacitor electrode 116 .

Then, a (Ba, Sr) TiO₃ film with a thickness of 20 nm, which contained about 1 wt .-% Fe, was deposited as the dielectric film 117 of the capacitor over the entire surface of the device by means of a sputtering process at a temperature of 550 to 700 ° C. The dielectric film 117 of the capacitor thus obtained had a perovskite structure of the ABO₃ type, in which Ba and Sr ions are located at position A, and a Ti ion is arranged at position B of the crystal lattice.

The addition of Fe to the (Ba, Sr) TiO₃ film can thereby ensure that Fe is built into a sputtering target beforehand, or by using a sputtering process with several Sources in which an Fe target or a target which Fe contains in a relatively high concentration, together with a Target is used, which contains no Fe.

Finally, as shown in Fig. 4D, a TiN film of 80 nm in thickness was deposited over the entire surface of the resulting device, and then patterned photolithographically to form an upper capacitor electrode (a plate electrode) 118 , thereby the basic structure of the DRAM cell was completed. In actual manufacturing, additional steps are performed, including a step to form Al wiring according to the usual procedures for completing a DRAM, which is not described in detail here.

In this example, a (Ba, Sr) TiO₃ film was used as dielectric film of the capacitor was used, and became Fe used as a metal additive. However, the present invention also use other materials.

For example, other materials such as SrTiO₃, BaTiO₃ or CaTiO₃ etc. as a dielectric film of Capacitor can be used instead of the (Ba, Sr) TiO₃ film. Furthermore, other materials can be used instead of Fe are, for example Mn, Co or a combination of Fe, Mn and Co.  

While Pt was used as the material for the lower capacitor electrode and TiN as the material for the upper capacitor electrode in this example, it is possible to use other conductive materials in the capacitor electrode. For example, a noble metal such as Pd, Ir, Rh, Ru and Au can be used as a material for a lower capacitor electrode, and also an oxide conductor such as ITO, RuO₂, BaRuO₃, SrRuO₃ (Ba, Sr) RuO₃ and Nb-doped SrTiO₃. On the other hand, a metal with a high melting point such as W, Mo or Ta, and a composite conductor such as WN _x , MoN _x or TaN _{x can be used} as the material for the upper capacitor electrode, in addition to the above-mentioned conductive materials.

(Example 2)

FIGS. 5A to 5D are sectional views for explaining manufacturing steps of a DRAM cell according to a second embodiment of the invention. The DRAM cell obtained by this manufacturing method was constructed so that a capacitor was arranged at a higher level than a MOS transistor (a switching transistor), a word line and a bit line, with a (Ba, Sr) TiO₃ film which contained a small amount of Mn instead of Fe as a dielectric film for the capacitor.

The essential feature in this example is that after forming a dielectric film one A capacitor with a perovskite crystal structure is a very small one Amount of Mn on the surface of the dielectric film and the resulting dielectric film has been subjected to heat treatment so that the adherent  Mn diffused into the dielectric film. The Heat treatment in this case also serves to improve the Crystal structure of the dielectric film so that the Diffusion of the metal and improvement of the Crystal structure together in a single step what can be done to the procedure overall simplified.

First, as shown in Fig. 5A, a predetermined surface portion of a p-type monocrystalline silicon substrate 201 having a main surface (a (100) crystal surface) and a resistivity of 10 Ω cm was etched away, thereby forming a groove in which an element insulation film 202 was then filled in to form an element insulation region. Alternatively, this element isolation area can also be produced using a LOCOS process.

Then, a silicon oxide film with a thickness of 20 nm was produced by thermal oxidation, and then a tungsten silicide film was deposited thereon. These films were patterned by photolithography and reactive ion etching to form a gate insulating film 203 and a gate electrode 204 . Then, ion implantation was performed using this gate electrode 204 as a mask, thereby self-aligning a source / drain region formed by n + type diffusion regions 205 and 206 , thereby producing an n-channel MOSFET as a switching transistor.

Then, as shown in FIG. 5B, a silicon oxide film 207 was deposited to a thickness of 100 nm over the entire upper surface of the MOSFET using a CVD method, and a contact hole 208 was formed in the silicon oxide film 207 by means of photolithography and reactive ion etching.

Then, a titanium silicide film 109 was selectively formed on the n⁻-type diffusion regions 205 located at the bottom of the contact hole 208 , and a tungsten silicide film was deposited over the entire surface of the device. Then, the tungsten silicide film was patterned using photolithography and reactive ion etching, thereby producing a bit line 210 .

Then, after a CVD oxide film 211 was deposited on the entire surface of the resulting device, as shown in FIG. 5C, the surface of the CVD oxide film 211 was flattened. Then, a contact hole 212 was photolithographically formed, and a first n⁺-type polycrystalline silicon film was deposited over the entire upper surface of the resulting device. Then, a flattening process such as etching back was used, so that only a portion of the first n⁺-type polycrystalline silicon film remained, which was disposed in the contact hole, thereby forming an outlet electrode 213 .

Then, a Ti film 214 and a TiN film 215 were deposited successively on the entire surface of the device as underlayers for a lower capacitor electrode 216 and a Pt film to serve as a lower capacitor electrode 216 .

Then, these films 214 , 215 and 216 were patterned photolithographically to obtain the lower capacitor electrode 216 .

Then, as shown in Fig. 5D, a (Ba, Sr) TiO₃ film 217 with a thickness of 20 nm over the entire surface of the device was produced by means of a sputtering process at a temperature of 500 to 700 ° C. Then the surface of the (Ba, Sr) TiO₃ film 217 was coated with a solution 200 which contained 0.1% by weight of Mn, and allowed to dry. The resultant device was then subjected to a heat treatment at a temperature of 700 ° C, so that the piled Mn in the (Ba, Sr) TiO₃ film improved 217 hineindiffundierte, and at the same time the crystal structure of the (Ba, Sr) TiO₃ film 217 has been.

Finally, a 80 nm thick TiN film was deposited over the entire surface of the resulting device, and then patterned photolithographically to form an upper capacitor electrode (plate electrode) 218 , thereby completing the basic construction of the DRAM cell was. Additional steps are included in actual manufacturing, including a step of forming Al wiring according to the usual procedure for completing a DRAM, which procedure is not described again here.

In this example, a (Ba, Sr) TiO₃ film was used as dielectric film of the capacitor was used, and was Mn used as a metallic additive. However, leave other materials in the present invention use.  

For example, other materials such as SrTiO₃, BaTiO₃ or CaTiO₃ and the like as a dielectric film for the Capacitor can be used instead of the (Ba, Sr) TiO₃ film. Furthermore, other materials can be used instead of Mn use, for example Fe, Co or a combination of Fe, Mn and Co.

A solution containing Mn was applied to the surface of the dielectric film for the capacitor in the above described example applied so that Mn in the was able to diffuse in the dielectric film of the capacitor, however, the Mn-containing solution can also be applied to the surface a lower capacitor electrode to be stacked so attach it to this Mn, and then it becomes a dielectric Film of the capacitor of this lower capacitor electrode, the Mn contains, superimposed so that the adhering Mn in the dielectric film of the capacitor are diffused can.

Pt was used as the lower capacitor electrode and TiN as the upper capacitor electrode in this example, but it is possible to use other conductive materials as the capacitor electrode. For example, a noble metal such as Pd, Ir, Rh, Ru and Au can be used as the lower capacitor electrode, and also an oxide conductor such as ITO, RuO₂, BaRuO₃, SrRuO₃, (Ba, Sr) RuO₃ and Nb-doped SrTiO₃. On the other hand, in addition to the conductive materials described above, a metal having a high melting point, for example W, Mo or Ta, or a composite conductor such as WN _x , MoN _x or TaN _x can be used as the upper capacitor electrode.

(Example 3)

FIGS. 6A to 6D respectively show sectional views for explaining manufacturing steps for manufacturing a DRAM cell according to a third embodiment of the present invention. The DRAM cell obtained in this manufacturing method was of the transistor and capacitor type, which is suitable for increasing the integration density, and was constructed so that a capacitor was arranged at a higher level than a MOS transistor (a switching transistor), one Word line and a bit line, a (Ba, Sr) TiO₃ film containing a small amount of Fe being used as the dielectric film for the capacitor.

As shown in Fig. 6A, a predetermined surface portion of a p-type monocrystalline silicon substrate 301 having a main surface (a crystal face ( 100 )) and a resistivity of 10 Ω x cm was etched away, thereby forming a groove in which is then filled with an element insulating film 302 so as to form an element insulating region. As an alternative to this, this element insulation area can also be produced using a LOCOS process.

Then, a silicon oxide film having a thickness of 10 nm was formed by thermal oxidation, and then a tungsten silicide film was deposited thereon to serve as the gate electrode 304 . These films were then patterned using photography and reactive ion etching to form a gate insulating film 303 and a gate electrode 304 . Then, ion implantation was performed using this gate electrode 304 as a mask, thereby self-aligning to form a source / drain region composed of n⁻-type diffusion regions 305 and 306 , thereby forming an n-channel MOSFET as a switching transistor.

Then, as shown in FIG. 6B, a silicon oxide film 307 was deposited to a thickness of 100 nm over the entire upper surface of the MOSFET using a CVD method, and a contact hole 308 was formed in the silicon oxide film 307 by means of photolithography and reactive ion etching.

Then, a titanium silicide film 309 was selectively formed on the n⁻-type diffusion regions 305 located on the bottom of the contact hole 308 , and a tungsten silicide film to be used as the bit line 310 was deposited over the entire upper surface of the device. The tungsten silicide film was then patterned using photolithography and reactive ion etching, thereby forming a bit line 310 .

Then, after a CVD oxide film 311 was deposited over the entire surface of the resulting device, as shown in FIG. 6C, the surface of the CVD oxide film 311 was flattened. Then, a contact hole 312 was photolithographically formed, and a first n⁺-type polycrystalline silicon film was deposited over the entire upper surface of the resulting device. Then, using a flattening method such as etching back, only a portion of the first n⁺-type polycrystalline silicon film remained, which was disposed in the contact hole 312 , thereby producing the outlet electrode 313 .

Then, a Ti film 314 and a TiN film 315 as underlayers for a lower capacitor electrode 316 and a RuO₂ film, which was to serve as a lower capacitor electrode 316 , were successively deposited over the entire surface of the device.

Then, these films 314 , 315 and 316 were patterned photolithographically so as to obtain the lower capacitor electrode 316 .

Then a (Ba, Sr) TiO₃ film with a thickness of 20 nm as the dielectric film 317 of the capacitor was produced over the entire surface of the device by means of a CVD method. Here, a CVD raw material for the (Ba, Sr) TiO₃ film and a CVD raw material for Fe were simultaneously fed, so that 0.1 to 1.0 wt .-% Fe in the (Ba, Sr) TiO₃ film in this step of film education.

Then, if desired, the resulting dielectric film 317 of the capacitor may be subjected to a heat treatment. In the present example, the (Ba, Sr) TiO₃ film was subjected to a heat treatment at a temperature of 700 ° C to thereby stabilize the Fe in the (Ba, Sr) TiO₃ film and at the same time to improve the crystal structure of the film.

Finally, as shown in Fig. 6D, a WN _x film with a thickness of 80 nm, which was later to be used as the upper capacitor electrode (a plate electrode) 318 , was deposited over the entire surface of the resulting device, and then photolithographically patterned to form the upper capacitor electrode 318 , thereby completing the basic structure of the DRAM cell. In the actual manufacturing, additional steps are performed including the step of forming Al wiring according to the usual procedure for completing a DRAM, which will not be described again here.

In this example, a (Ba, Sr) TiO₃ film was used as dielectric film of the capacitor was used, and became Fe used as a metal additive. However, at use other materials of the present invention.

For example, other materials such as SrTiO₃, BaTiO₃, CaTiO₃ or a mixture of these substances as a dielectric Film of the capacitor can be used instead of the (Ba, Sr) TiO₃- Films. Furthermore, other materials such as Mn, Co or any combination of Fe, Mn and Co instead of Fe be used.

RuO₂ was used as the lower capacitor electrode, and WN _x as the upper capacitor electrode, in this example, however, it is possible to use other conductive materials as the capacitor electrode. For example, a noble metal such as Pt, Pd, Ir, Rh and Au can be used as the lower capacitor electrode, and also an oxide conductor such as ITO, BaRuO₃, SrRuO₃, (Ba, Sr) RuO₃ and Nb-doped SrTiO₃. On the other hand, a high melting point metal such as W, Mo or Ta, or a composite conductor such as TiN, MoN _x or TaN _x can be used as the upper capacitor electrode, in addition to the conductive materials described above.

(Example 4)

FIGS. 7A to 7E are sectional views for explaining manufacturing steps of a DRAM cell according to a fourth embodiment of the present invention. This example describes a method of manufacturing a DRAM cell of the transistor and capacitor type, in which a transistor and a capacitor are separately fabricated on a separate semiconductor substrate, then overlaid on each other and connected together.

This example is characterized in that a dielectric perovskite film called dielectric film a capacitor is to be used, with the help of a Sputtering was generated, and that a metal, which a trivalent or tetravalent metal ion is available can put in the dielectric perovskite film during the Step of manufacturing the dielectric film Sputtering was introduced. More specifically, one was ((Ba, Sr) TiO₃ film containing a very small amount of Fe was added as the dielectric film of the capacitor used.

Then there was a semiconductor substrate on which a transistor was arranged, and a semiconductor substrate on which a Capacitor was stacked on top of one another Form DRAM cell.

First, as shown in Fig. 7A, a predetermined surface portion of a p-type monocrystalline silicon substrate 401 having a main surface (a (100) crystal surface) and a resistivity of 10 Ω cm was etched away, thereby forming a groove into which thereupon an element isolation area has been filled in to form an element isolation area. Alternatively, this element isolation area can also be produced by a LOCOS process.

Then, a silicon oxide film with a thickness of 10 nm was produced by thermal oxidation, and a tungsten silicide film was deposited thereon. These films were patterned photolithographically and by reactive ion etching to form a gate insulating film 403 and a gate electrode 404 . Then, with this gate electrode 404 as a mask, ion implantation was performed, thereby self-aligning to form a source / drain region composed of diffusion regions 405 and 406 of the n⁻ type, thereby forming an n-channel as a switching transistor.

Then, as shown in Fig. 7B, a silicon oxide film 407 was deposited by a CVD method in a thickness of 100 nm over the entire upper surface of the MOSFET, and a contact hole 408 was formed in the silicon oxide film 407 so that it was in contact with the diffusion region 404 of the n⁻ type was related, using photolithography and reactive ion etching.

Then, a titanium silicide film 409 was selectively deposited on the n⁻-type diffusion regions 405 located on the bottom of the via 408 , and a tungsten silicide film was deposited over the entire upper surface of the device. Then, the tungsten silicide film was patterned by means of photolithography and reactive ion etching, whereby a bit line 410 was formed.

Then, a CVD oxide film 411 was deposited over the entire surface of the resulting device.

Then, after a contact hole 412 was formed by photolithography as shown in FIG. 7C, an n ein-type polycrystalline silicon film was deposited over the entire upper surface of the resulting device by an LPCVD method. Then, by a flattening process such as etching back, only that portion of the n + type polycrystalline silicon film remaining in the contact hole 412 was left, thereby producing an outlet electrode 413 .

Then, a titanium silicide film 414 and a TiN film 415 were successively deposited on the entire surface of the device, and then patterned photolithographically. Then, a silicon oxide film 416 was formed on the entire surface of the substrate by a CVD method using TEOS and 03 as raw material gases, and then this silicon oxide film 416 was polished by a CMP method until the surface of the TiN film 415 exposed, which leveled the surface of the substrate.

As a result of these steps, a first Semiconductor substrate obtained, which is a MOS transistor who worked as a switching transistor.

Film 418 nm with a thickness of 50, a Ti film 419 nm with a thickness of 20 and a 50 nm thick - then a separate silicon substrate 417, as shown in Figure a TiSi _x N _y were on the whole surface 7D. Pt film that should serve as the lower capacitor electrode 420 is formed.

Then, a (Ba, Sr) TiO₃ film with a thickness of 20 nm, which contained about 1 wt .-% Fe, was produced as a dielectric film 421 of a capacitor over the entire surface of the substrate 417 by means of a sputtering process. In the present example, a sputtering process with multiple sources was used, using two different targets for the production of the dielectric film 421 for the capacitor, namely a target for (Ba, Sr) TiO₃, and another target for Fe.

A Pt film 50 nm thick was then formed over the entire surface of the dielectric film 421 of the capacitor, and then patterned using photolithography and reactive ion etching in a well known manner to form the upper capacitor electrode 422 .

Then, a silicon oxide film 423 was formed over the entire surface of the substrate by a CVD method using TEOS and O₃ as a raw material gas, and then this silicon oxide film 423 was polished by a CMP method until the surface of the upper capacitor electrode 422 was exposed, thereby leveling the surface of the substrate.

As a result of these steps, a second Semiconductor substrate obtained, which carried a capacitor.

Then, the first semiconductor substrate and the second semiconductor substrate were stacked so that the TiN film 415 existing on the first semiconductor substrate was overlaid on the upper electrode 422 arranged on the second semiconductor substrate to obtain a laminate arrangement with which then a heat treatment was carried out at a temperature of 900 ° C, whereby these two semiconductor substrates were attached to each other.

Finally, the silicon substrate 417 , which formed the second semiconductor substrate, was etched away to obtain the basic structure of a DRAM cell. In the actual manufacturing, additional steps are performed including a step of manufacturing Al wiring according to the usual procedure for manufacturing a DRAM, but this will not be described again in detail here.

In the present example, a ((Ba, Sr) TiO₃ film as dielectric film of the capacitor was used, and became Fe used as a metallic additive. However, at other materials are also used in the present invention will.

For example, other materials, such as SrTiO₃, BaTiO₃ or CaTiO₃, as a dielectric film for the capacitor are used instead of the (Ba, Sr) TiO₃ film. Farther other materials can be used instead of Fe, such as Mn, Co or any combination of these substances.

The introduction of Fe into the dielectric film for the Capacitor can coexist with the formation of the dielectric film for the capacitor are performed as in the case of Examples 1 and 2, or can thereby be performed that a diffusion in the dielectric Film of the capacitor after the manufacture of the dielectric Film is done for the capacitor. In addition, any  other suitable methods for introducing Fe into one dielectric film of a capacitor can be used.

Although Pt was used as the lower capacitor electrode and TiN was used as the upper capacitor electrode in the present example, it is possible to use other conductive materials to form the capacitor electrode. For example, a noble metal can be used as the lower capacitor electrode, for example Pd, Ir, Rh, Ru and Au, and also an oxide conductor such as ITO, RuO₂, BaRuO₃, SrRuO₃, (Ba, Sr) RuO₃ and Nb-doped SrTiO₃. On the other hand, a high melting point metal such as W, Mo or Ta, or a composite conductor such as WN _x , MoN _x or TaN _x , can be used as the upper capacitor electrode, in addition to the above-mentioned conductive materials.

The invention is of course not on the limited examples above. It was a CVD process or a sputtering process for manufacturing a dielectric film of a capacitor both previous examples used, but instead of this Sol-gel processing can also be used. If sol-gel processing is to be used, a predetermined amount of one of the above Metal elements, for example Fe, added to a sol, and then the resulting sol becomes a heat treatment performed to crystallize the sol.

According to the present invention, since an insulating thin film, which mainly consists of a metal oxide, which is a Perovskite crystal structure of the ABO₃ type, in which predetermined ions are arranged at the A place and B place,  and the film contains a predetermined metal element, as dielectric film of a capacitor is used, it is as explained above, the reduction in Dielectric constants and the generation of a leakage current to suppress even if the dielectric film of the Capacitor is made extremely thin.

Professionals in the field will see additional benefits and benefits Changes are noticed immediately. Therefore, the invention is in their overall aspect not on the specific details, exemplary devices and illustrated examples limited, which were presented and described here. Therefore can be made various changes without the Deviate essence or scope of the invention resulting from the All of the present application documents result, and from the appended claims are intended to be included.

Claims (20)

1. Semiconductor device with:
a semiconductor substrate; and
a capacitor provided on the semiconductor substrate;
wherein the capacitor has a lower electrode, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film,
characterized in that the dielectric film ( 117 ) has a film thickness of 100 nm or less, mainly consists of a metal oxide which has a perovskite crystal structure of the ABO₃ type (the space A being occupied by at least one metal ion which is derived from the Group is selected, which consists of Sr, Ba and Ca, and the place B is occupied by a Ti ion), and contains at least one element selected from the group consisting of Fe, Mn and Co. 2. Semiconductor device according to claim 1, characterized in that the concentration of the element in the dielectric film ( 117 ) is in the range of 0.01 wt .-% to less than 10 wt .-%. 3. A semiconductor device according to claim 1, characterized in that the concentration of the element in the dielectric film ( 117 ) is in the range of 0.1% by weight to 5% by weight. 4. A semiconductor device according to claim 1, characterized in that the film thickness of the dielectric film ( 117 ) is 50 nm or less. 5. The semiconductor device according to claim 1, characterized in that the concentration of the element in a region adjacent to an interface between the dielectric film ( 117 ) and at least one of the lower electrode ( 116 ) and the upper electrode ( 118 ) is higher than in other regions . 6. A semiconductor device according to claim 1, characterized in that the dielectric film ( 117 ) has as main component (Ba, Sr) TiO₃, which contains Fe. 7. Semiconductor device according to claim 1, characterized in that the lower electrode ( 116 ) comprises a material which is selected from the group consisting of Pt, Pd, Ir, Rh, Ru, Au, indium / tin oxide, RuO₂, BaRuO₃, SrRuO₃ and Nb-doped SrTiO₃ exists. 8. A semiconductor device according to claim 1, characterized in that the upper electrode ( 118 ) comprises a material which is selected from the group consisting of Pt, Pd, Ir, Rh, Ru, Au, indium / tin oxide, RuO₂, BaRuO₃, SrRuO₃, Nb-doped SrTiO₃, W, Mo, Ta, WN _x , MoN _x , TiN and TaN _x . 9. Dynamic random access memory device with:
a semiconductor substrate;
a MOS transistor provided on the semiconductor substrate; and
a capacitor provided on the semiconductor substrate;
wherein a memory cell of the memory device is formed by the MOS transistor and the capacitor;
wherein the capacitor has a lower electrode, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film,
characterized in that the dielectric film ( 117 ) has a film thickness of 100 nm or less, mainly consists of a metal oxide which has a perovskite crystal structure of the ABO₃ type (wherein the space A is occupied by at least one metal ion derived from the Group is selected, which consists of Sr, Ba and Ca, and place B is occupied by a Ti ion), and contains at least one element selected from the group consisting of Fe, Mn and Co. 10. A dynamic random access memory device according to claim 9, characterized in that the concentration of the element in the dielectric film ( 117 ) is in the range of 0.01% to less than 10% by weight. 11. A dynamic random access memory device according to claim 9, characterized in that the concentration of the element in the dielectric film ( 117 ) is in the range of 0.1% to 5% by weight. 12. A dynamic random access memory device according to claim 9, characterized in that the film thickness of the dielectric film ( 117 ) is 50 nm or less. 13. A dynamic random access memory device according to claim 9, characterized in that the concentration of the element is higher in an area adjacent to an interface between the dielectric film ( 117 ) and at least one of the lower electrode ( 116 ) and the upper electrode ( 118 ) than in other areas. 14. Dynamic random access memory device according to claim 9, characterized in that the dielectric film ( 117 ) contains as main component (Ba, Sr) TiO₃, which contains Fe. 15. A dynamic random access memory device according to claim 9, characterized in that the lower electrode ( 116 ) contains a material selected from the group consisting of Pt, Pd, Ir, Rh, Ru, Au, indium / tin oxide, RuO₂, BaRuO₃, SrRuO₃ and Nb-doped SrTiO₃. 16. A dynamic random access memory device according to claim 9, characterized in that the upper electrode ( 118 ) comprises a material selected from the group consisting of Pt, Pd, Ir, Rh, Ru, Au, indium / tin oxide, RuO₂, BaRuO₃, SrRuO₃ and Nb-doped SrTiO₃, W, Mo, Ta, WN _x , MoN _x , TiN and TaN _x . 17. A method of manufacturing a semiconductor device comprising the following steps:
Forming a lower electrode ( 116 ) on a semiconductor substrate ( 101 );
Forming a dielectric film ( 117 ) on the lower electrode, the dielectric film having a film thickness of 100 nm or less, and mainly made of a metal oxide having a perovskite crystal structure of the ABO₃ type (wherein the space A by at least one Metal ion is selected, which is selected from the group consisting of Sr, Ba and Ca, and the place B is occupied by a Ti ion);
Coating a surface of the dielectric film with a solution containing at least one element selected from the group consisting of Fe, Mn and Co;
Performing heat treatment of the dielectric film ( 117 ) coated with at least one element selected from the group consisting of Fe, Mn and Co, whereby the at least one element diffuses into the dielectric film ( 117 ); and
Forming an upper electrode ( 118 ) of the dielectric film, thereby forming a capacitor having the lower electrode ( 116 ), the dielectric film ( 117 ) and the upper electrode ( 118 ). 18. A method of manufacturing a semiconductor device according to claim 17, characterized in that the concentration of the element in the dielectric film ( 117 ) is in the range of 0.01 wt% to less than 10 wt%. 19. A method of manufacturing a semiconductor device comprising the following steps:
Forming a lower electrode ( 116 ) on a semiconductor substrate ( 101 );
Formation by means of a CVD process or a sputtering process, a dielectric film ( 117 ) on the lower electrode, the dielectric film having a film thickness of 100 nm or less, mainly consisting of a metal oxide which has a perovskite crystal structure of the ABO₃ type (where A is occupied by at least one metal ion selected from the group consisting of Sr, Ba and Ca and B is occupied by a Ti ion) and contains at least one element made of selected from the group consisting of Fe, Mn and Co; and
Forming an upper electrode ( 118 ) on the dielectric film ( 117 ), thereby forming a capacitor having the lower electrode ( 116 ), the dielectric film ( 117 ) and the upper electrode ( 118 ). 20. A method of manufacturing a semiconductor device according to claim 19, characterized in that the concentration of the element in the dielectric film ( 117 ) is in the range of 0.01 wt% to less than 10 wt%.