DE19527592C2 - Cache arrangement for a processor and method for entering data into a cache memory - Google Patents

Description

The invention relates to a cache arrangement for a Processor, with a cache memory for the processor, with an address directory belonging to the cache memory and with a buffer memory for the temporary storage of Rows of data. The invention further relates to a process for Entry of data into a cache memory.

Processor systems with one are from the prior art or several microprocessors known, in which so-called Cache memory can be used. Caches are fast Data storage, i.e. those with a short access time, the are generally located near a processor and serve to supplement the main memory of the system. In the Cache storage becomes a subset of the storage contents of the Main memory of the processor system stored by the Processor to which the respective cache memory belongs, are used particularly often. As a result, the Access time to data is reduced overall and one better efficiency of the system bus is guaranteed.

It is also known from the prior art, two or to provide multiple levels of cache memory, e.g. B. one so-called L1 cache and an L2 cache. To address the Data is already known, the data line by line save. A data line can then e.g. B. 128 bytes of data include. If a data line from the main memory of the Processor system is requested, so they become the requested data line related data generally in several "packets" from main memory to the L2 cache and transferred from the L2 cache to the L1 cache, e.g. B. in 8 "Packets" of 16 bytes each.

The processor that requested the data line needs typically only a few bytes of the total  128 bytes of the data line. The statistical one High probability that the byte Positions within the data line are adjacent. the one sixteen byte "packet" of the relevant data line, which contains the required byte positions is therefore transmitted first so that the processor after as low as possible Waiting time can continue to work. With the following ones Data transfers via the system bus are then the remaining "packets" transmitted.

When transferring the "packets" from the L2 cache to the L1 The cache that follows after the first "package" will be seven "packets" initially in a buffer memory cached. This is particularly necessary if immediately after the transmission of the first package the Processor processes the data of this packet and if it is the L1 cache is a so-called single-port array, which means that only one system participant at a time can access the L1 cache. As long as the processor with communicates its L1 cache, is therefore the L1 cache for the Storage of the other seven "packets" of 16 bytes of data each blocked. This data remains in the buffer memory for as long until the L1 cache is accessible for storing these "packets" is.

The first "package" that was initially created by the processor contains the required byte positions, can be within of a system cycle are both stored in the L1 cache as well as from the L1 cache to the processor. This is particularly possible if the L1 Cache is a so-called "write-through" cache the input data at the port of the L1 cache at the end of the system cycle in which the first "packet" in which L1 cache has been saved.

The following can occur when operating such a processor system Disadvantage arise: After the processor first Get requested byte positions with the first "packet" , it happens that the processor immediately follows  further byte positions of the same data line, which are in one or more of the other seven "packages", needed. However, these other "packages" are located too at this time not in the L1 cache but still in the buffer memory. Accordingly, the address of the relevant packets of the data line also in the Address directory for the control of the buffer memory registered. This registration means that the data line is already entered as valid in the cache directory, the package in question is not yet stored in the L1 cache has been.

Registration of the address or the addresses of the packages in the address directory of the L1 cache happens according to the status the technology only when the relevant data line is completely stored in the L1 cache. This will ensures the consistency of the data in the processor system.

The request for data in the other seven "Packets" are included in the L1 cache as long as they are not satisfied than the corresponding one Package in which the L1 cache is stored. A corresponding Requesting the processor before saving therefore results to a so-called line fetch buffer (LFB) conflict.

In this case, the processor must have access to the L1 Wait until the corresponding packet cache is saved. This goes through several system cycles for the Processing of instructions lost by the processor. In a so-called "pipelined" architecture is about In addition, the processing of instructions that are already in the "pipeline" are interrupted or delayed so that this results in further losses. Likewise, for Rebuilding the "pipeline" required some system cycles.

A "fast path" is known from US Pat. No. 4,654,778 to bypass intermediate levels in the storage hierarchy serves. The "Fast Path" is used in the system to control the Peak loads on the normal data path through the  Reduce storage hierarchies.

US Patent No. 4,445,174 shows a multiprocessor system main memory, L1 and L2 caches, each one of processors, and a "shared cache" that none the processors are assigned "privately", but to all Processors can access equally. The so-called "Shared cache" is used to further reduce Access times.

From US Patent No. 5,214,766 is a multiprocessor system known that also a "shared cache" for optimization which has access time. In addition, this points Multiprocessor system on a table in which the type and How a line of data is used by one of the Processors is registered. That is also supposed to Serve to optimize access times.

In the above prior art, the problem described above is the Access to "packets" that are already in the buffer, but not yet in the L1 cache, neither recognized still resolved.

US Patent 5,367,660 shows an improved cache for Use in a microprocessor system. A buffer storage saves tag and offset fields and the associated ones Data line. So-called valid bits are different Linked parts of the data row. Restricted to the reader This device allows access to processor instructions, that, while filling the data line with processor Instructions, processor instructions from the buffer memory can be read before the data line is completely through Main memory content is filled.

The invention is therefore based on the object, the use to make a buffer storage even more efficient.

The object underlying the invention is achieved by the in the features listed in the independent claims  solved.

The advantages achieved with the invention are in particular in that the processor waits for the full Storage of a line of data in the cache memory is eliminated, if the processor is on data within that data line want to access while the data row in question is still is not completely stored in the cache memory, but some of the "packets" of the data line are still in the Processor system buffer memory. That has continued the advantage that in this situation there is also an interruption the "pipeline" is not required.  

The invention is also particularly advantageous if Data from the processor is stored in the L1 cache should. For such storage it is according to the state of the Technique required that the corresponding data line in the L1 cache already exists so that the affected byte Positions of the data line in the L1 cache are overwritten can. This line of data is not yet in the L1 cache completely present, so it is now according to the teaching of Invention possible that are still in the buffer memory Data for performing this save operation consulted. For this, the "package" in the Buffer memory, which contains the affected byte positions contains, from the buffer memory into a multiplexer output. The multiplexer also receives the changed, data to be stored by the processor as well Control signal.

The multiplexer is switched by the control signal so that the byte positions to be overwritten by the Output buffer memory and this corresponding byte Replace positions while the remaining byte positions of the "Package" output from the buffer memory unchanged stay. The result is at the output of the multiplexer "Package" that already contains the changed data. This already changed "package" is then - as usual - in the L1 cache saved. In comparison to the prior art thereby avoided that initially the unchanged "package", such as it has been buffered in the buffer memory, unchanged must be stored in the L1 cache so that the byte positions to be changed in the relevant data line of the L1 cache can be overwritten.

The invention is also for fetching operands for the Processor advantageous. If, for example, to a Instruction two operands can belong based on the addresses of the operands are checked whether the second operand is data from another of the "packets" on the same row of data as the first operand required. This is particularly the case with one so-called carry of addresses the case. If such  Carry occurs, the data of the second operand can be combined with the corresponding "package" from the buffer memory are output and via the L1 cache in the processor can be entered. It is compared to the state of the Technology not required on full storage the appropriate line of data to wait for the processor can also access the second operand. This is what Use of a so-called write-through L1 cache memory required so that both the Saving the "package" as well as the output of the in the "Packet" contained data on the only port of the L1 Caches to the processor is possible.

An embodiment of the invention is in the drawing shown and is described in more detail below. Show it

Fig. 1, the line-wise organization of the address space;

FIG. 2 shows the addressing of individual byte positions within a data row;

Fig. 3 is a simplified block diagram of a processor system according to the invention;

Fig. 4 is a signal diagram for carrying out a memory operation by the processor to the L1 cache;

Fig. 5 is a signal diagram for the input of two operands, which are in different "packets".

In Fig. 1 of the addressing space 1 is illustrated the processor system. The addressing space 1 consists of the data lines Z0, Z1, Z2, Z3,. , ., Zn - 1. Each of the data lines Z has a width of 128 bytes. Furthermore, each of the data lines Z is logically divided into 8.16 tuples, that is to say into the 16 byte wide tuples S0, S1, S2, S3, S4, S5, S6 and S7.

Fig. 2, the addressability shows a single byte within a data line Zi. The variables X, Y and Z represent 3 address bits for specifying one of the 16-tuples within the respective data line Zi. The 3 bit positions X, Y and Z are sufficient for the Addressing of the 8 different 16 tuples within the data line Zi. Since each of the 16 tuples is 16 bytes wide, a further four address bits 2 are required for byte-precise addressing within a 16 tuple.

Fig. 3 is a block diagram showing a processor system according to the invention. The microprocessor PU of the system itself is not shown in FIG. 3. The processor PU has an L1 cache 3 (L1 CACHE). The port of the L1 cache memory 3 is connected to an interface 4 . Interface 4 is a so-called FETCH ALIGNER. This is used for the orderly output of data from the L1 cache memory 3 to the FETCH bus 5 . The FETCH bus 5 is a data bus and connects the interface 4 and therefore indirectly the L1 cache memory 3 to the processor PU.

Output data from the L1 cache 3 reach the processor PU via the FETCH bus 5 in order to be input into the processor PU. An address directory 6 , a so-called cache directory, belongs to the L1 cache memory 3 . The address directory 6 consists of registers for storing addresses. If the address Zi of a data line is registered in one of the registers in the address directory 6 , this means for the processor PU that the data line of the address Zi is present in the L1 cache memory 3 . This will be explained in more detail below.

The address directory 6 is connected to the L1 cache memory 3 via a signal line 7 . As soon as a data line Zi is to be stored in the L1 cache memory 3 , this is indicated to the address directory 6 via the signal line 7 , so that the corresponding registration in the address directory 6 of the address i of the data line Zi to be stored can be carried out. According to the invention, the address i of this data line is registered in the address directory 6 before the data lines Zi are completely stored in the L1 cache memory 3 .

The processor system also has an L2 cache 8 (L2 CACHE). The L2 cache 8 is connected to the main memory of the processor system via the system bus. Both the main memory and the system bus are not shown in FIG. 3. The L2 cache memory 8 is connected to a buffer memory 10 via a bus 9 . The bus 9 is wide in the embodiment of Fig. 3 sixteen bytes, which is the width of the 16-tuples of a data row corresponds to (see. Fig. 1 and Fig. 2). If a data line Zi is to be transferred from the L2 cache 8 to the L1 cache 3 , the eight 16 tuples of the data line Zi are transmitted sequentially in 8 "packets" of 16 bytes each via the bus 9 .

For example, the data line Zi can be output from the L2 cache 8 because the processor PU requires data which are contained in the 16 tuple S3 of the data line Zi. Then the first "packet" is the 16 tuple S3 from the L2 cache 8 and is transmitted via the bus 9 . However, this first "packet" is not temporarily stored in the buffer memory 10 , the so-called line fetch buffer, but is transmitted directly via the bus 11 , the multiplexer 12 and the bus 13 to the port of the L1 cache memory 3 . The L1 cache 3 is a so-called write-through cache. This means that data that is created for storage at the "DataIn" of the only port of the L1 cache memory is already available at the "DataOut" of the only port of the L1 cache memory within the same cycle.

Therefore, the first "packet", that is, the 16-tuple S3, which contains the data first required by the processor PU, can be stored in the L1 cache memory 3 as well as via the interface 4 and the system bus 5 within a system cycle Processor PU are transmitted.

Since the L1 cache memory 3 is a so-called single-port array (only 1 port is available for accessing the L1 cache memory 3 ), the further "packets" that correspond to the remaining 16 tuples of the data line Zi cannot do so long are stored in the L1 cache 3 when the processor PU communicates with the L1 cache 3 . After the first "packet", which contains the 16 tuple S3 of the data line Zi, the further 16 tuples S4, S5, S6, S7, S0, S1 and S2 are transmitted "in packets" in this order via the bus 9 and in the buffer memory 10 buffered.

As soon as the port of the L1 cache memory 3 is no longer occupied, the 16 tuples remaining in the buffer memory 10 are then gradually transferred to the L1 cache memory 3 via the bus 11 , the multiplexer 12 and the bus 13 . After transmission of the last "packet", which contains the data of the 16 tuple S2, the entire data line Zi is present in the L1 cache memory 3 . In contrast to the prior art, however, the address i of this data line is not registered in the address directory 6 until now, that is to say after the data line Zi has been completely stored in the L1 cache memory 3 . According to the invention, this registration is already carried out when the data line in question has not yet been completely stored in the L1 cache memory 3 . In the exemplary embodiment in FIG. 3, the address i is already registered when the first of the "packets" - in the example considered here, the 16-tuple S3 - is stored in the L1 cache memory 3 , while the remaining 16-tuples S4, S5, S6, S7, S0, S1 and S2 are still transmitted from the L2 cache 8 via the bus 9 or are buffered in the buffer memory 10 .

The processor system also has logic 14 which is connected to the address directory 6 via a signal line 15 and to the buffer memory 10 via a signal line 16 . The logic 14 has the following function: by storing the address i in the address directory 6 even before the data line Zi has been completely stored in the L1 cache memory 3 , it may happen that the processor PU wants to access data in the L1 cache memory 3 which there are not yet available, although the address i of the data line Zi to which this data belongs is already registered in the address directory 6 . If the logic 14 did not intervene in this situation, the processor PU would not receive a current copy from the L1 cache memory 3 if this data was appropriately accessed, but rather data that happens to be in the corresponding byte positions in the memory array of the L1 Cache 3 are present. This is because, viewed from the processor PU, the data line Zi is then completely stored in the L1 cache memory 3 when its address i is registered in the address directory 6 . The logic 14 monitors the access operations of the processor PU on the L1 cache memory 3 via signal lines (not shown in FIG. 3) that connect the logic 14 to the processor PU.

Via the signal lines 15 and 16 , the logic 14 receives the information as to whether an address i in the address directory 6 belongs to a data line Zi which is not yet completely stored in the L1 cache memory 3 . This is the case when 16 tuples of the data line Zi are still buffered in the buffer memory 10 .

When the processor PU requests access to data contained in a 16-tuple that is still buffered in the buffer memory 10 , the logic 14 via the signal line 16 causes the buffer memory 10 to output this 16-tuple via the bus 11 Multiplexer 12 and the bus 13 in the L1 cache 3 . Since the L1 cache memory 3 is a write-through cache memory, the data can in turn, as explained above, be transmitted to the processor PU essentially simultaneously. For the processor PU, the system behavior therefore appears as if the relevant 16 tuple, which was originally still buffered in the buffer memory 10 , was actually already there at the beginning of the access request to the L1 cache memory 3 .

The processor PU is connected via a store bus 17 to alignment means 18 , a so-called store aligner. The alignment means 18 are connected to a second input of the multiplexer 12 via a bus 19 , which is also 16 bytes wide. The multiplexer 12 also has a control input 20 which is 16 control lines wide. Byte-precise control of the multiplexer 12 is possible via the control input 20 .

Fig. 4 schematically illustrates the functionality of the multiplexer 12.. The first input of multiplexer 12 is connected to bus 11 , while the second input is connected to bus 19 (cf. FIG. 3). The output of the multiplexer 12 is connected to the bus 13 . Only the byte positions B1, B2, B3 and B4 of the respective buses are shown in FIG. 4. Each of the byte positions consists of 9 signal lines (8 bits and a parity bit), which are also not shown in FIG. 4. A switch in the multiplexer 12 belongs to each byte position: the byte position B1, the switch M1, B2 belongs to M2, B3 belongs to M3 and B4 belongs to M4. The further switches M5 to M16 that go to the byte positions B5 to B16 are also not shown in FIG. 4. The control input 20 can be used to determine for each of the switches M1 to M16 whether a bit position of the bus 11 or the bus 19 is to be connected to the bus 13 . Data is transmitted from the processor PU via the store bus 17 , which is 16 bytes wide, and is to be stored in the L1 cache memory 3 . For this purpose, the data to be stored are aligned in the alignment means 18 , the so-called store aligner, with the corresponding byte positions for transmission via the bus 19 . So-called store aligners are known per se from the prior art.

Before the processor PU can output data for storage on the store bus 17 , it must first be ascertained whether the corresponding data line Zi, to which the output data belong, is present in the L1 cache memory 3 . Only then can the corresponding byte positions in the memory line Zi be overwritten by the data output by the processor PU.

For this purpose, the processor PU checks whether the address i of the data line Zi is registered in the address directory 6 . If this is the case, the processor PU outputs the corresponding data via the store bus 17 . However, the situation can arise that although the address i is already registered in the address directory, the data line Zi is not yet completely stored in the L1 cache memory 3 . In particular, it can happen that the data that are output by the processor PU to the store bus 17 for storage belong to a 16-tuple that is still temporarily stored in the buffer memory 10 . Such an access by the processor PU to the L1 cache memory 3 due to a storage request for data is also monitored by the logic 14 .

If the case occurs that data to be stored are output on the bus 17 which belong to a 16 tuple, for example the tuple S1, which is still buffered in the buffer memory 10 , the logic 14 causes the buffer memory 10 via the signal line 16 Output of a "packet" containing tuple S1. According to the prior art, it would have been necessary in any case to first completely store the data line Zi, which contains the address area of the data to be stored, in the L1 cache memory 3 before storing the data.

In contrast, according to the invention, it is possible to enter the 16 tuple, which contains the address area of the data to be stored, from the buffer memory 10 via the bus 11 into the multiplexer 12 , as well as the data to be stored via the bus 19 into the multiplexer 12 , In the multiplexer 12 , only those byte positions of the 16-tuple output from the buffer memory 10 are connected to the corresponding byte positions of the bus 13 which are to remain unchanged. On the other hand, those byte positions that transmit the data to be stored via bus 19 replace the corresponding byte positions of bus 11 . This is done via switches M1 to M16, which are switched accordingly via control input 20 .

For example, if byte positions B2 and B3 are to be overwritten in a 16 tuple, switches M2 and M3 connect byte positions B2 and B3 of bus 19 with byte positions B2 and B3 of bus 13 , while the remaining bytes - Positions of the bus 13 , that is, the byte positions B1 and B4 to B16 are connected to the byte positions B1 and B4 to B16 of the bus 11 via the switches M1 and M4 to M16. As a result, the 16 tuple output from the buffer memory 10 via the bus 11 is updated in the multiplexer 12 with the new data to be stored and at the output of the multiplexer, so that the updated 16 tuple is already on the bus 13 is available. It is therefore unnecessary to first store the 16 tuple in the L1 cache 3 in order to overwrite it with the updated data at the corresponding byte positions immediately thereafter. The updated 16 tuple is transmitted via bus 13 to L1 cache memory 3 and stored there.

When the processor PU is operating, operands that extend over more than a 16 tuple are required to process an instruction. Such a situation is already due to the addresses of the operands recognizable (see. Fig. 1 and Fig. 2). In general, the operands that are required to execute an instruction are stored immediately adjacent. It is further assumed that the processor PU requires, for example, operands that are contained in two successive 16-tuples of a data line Zi, that is to say in the 16-tuples S6 and S7. If the address i of the data line Zi, which contains the required 16 tuples S6 and S7, is not registered in the address directory i, the data line Zi is stored by the L2 cache 8 in the order of the tuples S6, S7, S0, S1, S2 , S3, S4 and S5 are output via bus 9 . As described above, the first 16-tuple, which is output as a "packet" via the bus 9 , is directly forwarded to the processor PU, while the subsequent 16-tuples S7 and S0 to S5 are first buffered in the buffer memory 10 .

However, the processor PU can already see that the data contained in the 16-tuple S6 are not sufficient for the execution of the instructions, but further data are required which are present in the subsequent 16-tuple S7. After the 16 tuple S6 has been entered into the processor PU, it will therefore again access the L1 cache memory 3 in order to also obtain the 16 tuple S7. However, the 16-tuple S7 is still temporarily stored in the buffer memory 10 , although the address i of the data line Zi is already registered in the address directory 6 . Because of this, the logic 14 in turn causes the buffer memory 10 to output the 16-tuple S7, so that due to the write-through function of the L1 cache memory 3, the situation for the processor PU is as if the 16-tuple S7 were already in the L1 cache memory 3 have been present at the beginning of the access request on the 16-tuple S7 in the L1 cache. 3

FIG. 5 shows a signal diagram in the event that the processor PU wants to store data in the L1 cache memory 3 via the store bus 17 . It is assumed that with this access to the L1 cache memory 3, the address i of the corresponding data line Zi is already registered in the address directory 6 , but the 16 tuple to which the data to be stored still belongs is buffered in the buffer memory 10 . The signal diagram of FIG. 5 shows the system cycles Cycle 1 Cycle 2 Cycle 3 Cycle 4 and Cycle 5 of the "pipelined" processor PU.

In stage 0 of the pipeline, the processor fetches the next instruction from its processor (instruction fetch). In the example of FIG. 5, the processor fetches a storage instruction ST in the cycle 1, by means of which data is to be output from the processor PU and stored in the L1 cache memory 3 . In cycle 2, the instruction ST is decoded (OP decode, stage 1 ). In addition, the processor in cycle 2 already fetches the next instruction NSI (= next sequential instruction) from the program memory. This corresponds to the "pipelined" architecture of the processor PU.

In cycle 3 , the processor PU accesses the address directory 6 (L1 cache dir access). This geschiet in stage 2 (Stage 2) of the pipeline. Since the address i of the data line Zi is already registered in the address directory 6 , the situation for the processor PU is such that the requested data which is present in one of the 16 tuples of this data line Zi, for example in the tuple S5 are already stored in the L1 cache 3 . Logic 14 , however, notes that this is not the case, but that 16-tuple S5 is still temporarily stored in buffer memory 10 . This is done in cycle 3 (Compare LFB Addr with L1 CACHE Address Register). The 16 tuple S5 is then output from the buffer memory 10 and updated in the multiplexer 12 with the data to be stored. This happens in cycle 4 (ST with LF). It proves to be particularly advantageous that the pipeline has not been disturbed, since the instruction NSI in cycle 4 has already reached pipeline stage 2 .

FIG. 6 shows a signal diagram corresponding to FIG. 5 in the event that the processor PU requests operands to carry out an instruction which are stored in adjacent 16 tuples. The corresponding instruction for fetching the data is a so-called fetch instruction F. In cycle 3, the processor PU discovers that the second operand is contained in the next 16 tuple like the first operand (16 bytes crossing condition).

As a result, the next instruction NSI in the subsequent cycle 4 remains on pipeline stage 1 , since in cycle 4 a further fetch instruction F must first be carried out in order to fetch the next 16 tuple. Already in cycle 3 , the first operand is entered into the processor PU (L1 cache access, read). In addition, the logic 14 already determines in cycle 3 that the tuple in which the second operand is contained is still temporarily stored in the buffer memory 10 (Compare LFB Addr with L1 CACHE Address Register + 16). The corresponding tuple, which contains the second operand, is then output from the buffer memory 10 and, due to the write-through function of the L1 cache memory 3, is entered into the processor PU immediately thereafter. Again, it proves advantageous that the pipeline did not have to be interrupted.

The first and second operands can also be parts of one Operands are understood, whereby this operand then over extends two of the n-tuples of the same row of data.

Claims (8)

1. cache arrangement for a processor with a cache memory ( 3 ) for the processor, with an address directory ( 6 ) belonging to the cache memory and with a buffer memory ( 10 ) for intermediate storage of data lines,
wherein the registration of the address in the address directory (6) of the cache memory is performed (3) prior to the complete storage of the relevant data line in the cache memory (3);
marked by
a buffer cache control logic ( 14 ) for controlling the buffer memory ( 10 ), the output of data of the data line from the buffer memory ( 10 ) and the storage of this data in the cache memory ( 3 ) regardless of any further cache miss and parallel to the activity the processor causes; and
after this data has been output from the buffer memory ( 10 ) to the cache memory ( 3 ), this data from the cache memory ( 3 ) is made available to the requesting processor essentially simultaneously. 2. Cache arrangement for a processor according to claim 1, characterized in that each of the data lines is logically divided into n-tuples and the buffer memory ( 10 ) is organized in units of n-tuples. 3. Cache arrangement for a processor according to one of claims 1 to 2, characterized in that the processor system has a multiplexer ( 12 ) which is connected between the buffer memory ( 10 ) and the cache memory ( 3 ), a first input ( 11 ) of the multiplexer ( 12 ) with the buffer memory ( 10 ) and a second input of the multiplexer ( 12 ) with a memory bus ( 19 ), via which the processor transmits the data to be stored in the cache memory ( 3 ), and one Control input ( 20 ) of the multiplexer is connected to the buffer cache control logic. 4. cache arrangement for a processor according to one of claims 1 to 3, characterized in that data from the buffer memory ( 10 ) to the cache memory ( 3 ) and from the processor to the cache memory ( 3 ) are transmitted in units of an n-tuple. 5. cache arrangement for a processor according to one of claims 1 to 4, characterized in that it is in the cache memory ( 3 ) is a write-through cache. 6. The method for input / output of data in the cache device according to claim 1, wherein
the address of a data line which contains a data element requested by the processor is registered in the address directory ( 6 ) of the cache memory ( 3 ) before the relevant data line has been completely stored in the cache memory ( 3 ),
characterized in that
the output of a data element of a data line whose address is effected in the address directory ( 6 ) of the cache memory ( 3 ) in response to a corresponding cache read request by the processor in that
in a first step it is analyzed whether the data element of the cache read request is still in the buffer memory ( 10 ), and further, if this is the case, is brought about by
in a second step, at least one part of the data line comprising the data element is transferred ( 3 ) from the buffer memory ( 10 ) to the cache memory and at the same time the data element of the cache read request is transferred to the processor, and
in the case of a cache storage request by the processor with which a data element of a data line whose address is registered in the address directory ( 6 ) of the cache memory ( 3 ) is to be stored in the cache memory ( 3 ), a multiplexer ( 12 ) controls this, that a part of the data line addressed by the processor's cache request, which is still stored in the buffer memory ( 10 ), is transferred to the cache memory ( 3 ) and at the same time is replaced to the extent mentioned by the data elements transferred by the processor. 7. The method according to claim 6, characterized in that the data line divided into logical n-tuples and stored in the buffer memory ( 10 ) is transmitted parallel to the processor activity in the cache memory ( 3 ). 8. The method according to any one of claims 6 to 7, characterized in that if it is determined in the first step that the address of the data line of the requested data element is not yet registered in the address directory ( 6 ), that tuple that the data element requested by the processor contains, is transmitted as the first n-tuple and is stored directly in the cache memory ( 3 ) without buffering in the buffer memory ( 10 ) and the requested data element is made available directly to the processor.