DE112011103040T5 - Method for forming wafer vias in semiconductor structures using sacrificial material and semiconductor structures produced by these methods - Google Patents

Abstract

Methods of fabricating semiconductor structures include depositing a sacrificial material in a via recess, forming a first portion of a wafer via in the semiconductor structure, and replacing the sacrificial material with a conductive material to form a second portion of the wafer via. Semiconductor structures are formed by these methods , For example, a semiconductor structure may include a sacrificial material in a via recess and a first portion of a wafer via aligned with the via recess. Semiconductor structures include wafer vias that include two or more portions with a boundary between them.

Description

Technical area

The present invention generally relates to the fabrication of semiconductor structures containing through wafer interconnects, as well as to semiconductor structures fabricated by these methods.

background

Semiconductor structures are formed and include those used during the fabrication of devices using semiconductor materials (ie, semiconductor devices), such as electronic signal processing devices, memory devices, photoelectric devices (eg, light emitting diodes (LED), laser diodes, solar cells, etc.), electromechanical micro and nanodevices, etc. In such semiconductor structures, it is often necessary or advantageous to electrically and / or structurally connect one semiconductor structure to another device or structure (eg, another semiconductor structure). The processes in which semiconductor structures are connected to another device or structure are often referred to as three-dimensional integration processes.

The three-dimensional integration of two or more semiconductor structures can provide a number of advantages for microelectronic applications. For example, three-dimensional integration of microelectronic components may result in improvements in electrical performance as well as power consumption while reducing the footprint of the device (see, for example, US Pat P. Garrou et al. "The Handbook of 3D Integration", Wiley-VCH (2008) ).

The three-dimensional integration of semiconductor structures may be accomplished by attaching a semiconductor chip to one or more other semiconductor die (s) (ie, D2D (die-to-die)), a semiconductor die to one or more semiconductor wafers (ie, D2W (the die-to-die). wafer) as well as a semiconductor wafer on one or more additional semiconductor wafers (ie W2W (wafer-to-wafer)) or a combination thereof. Often, the individual semiconductor chips or wafers are relatively thin and are difficult to handle with devices for processing the chips or wafers. The so-called "carrier" chips or wafers may be attached to the actual chips or wafers that contain the active and passive components of functional semiconductor devices. The carrier chips or wafers typically do not contain any active or passive components of a semiconductor device to be fabricated. These carrier chips and wafers are referred to herein as "carrier substrates." Through the carrier substrates, the total thickness of the chips or wafers increases, and the handling of the chips or wafers by means of the processing devices that serve to process the active and / or passive components on the attached chips or wafers, the active and the passive components of a semiconductor device to be fabricated thereon is facilitated.

It is known that structures referred to herein as "through wafer interconnects" or "TWI" are employed for establishing electrical connections between active components in a semiconductor structure and conductive structures of another device or structure to which the semiconductor structure is attached becomes. Wafer vias are conductive vias that extend through at least a portion of a semiconductor structure.

Short Summary

In some embodiments, the present invention includes methods of fabricating a semiconductor structure. A sacrificial material may be present in at least one via hole that extends partially through a semiconductor structure. A first portion of at least one wafer via may be formed in the semiconductor structure. The first portion of the at least one wafer via may be aligned with the at least one via recess. The sacrificial material in the at least one via hole recess may be replaced with conductive material to form a second portion of the at least one wafer via in electrical contact with the first portion of the at least one wafer via.

The present invention further includes additional embodiments of methods for fabricating semiconductor structures. In this method, a sacrificial material is present in at least one contact hole recess extending into a surface of a semiconductor structure. A layer of semiconductor material may be present over the surface of the semiconductor structure, and at least one device structure may be fabricated using the layer of semiconductor material. A first portion of at least one wafer via extending through the layer of semiconductor material is formed. The semiconductor structure may be thinned by a side of the semiconductor material layer opposite thereto. The sacrificial material may be removed in the at least one via hole in the semiconductor structure, and the first portion of the at least one Wafer via may be exposed in the via recess, wherein conductive material may be present in the via recess to form a second portion of the at least one wafer via.

In further embodiments, the present invention includes semiconductor structures fabricated by methods disclosed herein. For example, in some embodiments, a semiconductor structure includes a sacrificial material in at least one via recess extending from a surface of the semiconductor structure partially through the semiconductor structure, a semiconductor material disposed over the surface of the semiconductor structure, and at least one semiconductor structure having at least one Section of the semiconductor material disposed over the surface of the semiconductor structure. A first portion of at least one wafer via extends through the semiconductor material disposed over the surface of the semiconductor structure, and the first portion of the at least one wafer via is in alignment with the at least one recess.

In further embodiments, the present invention includes semiconductor structures including an active area, a back surface, at least one transistor located in the semiconductor structure between the active area and the back surface, and at least one wafer via extending from the active surface and / or the rear surface extends at least partially through the semiconductor structure. The at least one wafer via includes a first portion, a second portion, and a detectable boundary between a microstructure of the first portion and a microstructure of the second portion.

Brief description of the different views in the drawings

Although the specification concludes with claims that specifically set forth and distinctly claim what is considered to be embodiments of the invention, the advantages of embodiments of the invention may be more readily understood from the description of certain examples of embodiments of the invention when read in conjunction with the accompanying drawings , in which:

1 is a simplified sectional side view of a portion of a semiconductor structure;

2 is a simplified side sectional view of a portion of another semiconductor structure that may be formed by partially including via holes through the semiconductor structure 1 be formed through;

3 is a simplified side sectional view of a portion of another semiconductor structure that may be formed by depositing a dielectric material on or over exposed areas of the semiconductor structure 2 is applied in the contact hole recesses therein;

4 is a simplified side sectional view of a portion of another semiconductor structure that may be formed by forming a material, such as polysilicon, in the via holes of the semiconductor structure 3 is applied;

5 is a simplified sectional side view of a portion of a bonded semiconductor structure that may be formed by attaching another semiconductor structure to the semiconductor structure in FIG 4 is bonded;

6 is a simplified side sectional view of a portion of another semiconductor structure that may be formed by forming the other semiconductor structure in the bonded semiconductor structure 5 is diluted;

7 FIG. 4 is an enlarged view of a portion of another semiconductor structure that may be formed by incorporating transistors and shallow trench isolation structures in and / or on the bonded semiconductor structure 6 getting produced;

8th FIG. 4 is an enlarged view of a portion of another semiconductor structure that may be formed by forming a layer of dielectric material over the semiconductor structure in FIG 7 is applied, and by portions of wafer via through the semiconductor structure in 7 be created;

9 FIG. 4 is an enlarged view of a portion of another semiconductor structure that may be formed by depositing one or more layers containing electrically conductive structures over a surface of the semiconductor structure in FIG 8th is / are produced;

10 is an enlarged view of a portion of another semiconductor structure that can be formed by the semiconductor structure in 9 bonded to a carrier substrate;

11 is an enlarged view of a portion of another semiconductor structure that may be formed by polysilicon material from contact hole recesses of the semiconductor structure in 10 Will get removed;

12 is an enlarged view of a portion of another semiconductor structure that may be formed by conductive material in the contact hole recesses of. Semiconductor structure in 11 is applied to form additional portions of wafer vias therein;

13 FIG. 4 is an enlarged view of a portion of another semiconductor structure that may be formed by placing the carrier substrate from the semiconductor structure in FIG 12 is removed and conductive bumps are applied over exposed ends of the wafer vias therein;

14 to 16 represent other methods that can be used to form a semiconductor structure like the one shown in FIG 10 illustrated to a semiconductor structure as in 11 to be processed; and

17 to 20 represent other methods that can be used to form a semiconductor structure like the one shown in FIG 10 illustrated to a semiconductor structure as in 11 to be processed.

Detailed description

The present description includes specific details, such as material types and machining conditions, to enable a thorough description of embodiments of the present disclosure, as well as forms of implementation thereof. However, one skilled in the art will appreciate that the embodiments of the present disclosure can be practiced without the use of these specific details and in connection with conventional manufacturing techniques. Furthermore, the present description does not form a complete process flow for manufacturing a semiconductor device or a semiconductor system. Only those process operations and structures required to understand the embodiments of the present invention are described in detail herein. The materials described herein can be formed (ie, deposited or grown) by any suitable method, spin coating, blanket coating, Bridgeman and Czochralski processes, CVD (chemical vapor deposition), PECVD ( plasma enhanced chemical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition) or PVD (physical vapor deposition) includes, but is not limited to. Although the materials described and illustrated herein may be formed as layers, the materials are not limited to layers and may be formed in other three-dimensional shapes.

As used herein, the terms "horizontal" and "vertical" define relative positions of elements or structures with respect to a major plane of a semiconductor structure (ie, wafer, chip, substrate, etc.) regardless of the orientation of the semiconductor structure and are rectangular dimensions which are understood in terms of the orientation of the structure described. As used herein, the term "vertical" refers to and includes a dimension substantially perpendicular to the major surface of a semiconductor structure, and the term "horizontal" refers to a dimension substantially parallel to the major surface of the semiconductor structure.

The term "semiconductor structure" as used herein means and includes a structure used in the formation of a semiconductor device. Semiconductor structures include, for example, chips and wafers (eg, carrier substrates and device substrates) as well as assemblies or composite structures that include two or more chips and / or wafers that are integrated three-dimensionally.

Semiconductor structures further include finished semiconductor structures as well as intermediate structures formed in the fabrication of semiconductor devices. Semiconductor structures may include conductive, semiconducting and / or non-conductive materials.

The "processed semiconductor structure" as used herein includes and includes any semiconductor structure that includes one or more at least partially formed semiconductor structures. Machined semiconductor structures are a subset of semiconductor structures, and all processed semiconductor structures are semiconductor structures.

As used herein, the term "bonded semiconductor structure" means any structure that includes two or more semiconductor structures attached to each other and includes them. Bonded semiconductor structures are a subset of semiconductor structures, and all bonded semiconductor structures are semiconductor structures. Furthermore, bonded semiconductor structures containing one or more processed semiconductor structures are also processed semiconductor structures.

As used herein, the term "device structure" refers to any portion of a processed semiconductor structure that includes a portion of an active or a passive component and device structures including, and including, semiconductor devices formed in the semiconductor structure include, for example, active and passive components of integrated circuits, such as transistors, transducers, capacitors, resistors, traces, vias, and conductive pads.

The term "wafer via" or "TWI" as used herein means any conductive via extending through at least a portion of a first semiconductor structure and serving to provide structural and / or electrical connection to the first semiconductor structure and a second semiconductor structure via an interface between the first semiconductor structure and the second semiconductor structure, and includes this. Wafer vias are also referred to in the art by other terms, such as "through silicon vias" or "through substrate vias" (TSV), and "wafer via" or "TWV". TWI typically pass through a semiconductor structure in a direction perpendicular to the generally planar major surface of the semiconductor structure (i.e., in a direction parallel to the Z axis).

As used herein, the term "active area", when used in conjunction with a processed semiconductor structure, refers to one or more device structures in and / or at the exposed major surface of the processed semiconductor structure that has been processed or processed Form the main surface of the processed semiconductor structure, and includes these.

The term "back surface" as used herein in connection with a processed semiconductor structure stands for and includes an exposed major surface of the processed semiconductor structure on an opposite side of the processed semiconductor structure from an active surface of the semiconductor structure.

The term "III-V semiconductor material" as used herein means any material consisting of one or more Group IIIA elements of the Periodic Table (B, Al, Ga, In, and Ti) and one or more Group VA elements Periodic table (N, P, As, Sb and Bi) and includes this.

As used herein, the term "thermal expansion coefficient", when used in relation to a material or structure, stands for the average linear thermal expansion coefficient of the material or structure at room temperature.

In some embodiments, as further explained below, the present invention includes methods of fabricating semiconductor structures that include one or more wafer via (s). The wafer vias may contain two or more portions that are formed in separate processes.

1 is a simplified sectional side view of a portion of a first semiconductor structure 100 , The first semiconductor structure 100 may be a layer or a substrate of material 102 include. The material 102 For example, a ceramic material, such as. For example, an oxide (eg, silicon dioxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )) or a nitride (eg, silicon nitride (Si ₃ N ₄ ) or boron nitride (BN)). In another example, the first semiconductor material 100 a semiconductor material such as silicon (Si), germanium (Ge), III-V semiconductor material, etc. Furthermore, the material 102 a single crystal of semiconductor material or an epitaxial layer of semiconductor material. In a non-limiting example, the material 102 the first semiconductor structure 100 comprise a single crystal of solid silicon material.

2 represents another semiconductor structure 110 which can be formed by in the semiconductor structure 100 in 1 Via recesses 112 be created. The contact hole recesses 112 may serve to form portions of wafer vias, as discussed in more detail below. The contact hole recesses 112 can, as in 2 shown from a first major surface 104 the semiconductor structure 110 out into the material 102 extend into it and at least partially therethrough. In some embodiments, the contact hole recesses 112 noncontinuous via holes which extend only partially through the material 102 the semiconductor structure 110 extend through.

The contact hole recesses 112 may have a generally cylindrical cross-sectional shape or any other cross-sectional shape. The contact hole recesses 112 may have an average cross-sectional dimension (eg, average diameter) of about 1 μm or less, or about 10 μm or less, or even 50 μm or less. Furthermore, the contact hole recesses 112 an average aspect ratio (ie, the ratio of the average height to the average cross-sectional dimension) in a range ranging from about 0.5 to about 10.0.

3 represents another semiconductor structure 120 which can be formed by a dielectric material 122 on the surfaces of the material 102 in the contact hole recesses 112 is applied. The dielectric material 122 As a non-limiting example, a ceramic material such as an oxide (eg, silicon dioxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )) or a nitride (eg, silicon nitride (Si ₃ N ₄ ) or boron nitride ( BN)) or an oxynitride (eg, silicon oxynitride). The dielectric material 122 may be in situ on or in the exposed areas of the material 102 in the contact hole recesses 112 be formed. In further embodiments, the dielectric material 122 over the exposed surfaces of the material 102 in the contact hole recesses 112 be deposited. In a specific, non-limiting example, the material 102 solid silicon material, the dielectric material 122 may include silicon oxide, and the dielectric material 122 can be formed by exposing the exposed surfaces of the material 102 in the contact hole recesses 112 be oxidized. In some embodiments, the dielectric material 122 also over the first main area 104 the semiconductor structure 110 ( 2 ) are deposited, as in 3 is shown.

The contact hole recesses 112 ( 3 ), as with reference to 4 can be seen with a sacrificial material 132 be filled. The sacrificial material 132 may include a material that is eventually removed and replaced with another material, as discussed below. The sacrificial material 132 For example, it may comprise polycrystalline silicon material. That is, the sacrificial material 132 may include silicon having a microstructure containing a plurality of inter-bonding crystal grains of silicon randomly aligned in the microstructure. Such a silicon material is commonly referred to in the art as "polysilicon" material. In other embodiments, the sacrificial material 132 comprise any other material relative to the material 102 (and the optional dielectric material 122 ) can be selectively etched, such as a ceramic material, a semiconductor material (eg, polycrystalline SiGe), a polymer material, a metal, etc. In some embodiments, the sacrificial material 132 an additional dielectric material or multiple additional materials, such as an oxide, nitride, or oxynitride (eg, silicon dioxide). The sacrificial material 132 may have a composition selected to be the atoms of the sacrificial material 132 when processing the semiconductor structure at temperatures above about 400 ° C, to which the semiconductor structure may be exposed in the fabrication of transistors or other device structures, as described in more detail below, do not significantly diffuse into surrounding regions of a semiconductor structure or adversely affect the semiconductor structure influenced by the fact that the atoms should diffuse in appreciable amount into the surrounding structures during such processes at higher temperatures. In some embodiments, the sacrificial material 132 have a coefficient of thermal expansion which is about 40% of a coefficient of thermal expansion of the material 102 is about 20% of a coefficient of thermal expansion, the material 102 or is about 5% of a coefficient of thermal expansion, the material 102 having. Furthermore, the sacrificial material 132 in some embodiments comprise a material having a coefficient of thermal expansion of about 5.0 × 10 ^-6 ° C. ^-1 or less, about 3.0 × 10 ^-6 ° C. ^-1 or less, or even 1.0 × 10 -4 ^{. 6} ° C ^-1 or less.

After the sacrificial material 132 in the recesses 112 has been applied ( 3 ), the surface can be 134 the semiconductor structure 130 be planarized to cause at least the exposed surfaces of the sacrificial material 132 and the exposed surface of the material 102 on the surface 134 the semiconductor structure 130 are coplanar and have the same extent. That is, the sacrificial material 132 For example, it may be adjusted over the first major surface using CVD techniques 104 (and the optional dielectric material 122 ) be formed. The sacrificial material 132 can be formed in a thickness through which the contact hole recesses 112 at least substantially completely with the sacrificial material 132 are filled. Any excess sacrificial material 132 (and optional dielectric material 132 ) can then be removed to the surface 134 the semiconductor structure 130 to planarize. For example, the surface 134 the semiconductor structure 130 using a chemical process (for example, a chemical wet or dry etching process), a mechanical process (for example, a grinding or Lapp process), or planarization with a CMP process (chemical mechanical polishing process).

After the sacrificial material 132 , as described above, in the recesses 112 may be applied, a thin layer of semiconductor material over the surface 134 the semiconductor structure 130 be applied. In a non-limiting example, a thin layer of semiconductor material may overlie the area 134 the semiconductor structure 130 be applied as below with reference to 5 and 6 is described.

6 FIG. 12 illustrates a bonded semiconductor structure that may be formed by forming a further semiconductor structure that is a substrate 142 includes, to the surface 134 the semiconductor structure 130 in 4 is bonded. The substrate 142 may comprise a semiconductor material such as silicon (Si), germanium (Ge), III-V semiconductor material, etc. Furthermore, the material of the substrate 152 a single crystal of semiconductor material or an epitaxial layer of semiconductor material. In a non-limiting example, the material of the substrate 142 comprise a single crystal of solid silicon material.

The substrate 142 can surface with a direct bond process 134 be bonded, at which the substrate 142 directly to the semiconductor structure 130 ( 4 ) is bonded directly by atomic or molecular bonds between a bonding surface of the semiconductor structure 130 and a bonding surface of the substrate 142 be formed along a bonding interface between them. That is, the substrate 142 can be achieved without the use of an adhesive or other intermediate bonding material between the substrate 142 and the semiconductor structure 130 directly to the semiconductor structure 130 be bonded. The properties of atomic or molecular bonds between the substrate 142 and the semiconductor structure 130 depend on the material composition of the substrate 142 and the semiconductor structure 130 from. Thus, in some embodiments, direct atomic or molecular bonds can be made, for example, between silicon oxide or germanium oxide and silicon, germanium, silica or / and germanium oxide.

The bonding surface of the substrate 142 For example, in one non-limiting example, it may include an oxide material (eg, (eg, silicon dioxide (SiO ₂ )), and the bond area of the semiconductor structure 130 may at least substantially consist of the same oxide material (for example, silicon dioxide (SiO ₂ )). In these embodiments, a process of directly bonding a silicon oxide to a silicon oxide surface may be employed to form the bonding surface of the substrate 142 to a bonding surface of the semiconductor structure 130 to bond. In these embodiments, as shown in FIG 5 shown a bonding material 148 (For example, a layer of oxide, such as silicon dioxide (SiO ₂ )) between the substrate 142 and the semiconductor structure 130 ( 4 ) may be disposed at a bonding interface between them. The bonding material 148 may have an average thickness of, for example, about 1000 angstroms.

In further embodiments, the bonding surface of the substrate 142 a semiconductor material (eg, silicon), and the bonding surface of the semiconductor structure 130 may at least substantially consist of the same semiconductor material (eg silicon). In these embodiments, a process for directly bonding a silicon surface to a silicon-to-silicon surface-direct-bonding ("") process may be used to form the bonding surface of the substrate 142 on a bonding surface of the semiconductor structure 130 to bond.

In some embodiments, direct bonding may occur between the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 be prepared by the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 are each formed so that they have relatively smooth surfaces, and then the bonding surfaces are joined and maintained during a heat treatment process, contact between the bonding surfaces.

For example, the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 are each made to have a root mean square surface roughness (R _RMS ) of about 2.0 nm or less, about 1.0 nm or less, or about 0.25 nm or less. In some embodiments, the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 each should be designed to have a root mean square surface roughness (R _RMS ) of between about 0.25 nm and about 2.0 nm, or between about 0.5 nm and about 1.0 nm.

The heat treatment process may include that of the substrate 142 and the semiconductor structure 130 for a period between about two minutes (2 minutes) and about fifteen hours (15 hours) in an oven to a temperature between about 100 ° C and about 400 ° C.

The bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 may, as mentioned above, each be formed to be relatively smooth using a mechanical polishing process and / or a chemical etching process. For example, a CMP (chemical mechanical polishing process) can be applied to the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 each planarize and / or reduce their surface roughness.

A first section 144 of the substrate 142 can from the semiconductor structure 140 in 5 be removed, leaving a second section 146 of the substrate 142 above the surface 134 remains and the bonded semiconductor structure 150 in 6 arises. That is, the first section 144 of the substrate 142 can from the second section 146 of the substrate 142 be separated. The semiconductor structure 150 in 6 contains a thin layer of Semiconductor material 152 above the surface 134 , The thin layer of semiconductor material 152 is through the second section 144 ( 5 ) educated.

It may, by way of non-limitative example, with reference to again 5 to see the process known in the industry under the name SMART-CUT ^® , the first section 144 of the substrate 142 from the second section 146 of the substrate 142 to separate. Such processes are for example in U.S. Patent No. RE 39,484 by Bruel (issued on 6 February 2007), U.S. Patent No. 6,303,468 by Aspar et al. (granted on October 16, 2001), U.S. Patent No. 6,335,258 by Aspar et al. (granted on January 1, 2002), U.S. Patent No. 6,756,286 by Moriceau et al. (granted on June 29, 2004), U.S. Patent No. 6,809,044 by Aspar et al. (granted on October 26, 2004) as well U.S. Patent No. 6,946,365 by Aspar et al. (September 20, 2005), the disclosure of all of these patents being incorporated herein in their entirety by this reference.

A variety of ions (eg, hydrogen, helium, or inert gas ions) may be introduced into the substrate 142 be implanted. The ions may be before or after attaching the substrate 142 on the semiconductor 130 in 4 as described above into the substrate 142 be implanted. For example, ions from an ion source (not shown) attached to one side of the substrate 142 is positioned in the substrate 142 be implanted. Ions may be in a direction substantially perpendicular to the major surfaces of the substrate 142 in the substrate 142 be implanted. The depth at which the ions are implanted into the substrate, as known in the art, is at least partially dependent on the energy with which the ions are implanted into the substrate. In general, ions implanted at lower energy are implanted at a relatively shallow depth, while ions implanted at higher energies are implanted relatively more deeply.

Ions can enter the substrate 142 be implanted with a given energy, which is selected so that the ions at an advantageous depth in the substrate 142 be implanted. The ions may in a particular non-limiting example in the substrate 142 be arranged at a selected depth so that the average thickness T of the second section 146 of the substrate 142 is about 300 nm or less, or about 100 nm or less. Inevitably, as known in the art, at least some ions may be implanted at depths other than the desired implantation depth, and a plot of the concentration of ions as a function of depth into the substrate 142 in from a surface of the substrate 142 generally, a bell-shaped (symmetrical or asymmetric) curve can be formed which has a maximum in an advantageous implantation depth.

After implantation in the substrate 142 the ions can form a fracture plane (fracture plane) 143 (in 5 shown as a broken line) in the substrate 142 form. The fracture surface 143 may be a layer or a region in the substrate 142 which is at the level of maximum ion concentration in the substrate 142 aligned (centered around them, for example). The fracture surface 143 can be a weak zone within the substrate 142 form along which the substrate 142 can be split or broken in a subsequent process. The substrate 142 can along the fracture surface 143 split or broken by the substrate 142 is heated, a mechanical force on the substrate 142 is exercised or otherwise energy to the substrate 142 acts.

In further embodiments, the second section 146 of the substrate 142 above the surface 134 the semiconductor structure 130 in 4 by providing a relatively thick layer of material (eg, a layer having an average thickness greater than about 300 microns), such as the substrate 142 , is bonded and then the relatively thick substrate 142 of the page 149 The surface is diluted 134 opposite. For example, the substrate 142 using a chemical process (eg, a dry or wet chemical etch process), a mechanical process (eg, a grinding or Lapp process), or by means of a CMP process.

In further embodiments, a relatively thin layer of semiconductor material (the second portion 146 of the substrate 142 substantially similar in composition and construction) in situ over (for example on) the surface 134 the semiconductor structure 130 in 4 be formed. For example, a relatively thin layer of silicon material may be formed by exposing material, such as silicon, over the surface 134 the semiconductor structure 130 in 4 is applied to an advantageous thickness.

After creating a thin layer of semiconductor material 152 above the surface 134 the semiconductor structure 130 in 3 may include one or more device structures on and / or in the thin layer of semiconductor material 152 be formed. That is, one or more device structures may under Use of the thin layer of semiconductor material 152 be formed. In a non-limiting example, a plurality of transistors may be formed using the thin layer of semiconductor material 152 getting produced.

7 represents a portion of the bonded semiconductor device 150 out 6 that with the broken line 158 is marked, after processing the semiconductor structure 150 for forming the bonded and processed semiconductor structure 160 in 7 dar. The semiconductor structure 160 contains one or more transistors 162 , In 7 the clarity is only one transistor 162 shown. Every transistor 162 can, as in 7 shown a source that has a source area 163A and a source contact 163B contains a drain that has a drain area 164A and a drain contact 164B contains, as well as a gate structure 165 contain. The source area 163A and the drain area 164A can be areas of the thin layer of semiconductor material 152 which has been doped with one or more dopants to make these regions electrically conductive. The source area 163A and the drain area 164A can through a channel area 166 separated from each other, which is an undoped portion of the thin layer of semiconductor material 152 may include. The gate structure 165 can over the channel area 166 in the transverse direction between the source and the drain of the transistor 162 be arranged. The source contact 163B , the drain contact 164B and the gate structure 165 may each contain a conductive material, such as one or more metals, or a doped polysilicon material. The conductive material of the gate structure 165 can face, the thin layer of semiconductor material 152 by one or more dielectric materials (eg, an oxide, a nitride, an oxynitride, etc.).

One or more shallow trench isolation structures 168 can / can, as in 7 shown in the thin layer of semiconductor material 152 close to the transistors 162 and be formed through them. The shallow trench isolation structures 168 may comprise a dielectric material and serve to each transistor 162 over other transistors or other device structures of the semiconductor structure 160 electrically isolate. The shallow trench isolation structures 168 For example, in one non-limiting example, they may include a dielectric material such as an oxide, a nitride, an oxynitride, etc. The shallow trench isolation structures 168 may be vertically aligned (ie, in a direction perpendicular to the major surfaces of the semiconductor structure 160 , such as the surface 134 ), wherein the contact hole recesses 112 and the sacrificial material 132 contained therein. That is, the contact hole recesses 112 and the sacrificial material 132 may be positioned to one another such that a straight line is at least substantially perpendicular to the major surfaces of the semiconductor structure 160 , such as the surface 134 , which can be pulled through a shallow trench isolation structure 168 and a volume of sacrificial material 132 in one of the contact hole recesses 112 runs.

As with reference to 8th can be seen, a bonded, processed semiconductor structure 170 be formed by a layer of dielectric material 172 (eg, an interlayer dielectric material) over an exposed surface 169 the semiconductor structure 160 in 7 is applied, in and / or at the one or more transistor (s) 162 and the shallow trench isolation structures 168 have been formed, and first sections 174 wafer vias are formed therein.

The layer of dielectric material 172 can on the surface 169 may be formed or deposited over and may have an average thickness sufficient to the gate structure 165 of the transistor 162 cover, as in 8th is shown. The layer of dielectric material 172 may comprise a dielectric material such as an oxide, a nitride, an oxynitride, etc.

First sections 174 wafer vias may, as further referenced 8th seen in the semiconductor structure 170 be educated. The first sections 174 Wafer vias may include a conductive material, such as one or more metals, doped polysilicon, etc. The first sections 174 wafer vias may be formed by contact hole recesses 176 through the layer of dielectric material 172 , through the shallow trench isolation structures 168 as well as by any bonding material 148 to the sacrificial material 132 in the contact hole recesses 112 in the material 102 be formed. In some embodiments, it is possible that the shallow trench isolation structures 168 not completely through the thin layer of semiconductor material 152 extend through, and the contact hole recesses 176 may also pass through at least a portion of the thin layer of semiconductor material 152 extend through. The contact hole recesses 176 For example, they may be formed using a masking and etching process. A mask layer may be over the exposed major surface 178 the layer of dielectric material 172 be applied. The masking layer may be patterned to form holes or openings passing through the masking layer at the positions where the via-hole recesses 176 to be trained. The openings in the mask layer may have a cross-sectional size and shape have a desired cross-sectional size and shape of the contact hole recesses 176 correspond to be trained. The semiconductor structure 170 may then be treated with one or more etchants which etch the various materials through which the via holes are formed 176 should extend through, without the mask layer (appreciably) is etched. For example, a wet chemical etching process or a dry reactive ion etching process may be used to form the via holes 176 through the layer of dielectric material 172 , the shallow trench isolation structures 168 and any bonding material 148 to the sacrificial material 132 train.

In some embodiments, the contact hole recesses 176 an average aspect ratio (ie, a ratio of the average height to the average cross-sectional dimension) in a range ranging from about 0.5 to about 10.0.

After forming the contact hole recesses 176 can be conductive material in the contact hole recesses 176 be applied. For example, one or more metal materials may be in the via holes 176 be deposited via an electroless plating process and / or a galvanic plating process.

The first sections 174 wafer vias may be like the shallow trench isolation structures 168 through which they pass, vertically on the contact hole recesses 112 and the sacrificial material contained therein 132 be aligned (ie, along a direction perpendicular to the main surfaces of the semiconductor structure 170 , such as the surface 134 , be aligned). That is, the first sections 174 of wafer vias and the sacrificial material 132 may be positioned to one another such that a straight line is at least substantially perpendicular to the major surfaces of the semiconductor structure 170 , such as the area 134 that can be pulled through a first section 174 a wafer via and a volume of sacrificial material 132 in one of the contact hole recesses 112 passes through.

After forming the first sections 174 wafer vias may be further processed to include additional device structures, such as conductive vias, leads, traces, and pads over the exposed major surface 178 the layer of dielectric material 172 train. These processes may include those known in the art as back end of line (BEOL) processes.

9 represents, for example, a bonded and processed semiconductor structure 180 by producing a variety of device structures 182 in one or more surrounding dielectric material 184 can be trained. The device structures 182 may include conductive vias, lines, traces, and / or pads comprising a conductive material, such as one or more metals, or doped polysilicon. The one or more surrounding dielectric materials 184 may include an oxide, a nitride, an oxynitride, etc. The various device structures 182 and the surrounding dielectric material 184 can lithographically (ie, layer by layer) over the major surface using processes known in the art 178 the layer of dielectric material 172 be formed.

After forming device structures 182 over the layer of dielectric material 172 as related to above 9 is explained, a section of the material 102 from the semiconductor structure 180 be removed to the sacrificial material 132 about the material 102 exposed as in the bonded and processed semiconductor structure 190 in 10 is shown. The section of the material 102 can from the exposed main surface 103 ( 9 ) of the material 102 at the active area 186 opposite side of the semiconductor structure 180 be removed. The section of the material 102 can be removed in a non-limiting example, for example, using a chemical etching process, a mechanical polishing process, or a CMP process. When there is a dielectric material 122 between the sacrificial material 132 and the material 102 is located, as in 9 may be a portion of the dielectric material 122 also be removed to the sacrificial material 132 to the outside of the semiconductor structure 190 to expose, as in 10 is shown.

Optionally, the active area 186 the semiconductor structure 180 in 9 to a carrier substrate 192 be bonded, like this in 10 is shown before the material 102 to expose the sacrificial material 132 is removed so as to handle the semiconductor structure when removing the material 102 to facilitate.

After exposing the sacrificial material 132 to the outside of the semiconductor structure 190 as it is in 10 is shown, the sacrificial material 132 in the contact hole recesses 112 be removed to the in 11 shown bonded and processed semiconductor structure 200 train. In one As a non-limiting example, a wet chemical etching process may be used to prepare the sacrificial material 132 in the contact hole recesses 112 to remove. It may be an etchant for removing the sacrificial material 132 be used, which is the sacrificial material 132 from the semiconductor structure 200 etched (eg, removed) at a rate higher than a rate at which the etchant is the dielectric material 122 and any bonding material 148 away. That is, it may be an etchant for removing the sacrificial material 132 used selectively on the sacrificial material 132 (and optionally on the optional dielectric material 122 ) and any bonding material 148 acts. In embodiments where the sacrificial material comprises polysilicon material, the etchant may comprise a mixture of nitric acid, hydrofluoric acid, and water. In embodiments where the sacrificial material 132 another dielectric material, such as silicon dioxide, may include the sacrificial material 132 can be selectively etched using an etching solution comprising hydrofluoric acid or a plasma etching process (using, for example, etching of sulfur hexafluoride (SF ₆ )).

Conductive material can, as in 12 shown in the contact hole recesses 112 (in which by the removal of the sacrificial material 132 vacated space) are applied to second sections 212 of wafer vias 214 train. The wafer vias 214 contain the first sections 174 and the second sections 212 , Direct physical and electrical contact can be made between the first sections 174 and the second sections 212 the wafer vias 214 getting produced.

The conductive material of the second sections 212 the wafer vias 214 may comprise a conductive material, such as one or more metals, doped polysilicon, etc. In some embodiments, the conductive material of the second portions 212 the wafer vias 214 at least substantially identical to the conductive material of the first sections 174 the wafer vias 214 be. The conductive material may be in the contact hole recesses 112 . 176 to be available. For example, one or more metal materials may be in the via holes 176 be deposited using an electroless plating process and / or a galvanic plating process.

The wafer vias 214 contain the first sections 174 and the second sections 212 , Because the first sections 174 and the second sections 212 in separate processes at different consecutive times in the fabrication of the semiconductor structure 210 may be formed in some embodiments of the invention, a single detectable limit 216 in the microstructure between the first sections 174 and the second sections 212 the wafer vias 214 to be available. The recognizable limit 216 may be close to a major surface of the thin layer of semiconductor material 152 are located. For example, the recognizable limit 216 and the bonding material 148 that attaches to a major surface of the thin layer of semiconductor material 152 is to be coplanar. Furthermore, the semiconductor structure 210 parallel to the active area 186 be aligned, as in 12 is shown.

In some embodiments, the wafer vias may 214 an average aspect ratio (ie, the ratio of the average height to the average cross-sectional dimension) in a range ranging from about 0.5 to about 10.0.

After forming the wafer vias, as described above, the carrier substrate may be 192 from the bonded and processed semiconductor structure 210 in 12 be removed to the bonded and processed semiconductor structure 220 in 13 train. Leading contact bumps 222 can, as in 13 shown structurally and electrically with the exposed ends of the second sections 212 the wafer vias 214 on the back surface 224 the semiconductor structure 220 the active area 186 be connected opposite. The conductive bumps 222 may include a conductive material, such as a conductive solder alloy.

In the 12 shown semiconductor structure 220 can be further processed and encapsulated if required or desired. The semiconductor structure 220 can then be done using the conductive bumps 222 structurally and electrically connected to another structure, such as a printed circuit board, another semiconductor structure (eg, another chip or wafer), etc. In further embodiments, the semiconductor structure 220 using other devices and methods known in the art, for example, using conductors, anisotropic conductive film, etc. structurally and electrically connected to another structure.

In some embodiments, as referenced above 10 can be seen, possibly relatively difficult, the sacrificial material 132 in the contact hole recesses 112 etch selectively, without other material of the semiconductor structure 190 to etch. In these embodiments, it may be desirable to use other materials Semiconductor structure 190 to protect before the sacrificial material 132 etched as described above.

14 for example, represents a semiconductor structure 230 which can be formed by a mask layer 232 over the surfaces of the semiconductor structure 190 in 10 is deposited such that it at least substantially all exposed surfaces of the semiconductor structure 230 covers, possibly some surfaces of the carrier substrate 192 with exception of. The mask layer 232 may be a ceramic material such as an oxide (eg, silicon dioxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )), a nitride (eg, silicon nitride (Si ₃ N ₄ ) or boron nitride (BN)) or an oxynitride.

The mask layer 232 can, as in 15 shown to be structured to openings 242 Trained through the mask layer 232 extend therethrough so that the bonded and processed semiconductor structure 240 in 15 arises. A photolithographic masking and etching process, as known in the art, may be employed to surround the apertures 242 through the mask layer 232 through train. The openings 242 can be sized, shaped and arranged so that the sacrificial material 132 in the contact hole recesses 112 over the openings 242 exposed. The semiconductor structure 240 can then be subjected to a wet or dry etching process using an etchant relative to the material of the mask layer 232 selectively on the sacrificial material 132 acts. This etching process becomes the sacrificial material 132 in the contact hole recesses 112 removed, leaving the semiconductor structure 250 in 16 arises. The mask layer 232 can then from the semiconductor structure 250 in 16 are removed, so that a semiconductor structure is formed, which is at least substantially identical to the semiconductor structure 200 in 11 is.

For additional procedures, after the material 102 has been diluted, as already related to 9 and 10 was explained, the material 102 relative to the sacrificial material 132 and / or the optional dielectric material 122 be deepened to the semiconductor structure 260 in 17 train. The material 102 in one non-limiting example relative to the sacrificial material 132 and / or the optional dielectric material 122 be deepened by about 2000 angstroms. After forming the semiconductor structure 260 in 17 can be a mask layer 272 over the semiconductor structure 260 are deposited to the semiconductor structure 270 in 18 train. The mask layer 272 For example, a ceramic material such as an oxide (eg, silicon dioxide (SiO ₂ ) or aluminum oxide (Al ₂ O ₃ )), a nitride (eg, silicon nitride (Si ₃ N ₄ ) or boron nitride (BN)), or an oxynitride. The semiconductor structure 270 can, as in 18 shown a main surface 274 on one side thereof, which are the carrier substrate 192 opposite.

The main area 274 the semiconductor structure 270 in 18 may be subjected to a planarization process, such as a CMP process, around the sections of the mask layer 272 (As well as sections of any dielectric material 122 ) about the volume of sacrificial material 132 from the contact hole recesses 112 to remove and so the bonded and processed semiconductor structure 280 in 19 train. The sacrificial material 132 can after planarizing the main surface 274 ( 18 ) through the mask layer 272 through. After exposing the sacrificial material 132 can the semiconductor structure 280 subsequently subjected to a wet or dry etching process using an etchant relative to the material of the mask layer 272 selectively on the sacrificial material 132 acts. This etching process becomes the sacrificial material 132 from the contact hole recesses 112 removed, leaving the bonded and processed semiconductor structure 290 in 20 arises. The mask layer 272 can then from the semiconductor structure 290 in 20 are removed to form a semiconductor structure that is at least substantially identical to the semiconductor structure 200 in 11 is, which then, as already described, can be further processed.

When wafer vias are formed in a multi-stage process (eg, a two-stage process), as above, in the context of the wafer vias 214 described above, since the aspect ratios of the various portions of the wafer vias are smaller than the aspect ratios of the entire wafer vias, it may be possible to improve the yield of properly functioning semiconductor structures, thereby potentially etching the via holes in which the vias different coverage of the wafer vias, better coverage of insulating dielectric materials over exposed areas in the via holes, and better plating of conductive material in the via holes for forming the various portions of the wafer vias. Furthermore, in the fabrication of transistors, such as the transistors described herein 162 , the semiconductor structure to temperatures of over 400 ° C are exposed. If, during processing of the semiconductor structure at such high temperatures, a conductive material would be in via holes, the metal atoms could possibly diffuse into other regions of the semiconductor structure, which diffusion would diffuse into contact hole recesses Function of the semiconductor structure could adversely affect. Furthermore, mismatching between the coefficient of thermal expansion of this metal material and the surrounding dielectric and semiconductor materials could lead to structural damage to the semiconductor structure. Thus, if a sacrificial material is deposited in via holes in a semiconductor structure before the transistors are fabricated and the sacrificial material is replaced with another conductive material after the transistors have been fabricated, such structural damage can be avoided or the likelihood that such structural damage occurs.

• Ausführungsform 1: Ein Verfahren zum Herstellen einer Halbleiterstruktur, das umfasst: Aufbringen eines Opfermaterials in wenigstens einer Kontaktloch-Aussparung, die sich teilweise durch eine Halbleiterstruktur hindurch erstreckt; Ausbilden eines ersten Abschnitts wenigstens einer Wafer-Durchkontaktierung in der Halbleiterstruktur und Ausrichten des ersten Abschnitts der wenigstens einen Wafer-Durchkontaktierung auf die wenigstens eine Kontaktloch-Aussparung; und Austauschen des Opfermaterials in der wenigstens einen Kontaktloch-Aussparung gegen leitendes Material und Ausbilden eines zweiten Abschnitts der wenigstens einen Wafer-Durchkontaktierung in elektrischem Kontakt mit dem ersten Abschnitt der wenigstens einen Wafer-Durchkontaktierung.
• Ausführungsform 2: Das Verfahren nach Ausführungsform 1, wobei Ausbilden eines ersten Abschnitts wenigstens einer Wafer-Durchkontaktierung in der Halbleiterstruktur des Weiteren Führen des ersten Abschnitts der wenigstens einen Wafer-Durchkontaktierung durch ein dielektrisches Material umfasst.
• Ausführungsform 3: Das Verfahren nach Anspruch 1, wobei Aufbringen des Opfermaterials in der wenigstens einen Kontaktloch-Aussparung, die sich teilweise durch die Halbleiterstruktur hindurch erstreckt, umfasst: Ausbilden wenigstens einer nicht-durchgehenden Kontaktloch-Aussparung, die sich teilweise durch die Halbleiterstruktur von einer Oberfläche derselben her hindurch erstreckt; und Aufbringen von Polysilizium-Material, eines III-V-Halbleitermaterials oder/und eines dielektrischen Materials in der wenigstens einen nicht-durchgehenden Kontaktloch-Aussparung.
• Ausführungsform 4: Das Verfahren nach Anspruch 3, wobei Aufbringen von Polysilizium-Material, eines III-V-Halbleitermaterials oder/und eines dielektrischen Materials in der wenigstens einen nicht-durchgehenden Kontaktloch-Aussparung Aufbringen von Polysilizium-Material in der wenigstens einen nicht-durchgehenden Kontaktloch-Aussparung umfasst.
• Ausführungsform 5: Das Verfahren nach Ausführungsform 3, das des Weiteren Ausbilden der wenigstens einen Kontaktloch-Aussparung durch massives Silizium-Material hindurch umfasst.
• Ausführungsform 6: Das Verfahren nach Ausführungsform 4, das des Weiteren Aufbringen eines dielektrischen Materials zwischen dem massiven Silizium-Material und dem Polysilizium-Material in der wenigstens einen nicht durchgehenden Kontaktloch-Aussparung umfasst.
• Ausführungsform 7: Das Verfahren nach Ausführungsform 3, das des Weiteren Aufbringen einer dünnen Schicht aus Halbleitermaterial über einer Oberfläche der Halbleiterstruktur nach dem Aufbringen des Polysilizium-Materials in der wenigstens einen nicht durchgehenden Kontaktloch-Aussparung umfasst.
• Ausführungsform 8: Das Verfahren nach Ausführungsform 7, wobei Aufbringen der dünnen Schicht aus Halbleitermaterial über der Oberfläche der Halbleiterstruktur umfasst: Implantieren von Ionen in ein Substrat, das Halbleitermaterial umfasst, um eine Bruchfläche in dem Substrat auszubilden; Bonden des Substrats an die Oberfläche des Halbleiter-Substrats sowie Brechen des Substrats entlang der Bruchfläche und Trennen der dünnen Schicht aus Halbleitermaterial von einem restlichen Abschnitt des Substrats, wobei die dünne Schicht aus Halbleitermaterial an der Oberfläche der Halbleiterstruktur gebondet bleibt.
• Ausführungsform 9: Das Verfahren nach Ausführungsform 8, wobei Bonden des Substrats an die Oberfläche der Halbleiterstruktur direktes Bonden des Substrats an die Oberfläche der Halbleiterstruktur umfasst.
• Ausführungsform 10: Das Verfahren nach Ausführungsform 7, das des Weiteren Ausbilden wenigstens eines Abschnitts einer Vorrichtungsstruktur unter Verwendung der dünnen Schicht aus Halbleitermaterial umfasst.
• Ausführungsform 11: Das Verfahren nach Ausführungsform 10, wobei Ausbilden des wenigstens einen Abschnitts der Vorrichtungsstruktur unter Verwendung der dünnen Schicht aus Halbleitermaterial Ausbilden wenigstens eines Abschnitts eines Transistors unter Verwendung der dünnen Schicht aus Halbleitermaterial umfasst.
• Ausführungsform 12: Das Verfahren nach Ausführungsform 7, wobei Aufbringen der dünnen Schicht aus Halbleitermaterial über der Oberfläche der Halbleiterstruktur umfasst, dass die dünne Schicht so ausgebildet wird, dass sie eine durchschnittliche Dicke von ungefähr 300 nm oder weniger hat.
• Ausführungsform 13: Das Verfahren nach Ausführungsform 12, wobei Aufbringen der dünnen Schicht aus Halbleitermaterial über der Oberfläche der Halbleiterstruktur umfasst, dass die dünne Schicht so ausgebildet wird, dass sie eine durchschnittliche Dicke von ungefähr 100 nm oder weniger hat.
• Ausführungsform 14: Das Verfahren nach einer der Ausführungsformen 1 bis 13, das des Weiteren umfasst, dass die Halbleiterstruktur nach Ausbilden des ersten Abschnitts der wenigstens einen Wafer-Durchkontaktierung und vor Austauschen des Opfermaterials gegen das leitende Material verdünnt wird und der zweite Abschnitt der wenigstens einen Wafer-Durchkontaktierung ausgebildet wird.
• Ausführungsform 15: Das Verfahren nach Ausführungsform 14, wobei Verdünnen der Halbleiterstruktur Freilegen des Opfermaterials zu einer Außenseite der Halbleiterstruktur hin umfasst.
• Ausführungsform 16: Das Verfahren nach Ausführungsform 14, das des Weiteren umfasst: Anbringen der Halbleiterstruktur an einem Trägersubstrat vor dem Verdünnen der Halbleiterstruktur; und Entfernen des Trägersubstrats von der Halbleiterstruktur nach Verdünnen der Halbleiterstruktur.
• Ausführungsform 17: Ein Verfahren zum Herstellen einer Halbleiterstruktur, das umfasst: Aufbringen eines Opfermaterials in wenigstens einer Kontaktloch-Aussparung, die sich in eine Oberfläche einer Halbleiterstruktur hinein erstreckt; Aufbringen einer Schicht aus Halbleitermaterial über der Oberfläche der Halbleiterstruktur; Herstellen wenigstens einer Vorrichtungsstruktur unter Verwendung der Schicht aus Halbleitermaterial; Ausbilden eines ersten Abschnitts wenigstens einer Wafer-Durchkontaktierung, die sich durch die Schicht aus Halbleitermaterial hindurch erstreckt; Verdünnen der Halbleiterstruktur von einer Seite derselben her, die der Schicht aus Halbleitermaterial gegenüberliegt; Entfernen des Opfermaterials aus der wenigstens einen Kontaktloch-Aussparung in der Halbleiterstruktur und Freilegen des ersten Abschnitts der wenigstens einen Wafer-Durchkontaktierung in der Kontaktloch-Aussparung; sowie Aufbringen von leitendem Material in der Kontaktloch-Aussparung und Ausbilden eines zweiten Abschnitts der wenigstens einen Wafer-Durchkontaktierung.
• Ausführungsform 18: Das Verfahren nach Ausführungsform 17, wobei Aufbringen des Opfermaterials in der wenigstens einen Kontaktloch-Aussparung Aufbringen von Polysilizium-Material in der wenigstens einen Kontaktloch-Aussparung umfasst.
• Ausführungsform 19: Das Verfahren nach Ausführungsform 17 oder Ausführungsform 18, das des Weiteren Aufbringen eines dielektrischen Materials zwischen dem Opfermaterial und der Halbleiterstruktur in der wenigstens einen Kontaktloch-Aussparung umfasst.
• Ausführungsform 20: Das Verfahren nach einer der Ausführungsformen 17 bis 19, wobei Aufbringen der Schicht aus Halbleitermaterial über der Oberfläche der Halbleiterstruktur umfasst, dass die Schicht aus Halbleitermaterial von einem Substrat auf die Halbleiterstruktur übertragen wird.
• Ausführungsform 21: Das Verfahren nach Ausführungsform 20, wobei Übertragen der Schicht aus Halbleitermaterial von einem Substrat auf die Halbleiterstruktur umfasst: Implantieren von Ionen in das Substrat; Bonden des Substrats an die Halbleiterstruktur; und Brechen des Substrats entlang einer durch die implantierten Ionen in dem Substrat gebildeten Ebene und Trennen der Schicht aus Halbleitermaterial von einem verbleibenden Abschnitt des Substrats.
• Ausführungsform 22: Das Verfahren nach einer der Ausführungsformen 17 bis 21, wobei Aufbringen der Schicht aus Halbleitermaterial über der Oberfläche der Halbleiterstruktur umfasst, dass die Schicht aus Halbleitermaterial so ausgewählt wird, dass sie eine durchschnittliche Dicke von ungefähr 100 nm oder weniger hat.
• Ausführungsform 23: Das Verfahren nach einer der Ausführungsformen 17 bis 22, das des Weiteren umfasst: Anbringen der Halbleiterstruktur an einem Trägersubstrat vor Verdünnen der Halbleiterstruktur; und Entfernen des Trägersubstrats von der Halbleiterstruktur nach Verdünnen der Halbleiterstruktur.
• Ausführungsform 24: Das Verfahren nach einer der Ausführungsformen 17 bis 23, das des Weiteren Ausbilden eines leitenden Kontakthöckers an der wenigstens einen Wafer-Durchkontaktierung umfasst.
• Ausführungsform 25: Eine Halbleiterstruktur, die umfasst: ein Opfermaterial in wenigstens einer Aussparung, die sich von einer Oberfläche einer Halbleiterstruktur aus teilweise durch die Halbleiterstruktur hindurch erstreckt; ein Halbleiter-Material, das über der Oberfläche der Halbleiterstruktur angeordnet ist; wenigstens eine Vorrichtungsstruktur, die wenigstens einen Abschnitt des Halbleitermaterials umfasst, das über der Halbleiterstruktur angeordnet ist; einen ersten Abschnitt wenigstens einer Wafer-Durchkontaktierung, die sich durch das Halbleitermaterial hindurch erstreckt, das über der Oberfläche der Halbleiterstruktur angeordnet ist, wobei der erste Abschnitt der wenigstens einen Wafer-Durchkontaktierung auf die wenigstens eine Kontaktloch-Aussparung ausgerichtet ist.
• Ausführungsform 26: Die Halbleiterstruktur nach Ausführungsform 25, die des Weiteren ein Volumen aus dielektrischem Material umfasst, das wenigstens teilweise von dem über der Oberfläche der Halbleiterstruktur angeordneten Halbleitermaterial umgeben ist, wobei sich der erste Abschnitt der wenigstens einen Wafer-Durchkontaktierung durch das Volumen aus dielektrischen Material hindurch erstreckt und direkt mit ihm in Kontakt ist.
• Ausführungsform 27: Die Halbleiterstruktur nach Ausführungsform 26, wobei das Volumen aus dielektrischem Material eine flache Graben-Isolierstruktur umfasst.
• Ausführungsform 28: Die Halbleiterstruktur nach einer der Ausführungsformen 25 bis 27, wobei das Opfermaterial Polysilizium-Material umfasst.
• Ausführungsform 29: Die Halbleiterstruktur nach einer der Ausführungsformen 25 bis 28, wobei die wenigstens eine Vorrichtungsstruktur wenigstens einen Transistor umfasst.
• Ausführungsform 30: Die Halbleiterstruktur nach einer der Ausführungsformen 25 bis 29, wobei das Opfermaterial zu einer Außenseite der Halbleiterstruktur hin an einer Seite desselben freiliegt, die dem über der Oberfläche der Halbleiterstruktur angeordneten Halbleitermaterial gegenüberliegt.
• Ausführungsform 31: Die Halbleiterstruktur nach einer der Ausführungsformen 25 bis 30, die des Weiteren ein Trägersubstrat umfasst, das an der Halbleiterstruktur angebracht ist.
• Ausführungsform 32: Die Halbleiterstruktur nach einer der Ausführungsformen 25 bis 31, wobei das über der Oberfläche der Halbleiterstruktur angeordnete Halbleitermaterial eine Schicht des Halbleitermaterials umfasst, die eine durchschnittliche Dicke von ungefähr 300 nm oder weniger hat.
• Ausführungsform 33: Halbleiterstruktur nach Ausführungsform 32, wobei die Schicht des Halbleitermaterials eine durchschnittliche Dicke von ungefähr 100 nm oder weniger hat.
• Ausführungsform 34: Eine Halbleiterstruktur, die umfasst: eine aktive Fläche; eine hintere Fläche; wenigstens einen Transistor, der sich in der Halbleiterstruktur zwischen der aktiven Fläche und der hinteren Fläche befindet; wenigstens eine Wafer-Durchkontaktierung, die sich von der aktiven Fläche oder/und der hinteren Fläche wenigstens teilweise durch die Halbleiterstruktur hindurch erstreckt, wobei die wenigstens eine Wafer-Durchkontaktierung umfasst: einen ersten Abschnitt; einen zweiten Abschnitt; sowie eine erkennbare Grenze zwischen einer Mikrostruktur des ersten Abschnitts und einer Mikrostruktur des zweiten Abschnitts.
• Ausführungsform 35: Die Halbleiterstruktur nach Ausführungsform 34, wobei der wenigstens eine Transistor wenigstens einen Abschnitt einer dünnen Schicht aus Halbleitermaterial umfasst.
• Ausführungsform 36: Die Halbleiterstruktur nach Ausführungsform 35, wobei die dünne Schicht aus Halbleitermaterial eine durchschnittliche Dicke von ungefähr 100 nm oder weniger hat.
• Ausführungsform 37: Die Halbleiterstruktur nach Ausführungsform 35 oder Ausführungsform 36, wobei sich die erkennbare Grenze nahe an einer Hauptfläche der dünnen Schicht aus Halbleitermaterial befindet.
• Ausführungsform 38: die Die Halbleiterstruktur nach einer der Ausführungsformen 34 bis 37, wobei die erkennbare Grenze parallel zu der aktiven Fläche oder/und der hinteren Fläche ausgerichtet ist.

Additional, non-limiting embodiments of the invention are described below:

• Embodiment 1: A method of fabricating a semiconductor structure, comprising: depositing a sacrificial material in at least one contact hole recess extending partially through a semiconductor structure; Forming a first portion of at least one wafer via in the semiconductor structure and aligning the first portion of the at least one wafer via on the at least one via hole; and replacing the sacrificial material in the at least one via hole recess with conductive material and forming a second portion of the at least one wafer via in electrical contact with the first portion of the at least one wafer via.
• Embodiment 2: The method of embodiment 1, wherein forming a first portion of at least one wafer via in the semiconductor structure further comprises passing the first portion of the at least one wafer via through a dielectric material.
• Embodiment 3: The method of claim 1, wherein depositing the sacrificial material in the at least one via hole, which extends partially through the semiconductor structure, comprises: forming at least one non-continuous via hole recess extending partially through the semiconductor structure of one Surface extending therethrough; and depositing polysilicon material, a III-V semiconductor material and / or a dielectric material in the at least one non-via via hole.
• Embodiment 4: The method of claim 3, wherein depositing polysilicon material, a III-V semiconductor material, and / or a dielectric material in the at least one non-via via hole comprises depositing polysilicon material in the at least one non-continuous one Contact hole recess included.
• Embodiment 5: The method of Embodiment 3, further comprising forming the at least one via hole through solid silicon material.
• Embodiment 6: The method of embodiment 4, further comprising depositing a dielectric material between the bulk silicon material and the polysilicon material in the at least one non-via via hole.
• Embodiment 7: The method of embodiment 3, further comprising depositing a thin layer of semiconductor material over a surface of the semiconductor structure after depositing the polysilicon material in the at least one non-via via hole.
• Embodiment 8: The method of embodiment 7, wherein depositing the thin layer of semiconductor material over the surface of the semiconductor structure comprises: implanting ions into a substrate comprising semiconductor material to form a fracture surface in the substrate; Bonding the substrate to the surface of the semiconductor substrate and breaking the substrate along the fracture surface and separating the thin layer of semiconductor material from a remainder portion of the substrate, wherein the thin layer of semiconductor material remains bonded to the surface of the semiconductor structure.
• Embodiment 9: The method of embodiment 8, wherein bonding the substrate to the surface of the semiconductor structure comprises directly bonding the substrate to the surface of the semiconductor structure.
• Embodiment 10: The method of Embodiment 7, further comprising forming at least a portion of a device structure using the thin layer of semiconductor material.
• Embodiment 11: The method of embodiment 10, wherein forming the at least one portion of the device structure using the thin layer of semiconductor material comprises forming at least a portion of a transistor using the thin layer of semiconductor material.
• Embodiment 12: The method of Embodiment 7, wherein depositing the thin layer of semiconductor material over the Surface of the semiconductor structure includes that the thin film is formed to have an average thickness of about 300 nm or less.
• Embodiment 13: The method of embodiment 12, wherein depositing the thin layer of semiconductor material over the surface of the semiconductor structure comprises forming the thin layer to have an average thickness of about 100 nm or less.
• Embodiment 14: The method of one of embodiments 1 to 13, further comprising diluting the semiconductor structure against the conductive material after forming the first portion of the at least one wafer via and replacing the sacrificial material and the second portion of the at least one Wafer through-hole is formed.
• Embodiment 15: The method of embodiment 14, wherein diluting the semiconductor structure comprises exposing the sacrificial material to an exterior of the semiconductor structure.
• Embodiment 16: The method of embodiment 14, further comprising: attaching the semiconductor structure to a carrier substrate prior to thinning the semiconductor structure; and removing the carrier substrate from the semiconductor structure after thinning the semiconductor structure.
• Embodiment 17: A method of fabricating a semiconductor structure, comprising: depositing a sacrificial material in at least one contact hole recess extending into a surface of a semiconductor structure; Depositing a layer of semiconductor material over the surface of the semiconductor structure; Producing at least one device structure using the layer of semiconductor material; Forming a first portion of at least one wafer via extending through the layer of semiconductor material; Thinning the semiconductor structure from a side thereof facing the layer of semiconductor material; Removing the sacrificial material from the at least one via hole in the semiconductor structure and exposing the first portion of the at least one wafer via in the via hole recess; and depositing conductive material in the via hole recess and forming a second portion of the at least one wafer via.
• Embodiment 18: The method of embodiment 17, wherein depositing the sacrificial material in the at least one contact hole recess comprises depositing polysilicon material in the at least one contact hole recess.
• Embodiment 19: The method of embodiment 17 or embodiment 18, further comprising depositing a dielectric material between the sacrificial material and the semiconductor structure in the at least one via hole recess.
• Embodiment 20: The method of any one of embodiments 17 to 19, wherein depositing the layer of semiconductor material over the surface of the semiconductor structure comprises transferring the layer of semiconductor material from a substrate to the semiconductor structure.
• Embodiment 21: The method of embodiment 20, wherein transferring the layer of semiconductor material from a substrate to the semiconductor structure comprises: implanting ions into the substrate; Bonding the substrate to the semiconductor structure; and breaking the substrate along a plane formed by the implanted ions in the substrate and separating the layer of semiconductor material from a remaining portion of the substrate.
• Embodiment 22: The method of any one of embodiments 17 to 21, wherein depositing the layer of semiconductor material over the surface of the semiconductor structure comprises selecting the layer of semiconductor material to have an average thickness of about 100 nm or less.
• Embodiment 23: The method of any one of embodiments 17 to 22, further comprising: attaching the semiconductor structure to a carrier substrate prior to thinning the semiconductor structure; and removing the carrier substrate from the semiconductor structure after thinning the semiconductor structure.
• Embodiment 24: The method of any one of embodiments 17 to 23, further comprising forming a conductive bump on the at least one wafer via.
• Embodiment 25: A semiconductor structure comprising: a sacrificial material in at least one recess extending from a surface of a semiconductor structure partially through the semiconductor structure; a semiconductor material disposed over the surface of the semiconductor structure; at least one device structure comprising at least a portion of the semiconductor material disposed over the semiconductor structure; a first portion of at least one wafer via extending through the semiconductor material disposed over the surface of the semiconductor structure, wherein the first portion of the at least one wafer via is aligned with the at least one via recess.
• Embodiment 26: The semiconductor structure of embodiment 25, further comprising a volume of dielectric material at least partially surrounded by the semiconductor material disposed over the surface of the semiconductor structure, the first portion of the at least one wafer via extends through the volume of dielectric material and is in direct contact with it.
• Embodiment 27: The semiconductor structure of embodiment 26, wherein the volume of dielectric material comprises a shallow trench isolation structure.
• Embodiment 28: The semiconductor structure according to any one of Embodiments 25 to 27, wherein the sacrificial material comprises polysilicon material.
• Embodiment 29: The semiconductor structure according to one of embodiments 25 to 28, wherein the at least one device structure comprises at least one transistor.
• Embodiment 30: The semiconductor structure according to any one of Embodiments 25 to 29, wherein the sacrificial material is exposed to an outside of the semiconductor structure at a side thereof opposite to the semiconductor material disposed above the surface of the semiconductor structure.
• Embodiment 31: The semiconductor structure according to any one of Embodiments 25 to 30, further comprising a support substrate attached to the semiconductor structure.
• Embodiment 32: The semiconductor structure according to any one of Embodiments 25 to 31, wherein the semiconductor material disposed above the surface of the semiconductor structure comprises a layer of the semiconductor material having an average thickness of about 300 nm or less.
• Embodiment 33: The semiconductor structure according to Embodiment 32, wherein the layer of the semiconductor material has an average thickness of about 100 nm or less.
• Embodiment 34: A semiconductor structure comprising: an active area; a rear surface; at least one transistor located in the semiconductor structure between the active area and the rear area; at least one wafer via extending at least partially through the semiconductor structure from the active surface and / or the back surface, the at least one wafer via comprising: a first portion; a second section; and a detectable boundary between a microstructure of the first portion and a microstructure of the second portion.
• Embodiment 35: The semiconductor structure of Embodiment 34, wherein the at least one transistor comprises at least a portion of a thin layer of semiconductor material.
• Embodiment 36: The semiconductor structure of Embodiment 35, wherein the thin layer of semiconductor material has an average thickness of approximately 100 nm or less.
• Embodiment 37: The semiconductor structure according to Embodiment 35 or Embodiment 36, wherein the detectable boundary is close to a major surface of the thin film of semiconductor material.
• Embodiment 38: The semiconductor structure according to any one of Embodiments 34 to 37, wherein the detectable boundary is aligned parallel to the active area and / or the rear area.

Although embodiments of the present invention have been described using particular example, it will be appreciated by those skilled in the art that the invention is not limited to the details of the exemplary embodiments. Rather, numerous additions, omissions, and alterations may be made to the exemplary embodiments without departing from the scope of the invention as claimed below. For example, features of one embodiment may be combined with features of other embodiments and yet remain within the scope of the invention as provided by the inventors.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• US 39484 [0055]
• US 6303468 [0055]
• US 6335258 [0055]
• US Pat. No. 6,756,286 [0055]
• US 6809044 [0055]
• US 6946365 [0055]

Cited non-patent literature

• P. Garrou et al. "The Handbook of 3D Integration", Wiley-VCH (2008) [0003]

Claims (25)

A method of manufacturing a semiconductor structure comprising: Depositing a sacrificial material in at least one contact hole recess extending partially through a semiconductor structure; Forming a first portion of at least one wafer via in the semiconductor structure and aligning the first portion of the at least one wafer via on the at least one via hole; and Replacing the sacrificial material in the at least one via hole recess with conductive material and forming a second portion of the at least one wafer via in electrical contact with the first portion of the at least one wafer via. The method of claim 1, wherein forming a first portion of at least one wafer via in the semiconductor structure further comprises passing the first portion of the at least one wafer via through a dielectric material. The method of claim 1, wherein depositing the sacrificial material in the at least one via hole that extends partially through the semiconductor structure comprises: Forming at least one non-continuous via hole recess extending partially through the semiconductor structure from a surface thereof; and Depositing polysilicon material, silicon germanium (SiGe), III-V semiconductor material, and / or a dielectric material in the at least one non-via via hole. The method of claim 3, wherein applying polysilicon material, a III-V semiconductor material and / or a dielectric material in the at least one non-via via hole comprises depositing polysilicon material in the at least one non-via via hole. The method of claim 3, further comprising forming the at least one via hole through solid silicon material. The method of claim 5, further comprising depositing a dielectric material between the bulk silicon material and the polysilicon material in the at least one non-via via hole. The method of claim 3, further comprising depositing a thin layer of semiconductor material over a surface of the semiconductor structure after depositing the polysilicon material in the at least one non-via via hole. The method of claim 7, wherein applying the thin layer of semiconductor material over the surface of the semiconductor structure comprises: Implanting ions into a substrate comprising semiconductor material to form a fracture surface in the substrate; Bonding the substrate to the surface of the semiconductor substrate; such as Breaking the substrate along the fracture surface and separating the thin layer of semiconductor material from a remaining portion of the substrate, wherein the thin layer of semiconductor material remains bonded to the surface of the semiconductor structure. The method of claim 8, wherein bonding the substrate to the surface of the semiconductor structure comprises directly bonding the substrate to the surface of the semiconductor structure. The method of claim 7, further comprising forming at least a portion of a device structure using the thin layer of semiconductor material. The method of claim 10, wherein forming the at least a portion of the device structure using the thin layer of semiconductor material comprises forming at least a portion of a transistor using the thin layer of semiconductor material. The method of claim 7, wherein applying the thin layer of semiconductor material over the surface of the semiconductor structure comprises forming the thin layer to have an average thickness of about 300 nm or less. The method of claim 12, wherein applying the thin layer of semiconductor material over the surface of the semiconductor structure comprises forming the thin layer to have an average thickness of about 100 nm or less. The method of claim 1, further comprising thinning the semiconductor structure after forming the first portion of the at least one wafer via and replacing the sacrificial material with the conductive material and forming the second portion of the at least one wafer via. The method of claim 14, wherein diluting the semiconductor structure comprises exposing the sacrificial material to an exterior of the semiconductor structure. The method of claim 14, further comprising: Attaching the semiconductor structure to a carrier substrate prior to thinning the semiconductor structure; and Removing the carrier substrate from the semiconductor structure after thinning the semiconductor structure. Semiconductor structure comprising: a sacrificial material in at least one recess extending from a surface of a semiconductor structure partially through the semiconductor structure; and a semiconductor material disposed over the surface of the semiconductor structure. at least one device structure comprising at least a portion of the semiconductor material disposed over the semiconductor structure; and a first portion of at least one wafer via extending through the semiconductor material disposed over the surface of the semiconductor structure, wherein the first portion of the at least one wafer via is aligned with the at least one via recess. The semiconductor structure of claim 17, further comprising a volume of dielectric material at least partially surrounded by the semiconductor material disposed over the surface of the semiconductor structure, wherein the first portion of the at least one wafer via extends through the volume of dielectric material and directly in contact with him. The semiconductor structure of claim 18, wherein the volume of dielectric material comprises a shallow trench isolation structure. The semiconductor structure of claim 17, wherein the sacrificial material comprises polysilicon material. The semiconductor structure of claim 17, wherein the at least one device structure comprises at least one transistor. The semiconductor structure according to claim 17, wherein the sacrificial material is exposed to an outside of the semiconductor structure at a side thereof opposite to the semiconductor material disposed above the surface of the semiconductor structure. The semiconductor structure of claim 22, further comprising a carrier substrate attached to the semiconductor structure. The semiconductor structure of claim 17, wherein the semiconductor material disposed over the surface of the semiconductor structure comprises a layer of the semiconductor material having an average thickness of about 300 nm or less. The semiconductor structure of claim 19, wherein the layer of semiconductor material has an average thickness of about 100 nm or less.

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