DE112006003051A5 - Layoutverfahren für vertikale Leistungstransistoren variierbarer Kanalweite - Google Patents

Layoutverfahren für vertikale Leistungstransistoren variierbarer Kanalweite Download PDF

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Publication number
DE112006003051A5
DE112006003051A5 DE112006003051T DE112006003051T DE112006003051A5 DE 112006003051 A5 DE112006003051 A5 DE 112006003051A5 DE 112006003051 T DE112006003051 T DE 112006003051T DE 112006003051 T DE112006003051 T DE 112006003051T DE 112006003051 A5 DE112006003051 A5 DE 112006003051A5
Authority
DE
Germany
Prior art keywords
channel width
power transistors
vertical power
layout method
variable channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE112006003051T
Other languages
English (en)
Inventor
Ralf Lerner
Wolfgang Miesch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
X Fab Semiconductor Foundries GmbH
Alpha Microelectronics GmbH
Original Assignee
X Fab Semiconductor Foundries GmbH
Alpha Microelectronics GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by X Fab Semiconductor Foundries GmbH, Alpha Microelectronics GmbH filed Critical X Fab Semiconductor Foundries GmbH
Priority to DE112006003051T priority Critical patent/DE112006003051A5/de
Publication of DE112006003051A5 publication Critical patent/DE112006003051A5/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
DE112006003051T 2005-10-27 2006-10-25 Layoutverfahren für vertikale Leistungstransistoren variierbarer Kanalweite Withdrawn DE112006003051A5 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112006003051T DE112006003051A5 (de) 2005-10-27 2006-10-25 Layoutverfahren für vertikale Leistungstransistoren variierbarer Kanalweite

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102005051417.0 2005-10-27
DE102005051417A DE102005051417A1 (de) 2005-10-27 2005-10-27 Simulations- bzw. Layoutverfahren für vertikale Leistungstransistoren mit variierbarer Kanalweite und variierbarer Gate-Drain-Kapazität
DE112006003051T DE112006003051A5 (de) 2005-10-27 2006-10-25 Layoutverfahren für vertikale Leistungstransistoren variierbarer Kanalweite
PCT/EP2006/067774 WO2007048812A1 (de) 2005-10-27 2006-10-25 Layoutverfahren für vertikale leistungstransistoren variierbarer kanalweite

Publications (1)

Publication Number Publication Date
DE112006003051A5 true DE112006003051A5 (de) 2008-10-30

Family

ID=37697954

Family Applications (2)

Application Number Title Priority Date Filing Date
DE102005051417A Ceased DE102005051417A1 (de) 2005-10-27 2005-10-27 Simulations- bzw. Layoutverfahren für vertikale Leistungstransistoren mit variierbarer Kanalweite und variierbarer Gate-Drain-Kapazität
DE112006003051T Withdrawn DE112006003051A5 (de) 2005-10-27 2006-10-25 Layoutverfahren für vertikale Leistungstransistoren variierbarer Kanalweite

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE102005051417A Ceased DE102005051417A1 (de) 2005-10-27 2005-10-27 Simulations- bzw. Layoutverfahren für vertikale Leistungstransistoren mit variierbarer Kanalweite und variierbarer Gate-Drain-Kapazität

Country Status (4)

Country Link
US (1) US8448101B2 (de)
EP (1) EP1941407A1 (de)
DE (2) DE102005051417A1 (de)
WO (1) WO2007048812A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
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AU2009222165B2 (en) 2008-02-29 2015-07-09 Smith & Nephew, Inc. Gradient coating for biomedical applications
EP2268327B1 (de) 2008-02-29 2019-05-29 Smith & Nephew, Inc. Beschichtung und beschichtungsverfahren
CN102831254B (zh) * 2011-06-15 2015-12-02 中国科学院微电子研究所 Mos器件版图批量化设计方法

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Also Published As

Publication number Publication date
US20090007046A1 (en) 2009-01-01
US8448101B2 (en) 2013-05-21
WO2007048812A1 (de) 2007-05-03
DE102005051417A1 (de) 2007-05-03
EP1941407A1 (de) 2008-07-09

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8139 Disposal/non-payment of the annual fee