DE10310346B4 - Method for producing a photomask on a microstructure with trenches and corresponding use of the photomask - Google Patents

Abstract

Method for producing a photomask (PM ') on a microstructure (S) having a surface (O) and having one or more trenches (G1, G2; G), comprising the following steps:
Providing a filling layer (L) on the microstructure (S) for completely filling the trench (s) (G1, G2; G) and covering the surface (O) of the microstructure, in particular the semiconductor structure (S);
Forming a modified microstructure (S ') by withdrawing the fill layer (L) to the surface (O) of the original microstructure (S), leaving the trench (s) (G1, G2; G) filled with the fill layer (L), and Taking back the filling layer (L) by polishing;
Applying an auxiliary layer (A ') on the modified microstructure (S') having a substantially planar surface (O ') above the surface (O) of the original microstructure (S); and
Producing the photomask (PM ') on the substantially planar surface (O') of the auxiliary layer (A ').

Description

The The present invention relates to a method for producing a Photomask on a microstructure, in particular a semiconductor structure, with trenches and corresponding use of the photomask.

From the DE 101 51 628 A1 For example, such a method is known in which an only partially filled contact hole is filled with a first ARC layer, after which it is etched back by an etching and wherein the etching is continued to a point at which the entire ARC material substantially out the flat surface area of the substrate is removed. Subsequently, a further ARC layer is deposited on the structure and provided thereon a photomask.

The EP 0 525 942 A2 discloses etching of an ARC layer with doped or undoped oxygen plasma.

From the US 5,883,006 It is known to use a deliquescent oxide film to fill a contact hole, after which the film is ashed in an oxygen plasma to later turn off a planar ARC layer thereon.

The EP 1,160,843 A1 discloses the deposition of two ARC layers over a trench, wherein the first ARC layer lines the trench walls and the second ARC layer completely fills the trench.

The US 5,705,430 discloses depositing a SOG film in a contact hole while overfilling the contact hole.

The US 6,004,883 discloses depositing a dielectric layer in contact holes and then planarizing the dielectric layer.

The US 2003/0040174 A1 discloses a contact hole with a first BARC layer to fill and then another BARC layer before forming a resist to form trenches.

From the US 5,795,825 It is known to planarize trenches by means of sacrificial layers and etching back the same.

Under Microstructure should be both a microelectronic and a micromechanical structure can be understood.

Even though in principle be applicable to any integrated circuits the present invention and its underlying problem in relating to integrated memory circuits in silicon technology explained.

With introduction the 110 nm memory technology and at the latest with the introduction of the 90nm memory technology is a transition of lithography to the 193-nm generation connected to the required smallest structures to be able to depict.

The introduction ever shorter Wavelengths leads to the Rayleigh criterion for limiting the depth of focus, and therefore it is necessary to be extremely thin Use photoresist layers and as planar as possible wafer surfaces to produce the respective lithographic plane.

at some levels with not too deep trenches as structural elements the use of a planarizing anti-reflective coating, ARC for short called, under the photomask possible. At certain levels, however, this is not possible because the geometric the trenches in the structure are too big and the planarizing properties of the ARC are therefore no longer sufficient.

For example becomes at the first metal level of certain semiconductor memory devices to fill up from contact holes and above Metal webs a dual damascene process used, which a simultaneous filling of contact holes and the first metal level with metal allows. This will cost saved a second metallization process.

Certain Layouts of semiconductor memory cells see vias in Shape of oblong holes or elongated trenches in the contact hole plane for the Contacting of the substrate and the transistors of the memory cells in front. Through the long holes can the contact resistance lowered and the timing on the chip are positively influenced.

Based such slots or longer trenches Now, the problem underlying the present invention be explained in more detail.

3a - 3d are schematic representations of successive process stages of a production process for a photomask on a microstructure, in particular semiconductor structure, with trenches for illustrating the problem underlying the invention.

In 3a Reference symbol S denotes a microstructure, in particular a semiconductor structure, in cross-section, in which elongated trenches G1 and G2 par allel are provided to each other.

3b shows this microstructure, in particular semiconductor structure, in plan view.

If one applies to the microstructure, in particular semiconductor structure, S according to 3a respectively. 3b now an antireflection onsschicht A, so first the trenches are filled, resulting in the result of the trench webs only an insufficiently thin layer thickness of the antireflection layer A is present.

It So far, no process has been found that has a planarizing ARC filling of such trenches G1, G2 in a one-step process.

• – Geometrie der Gräben;
• – Belegungsdichte (Anzahl parallel verlaufender Gräben, Abstand zwischen den Gräben);
• – rheologische Eigenschaften des verwendeten ARCs; und
• – Prozessbedingungen beim Aufbringen des ARCs (aufgebrachte Menge, Drehzahl,...).

The filling of the trenches G1, G2 with the ARC depends on the following factors:

• - geometry of the trenches;
• - occupation density (number of parallel trenches, distance between trenches);
• - rheological properties of the ARC used; and
• - Process conditions when applying the ARC (applied quantity, speed, ...).

As in 3c the resulting layer thickness of the antireflection layer A on the structure surface O on the trench webs is not sufficient for a stable lithography process. The substrate is not sufficiently optically decoupled and the paint webs of the resulting photomask PM on the trench webs are partially not formed or fall over or are smeared.

at the subsequent Dual damascene process in the example of said memory cells can thereby shorts be generated between the tracks of the first metal level. In chip regions with low occupation density of the trenches can By contrast, the nominal ARC layer thickness can be achieved because the ARC not in the trenches or contact holes flows.

The The object of the present invention is a method for producing a photomask on a microstructure, in particular Semiconductor structure, with trenches and to indicate appropriate uses, by which the unwanted distribution prevents an auxiliary layer located under the photomask in the trenches.

According to the invention we this Task by the production method specified in claim 1 solved.

Of the Advantage of the present invention is that by the occurred Preplaning a planarization with the auxiliary layer used for example, the anti-reflection layer, is possible, so that about one Photomask with very good quality can be produced.

In the dependent claims find advantageous developments and improvements of in claim 1 specified production method.

According to one Another preferred embodiment, the auxiliary layer is an anti-reflection layer, the for extensive planarization and optical decoupling during the subsequent exposure needed becomes.

According to one Another preferred development, several trenches are present, the one elongated Have shape and are substantially parallel to each other, wherein the photomask has webs on the trench webs of the Ditches are lost.

preferred Uses of the invention produced Photomask are found in claims 4 to 7.

embodiments The invention is illustrated in the drawings and in the following Description closer explained.

It demonstrate:

1a - 1d schematic representations of successive process stages of a production process for a photomask on a microstructure, in particular semiconductor structure, as a first embodiment of the present invention;

2a - 2i schematic representations of successive process stages of a production process for a photomask on a microstructure, in particular semiconductor structure, as a second embodiment of the present invention; and

3a - 3d schematic representations of successive process stages of a production process for a photomask on a microstructure, in particular semiconductor structure, to illustrate the problem underlying the invention.

In the same reference numerals designate the same or functionally identical Ingredients.

1a - 1d are schematic representations of successive process stages ei A manufacturing method for a photomask on a microstructure, in particular semiconductor structure, as a first embodiment of the present invention.

In 1a reference numeral S already referred to at the outset in connection with 3a . 3b introduced microstructure, in particular semiconductor structure, with elongated trenches G1, G2. In the present first embodiment, a complete filling of the trenches takes place first and covers the surface O of the microstructure, in particular the semiconductor structure S, with a filling layer L, for example a pre-planarizing lacquer.

• – vollständige Füllung der Gräben G1, G2;
• – keine Hohlraumbildung in den Gräben;
• – gute Ätzbeständigkeit der Füllschicht, damit bei einem späteren Ätzprozess, beispielsweise Dual-Damascene Prozess die Gräben nicht ausgeweitet werden;
• – die Füllschicht muss vollständig aus den Gräben entfernbar sein; und
• – möglichst gute Planarisierungseigenschaften der Füllschicht.

The following requirements are placed on the filling layer L:

• - complete filling of the trenches G1, G2;
• - no cavitation in the trenches;
• Good etching resistance of the filling layer, so that in a later etching process, for example dual damascene process, the trenches are not widened;
• - the filling layer must be completely removable from the trenches; and
• - As good as possible planarizing properties of the filling layer.

In a subsequent process step, the in 1b is shown, the filling layer L is taken back at least to the surface O, in the example shown up to a distance Δ below the surface O. This withdrawal takes place according to the invention by polishing and creates a modified microstructure, in particular semiconductor structure, S '.

• – vollständiger Abtrag der Füllschicht L von der Oberfläche O über den gesamten Wafer;
• – keine Schädigung/kein Abtrag der Oberfläche O, insbesondere keine Aufweitung der Gräben G1, G2;
• – möglichst gleichmäßiges Zurückziehen der Füllschicht L in den Gräben G1, G2 in Bereichen mit unterschiedlicher Belegungsdichte; und
• – vollständige Entfernbarkeit der Füllschicht L ohne Schädigung der Mikrostruktur, insbesondere Halbleiterstruktur, im Falle eines Lithographie-Reworks.

This step should meet the following requirements:

• Complete removal of the filling layer L from the surface O over the entire wafer;
• No damage / no removal of the surface O, in particular no widening of the trenches G1, G2;
• - As uniform as possible retraction of the filling layer L in the trenches G1, G2 in areas with different occupation density; and
• Complete removability of the filling layer L without damaging the microstructure, in particular the semiconductor structure, in the case of a lithography rework.

As in 1c an antireflection layer A 'having planarizing properties can then be applied, as can also be used in other lithographic planes in which the deep, elongated trenches G1, G2 are absent. After the antireflection layer A 'after the pre-planarization with the filling layer L only has to compensate for small trench depths (depth Δ adjustable), only very small ARC layer thickness variations result over the entire wafer. In other words, the surface O 'of the antireflection layer A' is substantially planar except for small height differences in the region of the trenches G1, G2.

As in 1d 1, an intact photomask PM 'of photoresist can be applied over the surface O', by means of which the further process steps for structuring the modified microstructure, in particular the semiconductor structure, S 'can be carried out after appropriate through-etching of the antireflection layer A'.

To be noted that dependent From the respective application, the filling layer L to any later Time again from the trenches G1, G2 must be removable, preferably, if possible, in a common process step with the removal of the photoresist the photomask PM '.

2a - 2i 12 are schematic representations of successive process stages of a photomask fabrication process on a microstructure, in particular a semiconductor structure, as a second embodiment of the present invention.

2a shows an exemplary silicon semiconductor substrate 1 with a memory cell arrangement not further illustrated. W1, W2 are two adjacent word and gate line stacks, which consist of a polysilicon layer 20 with underlying gate oxide layer 10 , a silicide layer 30 , Sidewall spacers 40 made of silicon oxide and a silicon nitride cap 50 (including Seitenwandspacer) are constructed. In the substrate 1 a common source / drain region of two memory cells is located between the gate line stacks (not shown). Also not shown, for reasons of clarity, is a liner layer lying above this structure, which serves as a barrier against the diffusion of boron and phosphorus and which serves as an etch stop for subsequent silicon oxide etching. As a liner, for example, silicon nitride or silicon oxynitride is suitable.

In 2 B describe 60 and 70 a first and second silicon dioxide layer in which the word line stacks W1, W2 are embedded, and 80 an overlying polysilicon hardmask layer.

Between the two word line stacks W1, W2, a critical contact, which electrically contacts the common source / drain region, must be provided, since the spacing of the gates W1, W2 has a critical dimension. For the contact hole etch, the hardmask layer becomes 80 according to 2c structured. The state after the following contact hole etching is in 2d shown.

To clarify the relationship with the first embodiment according to 1a to 1d are in 2d the reference symbols S for the initial microstructure, in particular the semiconductor structure, O for the surface of the microstructure, in particular the semiconductor structure, and G for the trench or the contact hole are shown.

Regarding 2e then takes place the application and lowering of the filling layer L for pre-planning, the lowering here analogous to 1b again denoted by Δ. As already explained above, the antireflection layer A 'is planarized on the thus modified microstructure, in particular the semiconductor structure S', and the photomask PM 'is produced on its surface O', as in FIG 2f shown.

Regarding 2g then throughput of the antireflection layer A 'and the hard mask layer takes place 80 using the photomask PM ', wherein an etch process may be selected to reduce the structure, which has a taper angle in the hard mask layer 80 provides so that it has a smaller opening than the opening of the photomask PM '.

Regarding 2h Then, an etching of the upper oxide layer 70 using the hard mask 80 and the photomask PM 'to provide a widening above the contact corresponding to a trace connected to the contact. Subsequently, the possibly remaining in the upper region of the contact hole anti-reflection layer A 'and in the lower region still present filling layer L are removed, wherein in the latter step, the photomask PM' is removed simultaneously.

In the further course of the process, then, as in 2i shown a metal 120 For example, tungsten is deposited over the resulting structure and polished back, eventually including the hard mask layer 80 Will get removed.

S

Microstructure in particular Halbleiterstruk

door,

S '

modified Microstructure, in particular half

waveguide structure,

G, G1, G2

trenches

O, O'

surface

L

Vorplanarisierungslack

Δ

distance

A, A '

Antireflection coating

PM, PM '

photomask

1

Semiconductor substrate

10

gate oxide

20

polysilicon

30

metal silicide

40

sidewall

50

nitride cap (including -spacer)

W1, W2

Wordline stack

60 70

oxide layers

80

Hard mask layer (made of polysilicon)

120

metal filling

Claims (8)

Method for producing a photomask (PM ') on a microstructure (S) with a surface (O) and with one or more trenches (G1, G2, G), which comprises the following steps: Provide a filling layer (L) on the microstructure (S) for completely filling the trench (s) (G1, G2; G) and covering the surface (O) of the microstructure, in particular semiconductor structure, (S); Forming a modified one Microstructure (S ') by taking back the filling layer (L) to the surface (O) the original one Microstructure (S), wherein the one or more trenches (G1, G2, G) with the filling layer Filled (L) stay and take back the filling layer (L) done by polishing; Applying an auxiliary layer (A ') on the modified Microstructure (S ') with a substantially planar surface (O ') above the surface (O) of the original Microstructure (S); and  Producing the photomask (PM ') on the substantially planar surface (O ') of the auxiliary layer (A '). Method according to claim 1, characterized in that that the auxiliary layer (A ') is an antireflection layer. Method according to one of the preceding claims, characterized characterized in that several trenches (G1, G2, G) are present, which have an elongated shape and are substantially parallel to each other, wherein the photomask (PM ') has webs, on the ditches of the trenches (G1, G2; G). Use of the photomask according to claim 3, wherein by means of the photomask (PM ') the auxiliary layer (A ') and a portion of the trench lands of the trenches (G1, G2, G) are etched. Use of the photomask according to claim 3, wherein by means of the photomask (PM ') the auxiliary layer (A'), an underlying hardmask ( 80 ) and a section of the trench ridges of the Trenches (G1, G2, G) is etched. Use according to claim 4 or 5, wherein the filling layer (L), the auxiliary layer (A ') and the photomask (PM ') after etching be removed in a common step. Use according to claim 4, 5 or 6, wherein the trenches (G1, G2; G) contact holes for bit line contacts for semiconductor memory cells are. Use according to one of the preceding claims, wherein the microstructure (S) is a semiconductor structure.