DE10310346A1 - Manufacturing photomask on semiconductor structure, involves filling wells in semiconductor structure, removing filling layer, and forming photomask on planar surface of auxiliary layer - Google Patents

Abstract

The method involves filling the wells (G1,G2,G) and covering the surface of the semiconductor structure with a filling layer (L), forming a modified semiconductor structure (S') by removing the filling layer up to the surface (O) of the original semiconductor structure, leaving the wells at least partially filled. An auxiliary layer (A') is applied to the modified semiconductor structure with a planar surface (O') over the original surface (O). The photomask (PM') is manufacture on the planar surface of the auxiliary layer. An independent claim is included for the use of the photomask.

Description

The present invention relates to a method for producing a photomask on a microstructure, in particular semiconductor structure, with trenches and a corresponding one Use of the photomask.

Under microstructure, both a microelectronic as well as a micromechanical structure be understood.

Although in principle on any Integrated circuits applicable, the present invention as well as the underlying problem with regard to integrated Memory circuits in silicon technology explained.

With the introduction of 110 nm memory technology and at the latest with the introduction 90 nm memory technology is a switch from lithography to the 193 nm generation connected to the smallest required To be able to map structures.

The introduction of ever shorter wavelengths follows the Rayleigh criterion for limiting the depth of focus, and therefore it is necessary to be extremely thin Use photoresist layers and planar wafer surfaces if possible to generate the respective lithography level.

At some levels with not too deep trenches the use of a planarizing anti-reflection layer as structural elements, ARC for short, possible under the photomask. At certain levels however, this is not possible because the geometrical of the trenches are too large in structure and the planarizing properties of the ARC are therefore no longer sufficient.

For example, the first Metal level of certain semiconductor memory devices for filling up vias and above Metal tracks using a dual damascene process used, which a simultaneous filling of contact holes and the first metal level with metal. This will cost a second metallization process.

Certain layouts of semiconductor memory cells see contact holes in the form of elongated holes or elongated trenches in the via level for the Contacting the substrate and the transistors of the memory cells in front. Through the long holes can the contact resistances reduced and the timing on the chip can be positively influenced.

Using such elongated holes or elongated trenches is now the problem underlying the present invention are explained in more detail.

3a - d are schematic representations of successive process stages of a manufacturing process for a photomask on a microstructure, in particular semiconductor structure, with trenches to illustrate the problem on which the invention is based.

In 3a Reference symbol S denotes a microstructure, in particular a semiconductor structure, in cross section, in which elongated trenches G1 and G2 are provided parallel to one another.

3b shows this microstructure, in particular semiconductor structure, in plan view.

If one carries on the microstructure, in particular semiconductor structure, S according to 3a respectively. 3b now an antireflection layer A, the trenches are first filled, resulting in an insufficiently thin layer thickness of the antireflection layer A resulting on the trench webs.

No process has been found so far which is a planarizing ARC fill such trenches G1, G2 in a one-step process.

• – Geometrie der Gräben;
• – Belegungsdichte (Anzahl parallel verlaufender Gräben, Abstand zwischen den Gräben);
• – rheologische Eigenschaften des verwendeten ARCs; und
• – Prozessbedingungen beim Aufbringen des ARCs (aufgebrachte Menge, Drehzahl,...).

The filling of the trenches G1, G2 with the ARC depends on the following factors:

• - geometry of the trenches;
• - Occupancy density (number of trenches running in parallel, distance between the trenches);
• - rheological properties of the ARC used; and
• - Process conditions when applying the ARC (quantity applied, speed, ...).

As in 3c the resulting layer thickness of the antireflection layer A on the structural surface O on the trench webs is not sufficient for a stable lithography process. The surface is not sufficiently optically decoupled and the lacquer bars of the resulting photomask PM on the ditch bars are sometimes not formed or fall over or are smeared.

In the subsequent dual damascene process in the example of the memory cells mentioned, short circuits between them the conductor tracks of the first metal level are generated. In chip regions with a low occupancy of the trenches, however, the nominal ARC layer thickness can be achieved because the ARC does not flow into the trenches or contact holes.

The object of the present invention is a method of making a photomask a microstructure, in particular a semiconductor structure, with trenches and to indicate appropriate uses, by which the undesirable distribution prevent an auxiliary layer located under the photomask in the trenches.

According to the invention, this object is achieved by solved manufacturing method specified in claim 1.

The advantage of the present invention lies in the fact that a pre-planning takes place Planarization with the auxiliary layer used, for example the anti-reflection layer, is possible, so that a photomask of very good quality can be produced.

There are advantageous ones in the subclaims Developments and improvements to that specified in claim 1 Manufacturing process.

According to a preferred further training takes place when the modified microstructure is formed, in particular Semiconductor structure, a withdrawal the filling layer to below the surface the original Microstructure, in particular semiconductor structure.

According to another preferred Continuing education is the auxiliary layer an anti-reflection layer that for extensive planarization and for optical decoupling during the subsequent exposure needed becomes.

According to another preferred Continuing education takes place through the filling layer Etching back, ashing or polishing.

According to another preferred Continuing education is multiple trenches present, which is an elongated Have shape and run essentially parallel to each other, wherein the photomask has webs that rest on the trench webs Ditches run.

Preferred uses of those produced according to the invention Photomasks can be found in claims 6 to 9.

Embodiments of the invention are shown in the drawings and in the description below explained in more detail.

Show it:

1a - d schematic representations of successive process stages of a production process for a photomask on a microstructure, in particular semiconductor structure, as the first embodiment of the present invention;

2a - i schematic representations of successive process stages of a manufacturing process for a photomask on a microstructure, in particular semiconductor structure, as a second embodiment of the present invention; and

3a - d schematic representations of successive process stages of a production process for a photomask on a microstructure, in particular a semiconductor structure, to illustrate the problems on which the invention is based.

In the figures denote the same Reference numerals same or functionally identical components.

1a - d are schematic representations of successive process stages of a manufacturing process for a photomask on a microstructure, in particular semiconductor structure, as the first embodiment of the present invention.

In 1a Reference symbol S denotes the one already mentioned in connection with 3a . b introduced microstructure, in particular semiconductor structure, with elongated trenches G1, G2. In the present first embodiment, the trenches are first completely filled and cover the surface O of the microstructure, in particular the semiconductor structure, S with a filler layer L, for example a pre-planarization lacquer.

• – vollständige Füllung der Gräben G1, G2;
• – keine Hohlraumbildung in den Gräben;
• – gute Ätzbeständigkeit der Füllschicht, damit bei einem späteren Ätzprozess, beispielsweise Dual-Damascene Prozess die Gräben nicht ausgeweitet werden;
• – die Füllschicht muss vollständig aus den Gräben entfernbar sein; und
• – möglichst gute Planarisierungseigenschaften der Füllschicht.

The following requirements are placed on the filling layer L:

• - complete filling of the trenches G1, G2;
• - no cavities in the trenches;
• - Good etch resistance of the filling layer, so that the trenches are not widened in a later etching process, for example dual damascene process;
• - The filling layer must be completely removable from the trenches; and
• - The best possible planarization properties of the filling layer.

In a subsequent process step, which in 1b is shown, the filling layer L is withdrawn up to at least surface O, in the example shown up to a distance Δ below surface O. This removal is expediently carried out by etching back, ashing or polishing and creates a modified microstructure, in particular semiconductor structure, p '.

• – vollständiger Abtrag der Füllschicht L von der Oberfläche O über den gesamten Wafer;
• – keine Schädigung/kein Abtrag der Oberfläche O, insbesondere keine Aufweitung der Gräben G1, G2;
• – möglichst gleichmäßiges Zurückziehen der Füllschicht L in den Gräben G1, G2 in Bereichen mit unterschiedlicher Belegungsdichte; und
• – vollständige Entfernbarkeit der Füllschicht L ohne Schädigung der Mikrostruktur, insbesondere Halbleiterstruktur, im Falle eines Lithographie-Reworks.

The following requirements should be met at this step:

• Complete removal of the filling layer L from the surface O over the entire wafer;
• - no damage / no removal of the surface O, in particular no widening of the trenches G1, G2;
• Retraction of the filling layer L in the trenches G1, G2 in areas with different occupancy density as uniformly as possible; and
• - The filler layer L can be completely removed without damaging the microstructure, in particular the semiconductor structure, in the case of a lithography rework.

As in 1c shown, an antireflection layer A 'with planarizing properties can then be applied, as can also be used in other lithography planes in which the deep, elongated trenches G1, G2 are not present. Since the antireflection layer A 'only has to compensate for small trench depths after the pre-planarization with the filling layer L (depth Δ adjustable), there are only very small ARC layer thickness fluctuations when viewed over the entire wafer. In other words, the surface O 'of the anti-reflection layer A' is essentially planar - apart from small height differences in the region of the trenches G1, G2.

As in 1d shown, an intact photomask PM 'made of photoresist can be applied over the surface O', by means of which the further process steps for structuring the modified microstructure, in particular semiconductor structure, S 'can be carried out after the antireflection layer A' has been appropriately etched through.

It should be noted that depending on the the filler layer in each application L to any later Time again from the trenches G1, G2 must be removable, preferably, if possible, in a common process step with the removal of the photoresist the PM 'photo mask.

2a - i are schematic representations of successive process stages of a manufacturing process for a photomask on a microstructure, in particular semiconductor structure, as a second embodiment of the present invention.

2a shows an exemplary silicon semiconductor substrate 1 with a memory cell arrangement not illustrated in detail. W1, W2 are two adjacent word or gate line stacks, which consist of a polysilicon layer 20 with underlying gate oxide layer 10 , a silicide layer 30 , Sidewall spacers 40 made of silicon oxide and a silicon nitride cap 50 (including sidewall spacers). In the substrate 1 there is a common source / drain region (not shown) of two memory cells between the gate line stacks. Also not shown for reasons of clarity is a liner layer lying above this structure, which serves as a barrier against the diffusion of boron and phosphorus and which serves as an etch stop for a later silicon oxide etching. For example, silicon nitride or silicon oxynitride is suitable as the liner layer.

In 2 B describe 60 and 70 first and second silicon dioxide layers in which the word line stacks W1, W2 are embedded, and 80 an overlying hard mask layer made of polysilicon.

A critical contact, which electrically contacts the common source / drain region, must be provided between the two word line stacks W1, W2, since the distance between the gate stacks W1, W2 has a critical dimension. The hard mask layer is used for the contact hole etching 80 according to 2c structured. The state after the following contact hole etching is in 2d shown.

To clarify the connection with the first embodiment according to 1a to d are in 2d the reference symbols S for the initial microstructure, in particular the semiconductor structure, O for the surface of the microstructure, in particular the semiconductor structure, and G for the trench or the contact hole.

Regarding 2e Then the filling layer L is applied and lowered for pre-planing, the lowering here being analogous to 1b has again been designated Δ. As already explained above, the anti-reflection layer A 'is applied in a planarizing manner to the modified microstructure, in particular the semiconductor structure S', and the photomask PM 'is produced on its surface O', as in 2f shown.

Regarding 2g the antireflection layer A 'and the hard mask layer are then etched through 80 using the photomask PM ', wherein an etching process can be selected to reduce the structure, which has a taper angle in the hard mask layer 80 provides so that it has a smaller opening than the opening of the photomask PM '.

Regarding 2h the upper oxide layer is then etched 70 using the hard mask 80 and the photomask PM 'to provide a widening above the contact which corresponds to a conductor track which is connected to the contact. Subsequently, the antireflection layer A 'possibly remaining in the upper region of the contact hole and the filling layer L still present in the lower region are removed, the photomask PM' being removed at the same time in the latter step.

In the further course of the process, as in 2i shown a metal 120 , for example, tungsten is deposited over the resulting structure and polished back, finally also the hard mask layer 80 Will get removed.

S

Microstructure especially semiconductor structure

door,

S '

modified Microstructure, especially half

waveguide structure,

G, G1, G2

trenches

O, O'

surface

L

Vorplanarisierungslack

Δ

distance

A, A '

Antireflection coating

PM, PM '

photomask

1

Semiconductor substrate

10

gate oxide

20

polysilicon

30

metal silicide

40

sidewall

50

nitride cap (including spacer)

W1, W2

Wordline stack

60 70

oxide layers

80

Hard mask layer (made of polysilicon)

120

metal filling

Claims (9)

Method for producing a photomask (PM ') on a microstructure, in particular semi-lead ter structure, (S) with a surface (O) and with one or more trenches (G1, G2; G), which has the following steps: providing a filler layer (L) on the microstructure, in particular semiconductor structure, (S) for completely filling the or the trenches (G1, G2; G) and for covering the surface (O) of the microstructure, in particular semiconductor structure, (S); Forming a modified microstructure, in particular semiconductor structure, (S ') by taking back the filling layer (L) up to at least the surface (O) of the original microstructure, in particular semiconductor structure, (S), the trench (s) (G1, G2; G) at least partly remain filled with the filling layer (L); Application of an auxiliary layer (A ') on the modified microstructure, in particular semiconductor structure, (S') with an essentially planar surface (O ') above the surface (O) of the original microstructure, in particular semiconductor structure, (S); and producing the photomask (PM ') on the substantially planar surface (O') of the auxiliary layer (A '). A method according to claim 1, characterized in that when forming the modified microstructure, in particular semiconductor structure, (S ') a withdrawal the filling layer (L) to below the surface (O) the original Microstructure, in particular semiconductor structure, (S) takes place. A method according to claim 1 or 2, characterized in that the auxiliary layer (A ') is an anti-reflective layer. Method according to one of the preceding claims, characterized characterized that withdrawal the filling layer (L) by etching back, ashing or polishing. Method according to one of the preceding claims, characterized characterized that multiple trenches (G1, G2; G) are present which have an elongated shape and run essentially parallel to one another, the photomask (PM ') has webs, on the trenches of the trenches (G1, G2; G) run. Use of the photomask according to claim 5, wherein using the photomask (PM ') the auxiliary layer (A ') and a section of the trench webs of the trenches (G1, G2; G) are etched. Use of the photomask according to claim 5, wherein by means of the photomask (PM ') the auxiliary layer (A'), an underlying hard mask ( 80 ) are etched and a section of the trench webs of the trenches (G1, G2; G) is etched. Use according to claim 6 or 7, wherein the filling layer (L), the auxiliary layer (A ') and the photomask (PM ') after the etching be removed in a common step. Use according to claim 6, 7 or 8, wherein the trenches (G1, G2; G) contact holes for bit line contacts for semiconductor memory cells are.