DE10246389B4 - Method for producing a trench semiconductor device - Google Patents

Abstract

A method of manufacturing a trench semiconductor device, comprising the following steps:
(a) forming a trench (2) in a semiconductor body (1),
(b) forming the insulating layer (3) on the bottom and the wall of the trench (2),
(c) depositing polycrystalline silicon (4) in the trench (2) and on the surface of the semiconductor body (1),
(d) back etching of the polycrystalline silicon (4) from the surface of the semiconductor body (1) and from the upper region of the trench (2),
(e) applying a further material (10) to fill the trench and cover the surface of the semiconductor body,
(f) planarizing the surface by removing the deposited further material up to the surface of the semiconductor body (1),
(h) implanting at least one doped zone (6, 13) with associated temperature treatments to form at least one zone of a body zone (6) and a source zone (13),
(i) applying an intermediate oxide layer (14),
(j) forming at least one contact hole (15) in the intermediate oxide layer (14), in which ...

Description

The The present invention relates to a method for producing a Trench semiconductor device, in particular trench power semiconductor device, in that after creating a trench in a semiconductor body, slip at least parts of the trench walls with an insulating layer and at least partially filling the trench with a first material, in particular polycrystalline Silicon, in the semiconductor body at least one doped zone by ion implantation in addition to the trench is introduced.

at The production of trench power transistors become source zones and body zones preferably by means of implantations and subsequent annealing brought in. The implantations are usually in a process stage executed in which the trench already with an insulating layer as a gate oxide and polycrystalline silicon is filled as a gate electrode, wherein the polycrystalline silicon by means of a Recessätzung (Aussparungsätzung) again from the surface of the semiconductor body was removed.

The implantations made at this stage of the process the source zone and the body zone cause unwanted trench sidewall implants by lateral "straggling" (lateral spreading) and imperfect "0 ° tilt" (pitch) setting the implantation source with respect to the trench sidewalls and / or through taped (or oblique) Trench sidewalls. Such unwanted trench sidewall implants often even reach later Channel region of the trench transistors and thus influence their Threshold voltage. This in turn results in large spreads the threshold voltages of Tenchtransistoren produced, wherein even failures not exclude them to let.

In order to avoid such unwanted trench sidewall implantations, it has already been thought that the production of the source zone and the body zone should be completely preferred by implantation before the trench etching, as described in US Pat US 5 648 670 (See there especially the 3A to 3C ) is proposed. However, such a procedure inevitably has the disadvantage that the complete and large temperature budget of the so-called "trench block", ie the process steps for trench production by etching, oxidation in the trench to produce the gate oxide and the deposition of polycrystalline silicon, on the already implanted source and In some cases, such an effect is still acceptable for a body zone, although this is not true for the mostly flat source zones, since the aforementioned large temperature budget of the trench block leads to a correspondingly strong outdiffusion of the source zone. Zones leads and they lose their flat profile.

Besides that is to keep in mind that even the slightest fluctuations in the temperature budget of the trench block directly and strongly on the doping profiles of body zone and source zone and thus affect the parameters of the completed trench transistor influence.

by virtue of the above considerations, after which the source zone across from the high temperature budget of the trench block particularly critical reacted, was already thought of the implantation for the introduction the source zone to drive in several stages and thereby affect the trench sidewall by appropriate adjustment of dose and Energy as well as by means of an additional Minimize photo level.

Instead of an additional photo plane may be used for masking in the production of the source zone optionally also a spacer process, as shown in the US 6 051 468 is described.

It so many efforts have been made, unwanted Trench sidewall implants and thus strong application voltage scattering to avoid trench transistors.

As a general example of a trench power transistor is on the US 5 034 785 Here, the trench, in the lower region of which a polycrystalline silicon gate electrode is provided and whose upper half adjoins a body zone and a source zone embedded in it, is closed with an oxide plug whose upper edge is clearly above the surface the semiconductor body protrudes or could also be designed coplanar. The production of this trench power transistor takes place in the manner already described above: body zone and source zone are introduced before the trench etching, so that they are exposed to the high temperature budget of the trench block.

Furthermore, from the US Pat. No. 5,918,114 A method of fabricating a vertical semiconductor device is known in which a source region and a body region are implanted after a gate polysilicon in a trench has been oxidized in its upper region to a thick oxide.

The US 5 099 304 describes a semiconductor device with an insulating trench, wherein in a lower region polysilicon is provided, while the upper region by an insulating layer is formed from, for example Borphosphorsilikatglas. Planarization occurs here with respect to the surface of a silicon nitride layer.

Finally, it is still out of the US 4,835,115 a method of forming an oxide-covered trench isolation is known. Also in this method, no further implantation is carried out after the production of the trench isolation.

It It is an object of the present invention to provide a method for manufacturing a trench semiconductor device to indicate in which unwanted Trench sidewall implantations be avoided without exposing implanted zones to a trench block, and ensuring good contact with a doped zone is.

These Task is in accordance with the invention in a method of the type mentioned a method with the features of claim 1 solved.

Of the So Trench becomes essentially complete with another material first filled and only then made the at least one ion implantation becomes. For the introduction of this further material in the trench is suitable the deposition of an oxide, in particular silicon dioxide, wherein preferably also TEOS (tetraethylene orthosilicate), USG (undoped silicate glass), PSG (phosphosilicate glass) or BPSG (borophosphosilicate glass) for Application reach.

• (a) Im Halbleiterkörper wird zunächst ein Trench, vorzugsweise durch Ätzen, ausgebildet.
• (b) Wände und Boden des Trenches werden mit einer Oxidschicht, insbesondere einer Siliziumdioxidschicht, versehen, wozu große Temperaturbudgets erforderlich sind.
• (c) In den Trench hinein und auf der Oberfläche des Halbleiterkörpers wird polykristallines Silizium abgeschieden.
• (d) Es schließt sich eine Polyrecessätzung an, bei der das polykristalline Silizium im oberen Bereich des Trenches und auf der Oberfläche des Halbleiterkörpers wieder entfernt wird.
• (e) Es wird eine Isolierschicht, insbesondere eine Siliziumdioxidschicht und vorzugsweise eine Schicht aus TEOS, USG, PSG oder BPSG abgeschieden, um den oberen Bereich des Trenches aufzufüllen und die Oberfläche des Halbleiterkörpers zu bedecken.
• (f) Mittels eines CMP-Schrittes (CMP = chemisch-mechanisches Polieren) und vorzugsweise eines TEOS-CMP-Schrittes wird die Oberfläche bis zum Silizium des Halbleiterkörpers planarisiert.
• (g) Optional kann anschließend ein definiertes Streuoxid für nachfolgende Implantationen aufgebracht werden (dieser Schritt kann gegebenenfalls auch weggelassen werden).
• (h) Es werden sodann Implantationen mit zugehörigen Temperungen vorzugsweise für Body-Zone, Source-Zone und Body-Kontakgebiete vorgenommen.
• (i) Es schließt sich die Abscheidung einer Zwischenoxidschicht auf der Oberfläche des planarisierten und gegebenenfalls mit dem Streuoxid versehenen Halbleiterkörpers an.
• (j) In der Zwischenoxidschicht werden sodann Kontaktlöcher für die Source-Zone bzw. Body-Zone ausgebildet.
• (k) Über die Kontaktlöcher wird schließlich eine Metallisierung zu der Body-Zone bzw. Source-Zone geführt.

The process steps of a "process flow" carried out in the method for producing a trench semiconductor component, in particular a trench power transistor, can be summarized as follows:

• (a) In the semiconductor body, a trench is first formed, preferably by etching.
• (b) Walls and bottom of the trench are provided with an oxide layer, in particular a silicon dioxide layer, which requires large temperature budgets.
• (c) Polycrystalline silicon is deposited in the trench and on the surface of the semiconductor body.
• (D) This is followed by a Polyrecessätzung, in which the polycrystalline silicon in the upper region of the trench and on the surface of the semiconductor body is removed again.
• (e) An insulating layer, in particular a silicon dioxide layer and preferably a layer of TEOS, USG, PSG or BPSG is deposited in order to fill up the upper region of the trench and to cover the surface of the semiconductor body.
• (f) By means of a CMP step (CMP = chemical-mechanical polishing) and preferably a TEOS-CMP step, the surface is planarized to the silicon of the semiconductor body.
• (g) Optionally, then a defined littering oxide for subsequent implantations can be applied (this step can also be omitted if necessary).
• (h) Implants with associated anneals are then preferably made for body zone, source zone and body contact areas.
• (i) The deposition of an intermediate oxide layer on the surface of the planarized semiconductor body optionally provided with the scattering oxide follows.
• (j) Contact holes are then formed in the intermediate oxide layer for the source zone or body zone.
• (k) Via the contact holes, a metallization is finally led to the body zone or source zone.

In the process block with the method steps (e) to (h) is the Trench sealed with the insulating layer; the iso lierschicht is then planarized by means of the CMP step and thus provides a reproducible and uniform basis for all subsequent implants of step (h). These implants of step (h) but no unwanted Trench sidewall implants produce more, since those in the trench insulating layer of step (e) the trench sidewall reliable masked.

• – Es treten keine ungewollten Trenchseitenwand-Implantation auf, da die Isolierschicht des Verfahrensschrittes (e) im Trench die Implantationen für Source-Zone und Body-Zone maskiert.
• – Durch eine planare und gemeinsame Basis nach dem CMP-Schritt (f) ist eine hohe Reproduzierbarkeit für die Implantationen gewährleistet, wobei optional noch ein definiertes Streuoxid (Schritt (g)) eingeführt werden kann.
• – Das hohe Temperaturbudget des Trenchblockes der Schritte (a) bis (c) beeinflusst die Ausbildung der Source-Zone und der Body-Zone nicht.
• – Der hohe Aufwand für mehrstufige Implantationen für die Source-Zone wird vermieden; außerdem sind keine zusätzlichen Fototechniken und Maskenebenen erforderlich; schließlich ist kein Spacerprozess notwendig. Insgesamt liegt aber eine nicht unerhebliche Prozessvereinfachung vor.

The present method offers a number of advantages:

• - There is no unwanted trench sidewall implantation, since the insulating layer of process step (e) in the trench mask the implantations for source zone and body zone.
• By a planar and common base after the CMP step (f) a high reproducibility for the implantations is ensured, whereby optionally a defined litter oxide (step (g)) can be introduced.
• The high temperature budget of the trench block of steps (a) to (c) does not affect the formation of the source zone and the body zone.
• - The high cost of multi-stage implantation for the source zone is avoided; In addition, no additional photo techniques and mask levels are required; finally, no spacer process is necessary. Overall, however, there is a considerable process simplification.

Another essential aspect of the invention is that to increase the Kon contact surface over the etching of the insulating layer in the upper part of the trench is partially removed and remain Mesabereiche between adjacent Trenchs. It is here so just to the trench transistor of the US 5 034 785 opposite approach taken: the surface of the semiconductor body is lowered in the area of the Trench and not as in the US 5 034 785 increased or coplanar. Thus, in the method according to the invention, elevated mesas are present between adjacent trenches and not over the trench itself. By lowering in the region of the trench, an increased contact surface can be ensured, especially for the source zone and the body zone, which reduces the contact resistance. This is particularly advantageous if the contact surface is very small by itself without this measure, for example if the mesa width is smaller than the trench width and also smaller than 2.5 times the insulating layer thickness of the gate oxide in the trench.

following The invention will be explained in more detail with reference to the drawings. Show it:

1a and 1b Sectional views for explaining the method according to the invention ( 1a ) in comparison to the conventional method ( 1b )

2a to 2l Sectional views to explain the process flow, and

2k ' and 2l ' Sectional views for explaining the method according to the invention.

1b serves to explain how it comes with conventional methods to an unwanted Trench sidewall implantation. An example n-type semiconductor body 1 has a trench 2 on, its side wall and floor with an insulating layer 3 made of, for example, silicon dioxide as the gate oxide. After repainting originally the trench 2 filling doped polycrystalline silicon 4 lies the upper part of the trench 2 free. On the surface of the semiconductor body 1 there is still a litter oxide layer (STROX) 5 from, for example, silicon dioxide.

Now an implantation followed by temperature treatment is made to a p-conducting body or bulk zone 6 ' to generate, as indicated by arrows 7 is indicated, even if the implantation takes place at an angle of incidence of 0 ° (0 ° -Tilt), trench sidewall implantation occurs in one area 8th on that in 1b for highlighting with a circle 9 is provided.

This trench sidewall implantation in the area 8th elicits the above-mentioned disadvantages.

The main difference between the present method and that based on 1b explained conventional method can be seen when the 1a , which serves to explain the method according to the invention, with the 1b In the present process, after the back-etching of the polycrystalline silicon 4 in the trench 2 Thus, after the poly-etch etch (see method step (d) above), an insulating material, preferably a silicon dioxide layer, and in particular a layer of TEOS or USG or PSG or BPSG for filling the trench 2 and for covering the semiconductor body 1 (see the above method step (e)), followed by planarization of the surface of the silicon body by a CMP step (see method step (f) above) and possibly also the litter oxide layer 5 is applied (see the above process step (g)). Only then is the implantation (see arrows 7 ) made, for example, the body zone 6 and to implant a source zone. Here then masked in the upper part of the trench 2 remaining insulating material 10 So, for example, preferably TEOS, the trench side wall, so that reliably no areas here 8th , so no trench sidewall implants occur.

In the present invention, the insulating material 10 in the trench 2 in its surface area still below the surface of the semiconductor body 1 etched back to a depth of about 100 to 300 nm and in particular 200 nm, as indicated by a dashed line 11 in insulating material 10 is suggested, so that a larger contact area for a metallization to the body zone 6 and to the source zone arises. However, this will be explained below on the basis of 2k ' will be explained in more detail.

In detail, the process flow in the present method is now based on the 2a to 2l described in these figures for corresponding components, the same reference numerals as in the 1a and 1b be used.

First, as in 2a is shown in a semiconductor body 1 by means of a masking layer 12 made of, for example, silicon dioxide or silicon nitride a trench 2 introduced by etching. For the semiconductor body 1 For example, n- or p-doped silicon or another suitable semiconductor material such as SiC or a compound semiconductor may be selected. In the following, it is assumed that the semiconductor body 1 consists of n-doped silicon.

Then, a gate oxidation is carried out at the bottom and at the sidewalls of the trench 2 an insulating layer 3 is formed from, for example, silicon dioxide. This is the in 2 B shown structure. Optionally, also the masking layer 12 be removed before the gate oxidation.

This is followed by deposition of doped polycrystalline silicon 4 in the trench 2 and on the surface of the semiconductor body 1 or the masking layer 12 so that the in 2c structure shown is obtained.

This is followed by back etching of the polycrystalline silicon from the surface of the semiconductor body 1 and from the top of the trench 2 , After this "polyrecess" the in 2d obtained arrangement shown.

Subsequently, the following steps of the method are carried out: Instead of an ion implantation to form the body zone becomes an insulating layer 10 from, for example, TEOS in the upper part of the trench 2 and on the surface of the semiconductor body 1 deposited. This is the in 2e represented structure before. Instead of TEOS, other suitable materials may be used.

This is followed by a CMP step in which the insulating layer 10 , that is the TEOS, on the surface of the semiconductor body 1 as well as the masking layer 12 and optionally also surface areas of the semiconductor body 1 be removed to obtain a planarized surface, as in 2f is shown.

Optionally, a scattering oxide layer can be applied to the planarized surface 5 be applied. However, this step can also be omitted if necessary. That is, the scattering oxide layer 5 does not necessarily have to be applied. Will the litter oxide layer 5 however formed, so lies the in 2g represented structure before.

This is followed by an implantation in order to be in the semiconductor body 1 a p-doped profile for a body zone 6 ' to build. Is the semiconductor body 1 p-doped, this profile becomes the body zone 6 ' provided with an n-doping. This process step with the implantation 7 is in 2h illustrated. As can be seen immediately from this figure, the insulating material masks 10 , so for example the TEOS, in the upper part of the trench 2 its sidewall so that areas with sidewall implantation can not occur even if there is no full 0 ° tilt ("0 ° tilt").

It then joins in the usual way to a temperature treatment, in which an actual body zone 6 by diffusion from the profile of 2h is produced. This is the in 2i illustrated structure with the extended body zone 6 in front.

This is followed by another implantation step with a temperature treatment (drive) to form a source zone 13 in the surface area of the body zone 6 , On the surface of the litter oxide layer 5 then an intermediate oxide layer (ZWOX) 14 made of, for example, silicon dioxide as a masking layer. This is the in 2y illustrated arrangement.

Then, in the intermediate oxide layer 14 and the scattering oxide layer 5 a contact hole 15 introduced by etching. It is in the upper part of the trench 2 the insulating material 10 with the insulating layer (gate oxide) 3 to a dashed line 11 removed to contact the source zone 13 enlarge the available area. It arises so in the 2k shown arrangement. Will the insulating material 10 to the dashed line 11 removed, an arrangement is obtained, as in 2k ' With 2 Trenches is shown. Between the two trenches 2 then lies a mesa area 18 , This mesa area 18 preferably has a width W between the two adjacent trenches which is smaller than the trench width D and, in the preferred embodiment, is smaller than 2.5 times the thickness d of the insulating layer 3 (In the figures, the width W is shown enlarged for clarity).

Finally, as in 2l respectively. 2l ' is shown, still in the contact hole 15 a source metallization 16 and on the back of the semiconductor body 1 a drain metallization 17 applied. Both metallizations 16 and 17 For example, they can be made of aluminum.

1

Semiconductor body

2

trench

3

insulating

4

polycrystalline silicon

5

screen oxide

6 6 '

Body zone

7

implantation

8th

area with trench sidewall implantation

9

circle

10

insulating material

11

dotted line

12

masking layer

13

Source zone

14

intermediate oxide

15

contact hole

16

Source metallization

17

Drain metallization

18

mesa

W

Mesaweite

D

trench width

d

thickness the insulating layer

Claims (7)

A method of fabricating a trench semiconductor device, comprising the steps of: (a) forming a trench ( 2 ) in a semiconductor body ( 1 ), (b) forming the insulating layer ( 3 ) on the bottom and the wall of the trench ( 2 ), (c) depositing polycrystalline silicon ( 4 ) in the trench ( 2 ) and on the surface of the semiconductor body ( 1 ), (d) back etching of the polycrystalline silicon ( 4 ) from the surface of the semiconductor body ( 1 ) and from the upper part of the trench ( 2 ), (e) applying another material ( 10 for filling the trench and covering the surface of the semiconductor body, (f) planarizing the surface by removing the deposited further material up to the surface of the semiconductor body ( 1 ), (h) implanting at least one doped zone ( 6 . 13 ) with associated temperature treatments to form at least one zone from a body zone ( 6 ) and a source zone ( 13 ), (i) applying an intermediate oxide layer ( 14 ), (j) forming at least one contact hole ( 15 ) in the intermediate oxide layer ( 14 ), in which to increase the contact surface of a metallization layer ( 16 ) to the source zone ( 13 ) and / or Bodyzone ( 6 ) a contact hole overetching (see dashed line 11 ) is carried out so that the applied further material ( 10 ) with insulating layer ( 3 ) is partially removed and mesa areas ( 18 ) between adjacent trenches ( 2 . 2 ' ), and (k) applying the metallization ( 16 . 17 ) in the contact hole ( 15 ). A method according to claim 1, characterized by the following step after step (f): (g) applying a defined scattering oxide layer ( 5 ) on the planarized surface. A method according to claim 1 or 2, characterized in that the Mesaweite (W) smaller than the trench width (D) and / or smaller than 2.5 times the thickness (d) of the insulating layer ( 3 ). Method according to one of claims 1 to 3, characterized in that for the further material ( 10 ) an insulating material is used. Method according to claim 4, characterized in that that for the insulating material TEOS, USG, PSG or BPSG is used. Method according to one of claims 1 to 5, characterized in that the mesa areas ( 18 ) have a height of 100 to 300 nm and preferably 200 nm. Method according to one of claims 1 to 6, characterized that the planarization in process step (f) by chemical-mechanical polishing he follows.