DE102009024311A1 - Semiconductor component and method for its production - Google Patents
Semiconductor component and method for its production Download PDFInfo
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- DE102009024311A1 DE102009024311A1 DE200910024311 DE102009024311A DE102009024311A1 DE 102009024311 A1 DE102009024311 A1 DE 102009024311A1 DE 200910024311 DE200910024311 DE 200910024311 DE 102009024311 A DE102009024311 A DE 102009024311A DE 102009024311 A1 DE102009024311 A1 DE 102009024311A1
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- masking layer
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- semiconductor material
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 230000000873 masking effect Effects 0.000 claims abstract description 70
- 239000000758 substrate Substances 0.000 claims abstract description 57
- 239000000463 material Substances 0.000 claims abstract description 49
- 238000000151 deposition Methods 0.000 claims abstract description 9
- 239000006251 one-dimensional electron gas Substances 0.000 claims abstract description 9
- 239000002070 nanowire Substances 0.000 claims description 63
- 238000009413 insulation Methods 0.000 claims description 32
- 238000000926 separation method Methods 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims description 5
- 230000003287 optical effect Effects 0.000 claims description 5
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 4
- 238000000609 electron-beam lithography Methods 0.000 claims description 3
- 238000001459 lithography Methods 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 description 8
- 229910002601 GaN Inorganic materials 0.000 description 7
- 239000013078 crystal Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 229910003460 diamond Inorganic materials 0.000 description 4
- 239000010432 diamond Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 229910052733 gallium Inorganic materials 0.000 description 4
- 239000010980 sapphire Substances 0.000 description 4
- 229910052594 sapphire Inorganic materials 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- IOVCWXUNBOPUCH-UHFFFAOYSA-M Nitrite anion Chemical compound [O-]N=O IOVCWXUNBOPUCH-UHFFFAOYSA-M 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
- 238000003486 chemical etching Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 238000010884 ion-beam technique Methods 0.000 description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- -1 AlInN Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- QLJCFNUYUJEXET-UHFFFAOYSA-K aluminum;trinitrite Chemical compound [Al+3].[O-]N=O.[O-]N=O.[O-]N=O QLJCFNUYUJEXET-UHFFFAOYSA-K 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052729 chemical element Inorganic materials 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229930195733 hydrocarbon Natural products 0.000 description 2
- 150000002430 hydrocarbons Chemical class 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 239000000395 magnesium oxide Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 230000005428 wave function Effects 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- BUHVIAUBTBOHAG-FOYDDCNASA-N (2r,3r,4s,5r)-2-[6-[[2-(3,5-dimethoxyphenyl)-2-(2-methylphenyl)ethyl]amino]purin-9-yl]-5-(hydroxymethyl)oxolane-3,4-diol Chemical compound COC1=CC(OC)=CC(C(CNC=2C=3N=CN(C=3N=CN=2)[C@H]2[C@@H]([C@H](O)[C@@H](CO)O2)O)C=2C(=CC=CC=2)C)=C1 BUHVIAUBTBOHAG-FOYDDCNASA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- XBPBJVZJEBBUFI-UHFFFAOYSA-H N(=O)[O-].[In+3].[Al+3].N(=O)[O-].N(=O)[O-].N(=O)[O-].N(=O)[O-].N(=O)[O-] Chemical compound N(=O)[O-].[In+3].[Al+3].N(=O)[O-].N(=O)[O-].N(=O)[O-].N(=O)[O-].N(=O)[O-] XBPBJVZJEBBUFI-UHFFFAOYSA-H 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NHWNVPNZGGXQQV-UHFFFAOYSA-J [Si+4].[O-]N=O.[O-]N=O.[O-]N=O.[O-]N=O Chemical compound [Si+4].[O-]N=O.[O-]N=O.[O-]N=O.[O-]N=O NHWNVPNZGGXQQV-UHFFFAOYSA-J 0.000 description 1
- 230000001464 adherent effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000004038 photonic crystal Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
Abstract
Die Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterbauelementes, in welchem ein eindimensionales Elektronengas ausbildbar ist, welches die folgenden Schritte enthält: Bereitstellen eines Substrates mit einer ersten Oberfläche; Abscheiden einer Maskierungsschicht mit einer ersten Oberfläche und einer zweiten Oberfläche, wobei die zweite Oberfläche der Maskierungsschicht auf der ersten Oberfläche des Substrates angeordnet ist; Einbringen von mindestens einem Graben in die Maskierungsschicht, welcher bis zur ersten Oberfläche des Substrates reicht; Einbringen eines Halbleitermaterials in den mindestens einen Graben und Entfernen der ersten Maskierungsschicht. Weiterhin betrifft die Erfindung ein nach diesem Verfahren hergestelltes Halbleiterbauelement.The invention relates to a method for producing a semiconductor component in which a one-dimensional electron gas can be formed, which includes the following steps: providing a substrate with a first surface; Depositing a masking layer having a first surface and a second surface, the second surface of the masking layer being arranged on the first surface of the substrate; Introducing at least one trench in the masking layer which extends to the first surface of the substrate; Introducing a semiconductor material into the at least one trench and removing the first masking layer. The invention also relates to a semiconductor component produced by this method.
Description
Die Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterbauelementes, in welchem ein eindimensionales Elektronengas ausbildbar ist, welches die folgenden Schritte enthält: Bereitstellen eines Substrates mit einer ersten Oberfläche; Abscheiden einer Maskierungsschicht mit einer ersten Oberfläche und einer zweiten Oberfläche, wobei die zweite Oberfläche der Maskierungsschicht auf der ersten Oberfläche des Substrates angeordnet ist; Einbringen von mindestens einem Graben in die Maskierungsschicht; Einbringen eines Halbleitermaterials in den mindestens einen Graben und Entfernen der ersten Maskierungsschicht. Weiterhin betrifft die Erfindung ein nach diesem Verfahren hergestelltes Halbleiterbauelement.The The invention relates to a method for producing a semiconductor component, in which a one-dimensional electron gas can be formed, which the following steps are included: Providing a Substrate with a first surface; Depositing a masking layer with a first surface and a second surface, wherein the second surface of the masking layer on the first surface of the substrate is arranged; bring at least one trench into the masking layer; bring of a semiconductor material in the at least one trench and removing the first masking layer. Furthermore, the invention relates a manufactured according to this method semiconductor device.
Halbleiterbauelemente der eingangs genannten Art können beispielsweise Feldeffekttransistoren, optische Wellenleiter oder nanoelektromechanische Systeme enthalten.Semiconductor devices of the type mentioned in the introduction, for example, field-effect transistors, optical waveguides or nanoelectromechanical systems.
Aus
Nachteilig an diesem Stand der Technik ist jedoch, dass das Halbleitermaterial aus einer Vielzahl von Kristalliten mit dazwischen liegenden Korngrenzen zusammengesetzt ist. Die Korngrenzen bilden dabei unerwünschte Störstellen, welche den Ladungsträgertransport innerhalb des Halbleitermaterials behindern und/oder Zentren für die Rekombination von Nichtgleichgewichtsladungsträgern bilden. Die Leistungsfähigkeit dieser vorbekannten Halbleiterbauelemente ist daher herabgesetzt.adversely However, in this prior art is that the semiconductor material from a multitude of crystallites with intervening grain boundaries is composed. The grain boundaries form undesirable Defects that the carrier transport hinder within the semiconductor material and / or centers for the recombination of nonequilibrium carriers form. The performance of these prior art semiconductor devices is therefore reduced.
Ausgehend von diesem Stand der Technik liegt der Erfindung daher die Aufgabe zugrunde, niedrigdimensionale Halbleiterstrukturen, insbesondere Nanodrähte, zur Verfügung zu stellen, welche einen geringeren elektrischen Widerstand und/oder eine erhöhte Ladungsträgerbeweglichkeit und/oder eine erhöhte Lebensdauer der Ladungsträger aufweisen.outgoing From this prior art, the invention is therefore the task underlying, low-dimensional semiconductor structures, in particular Nanowires, which provide one lower electrical resistance and / or increased Charge carrier mobility and / or increased Have life of the charge carriers.
Die Aufgabe wird erfindungsgemäß gelöst durch ein Verfahren zur Herstellung eines Halbleiterbauelements, in welchen ein eindimensionales Elektronengas ausbildbar ist, welches die folgenden Schritte enthält: Bereitstellen eines Substrats mit einer ersten Oberfläche; Abscheiden einer Maskierungsschicht mit einer ersten Oberfläche und einer zweiten Oberfläche, wobei die zweite Oberfläche der Maskierungsschicht auf der ersten Oberfläche des Substrats angeordnet ist; Einbringen von mindestens einem Graben in die Maskierungsschicht, welcher bis zur ersten Oberfläche des Substrats reicht; Einbringen eines Halbleitermaterials in den mindestens einen Graben und Entfernen der ersten Maskierungsschicht.The The object is achieved by a method of manufacturing a semiconductor device in which a one-dimensional electron gas can be formed, which is the following steps includes: providing a substrate with a first one Surface; Depositing a masking layer with a first surface and a second surface, wherein the second surface of the masking layer on the first surface of the substrate is disposed; bring at least one trench in the masking layer, which is up to the first surface of the substrate is sufficient; Introducing a Semiconductor material in the at least one trench and removing the first masking layer.
Weiterhin besteht die Lösung der Aufgabe in einem Halbleiterbauelement, welches durch die folgenden Schritte erhältlich ist: Bereitstellen eines Substrats mit einer ersten Oberfläche; Abscheiden einer Maskierungsschicht mit einer ersten Oberfläche und einer zweiten Oberfläche, wobei die zweite Oberfläche der Maskierungsschicht auf der ersten Oberfläche des Substrats angeordnet ist; Einbringen von mindestens einem Graben in die Maskierungsschicht, welcher bis zur ersten Oberfläche des Substrats reicht; Einbringen eines Halbleitermaterials in den mindestens einen Graben und Entfernen der ersten Maskierungsschicht.Farther is the solution of the problem in a semiconductor device, which is available through the following steps: Provide a substrate having a first surface; Separating one Masking layer having a first surface and a second surface, wherein the second surface the masking layer on the first surface of the substrate is arranged; Introducing at least one trench into the masking layer, which extends to the first surface of the substrate; Introducing a semiconductor material into the at least one trench and removing the first masking layer.
Erfindungsgemäß wurde erkannt, dass die Kristallqualität eines niedrigdimensionalen Halbleitermaterials, wie beispielsweise eines Nanodrahtes, gegenüber dem Stand der Technik verbessert werden kann, wenn das Halbleitermaterial im Wesentlichen auf der Oberfläche des Substrats angeordnet und nicht im Substrat vergraben ist. Weiterhin ermöglicht die erfindungsgemäß vorgeschlagene, planare Geometrie des Halbleiterbauelementes die Verwendung üblicher Herstellungsverfahren, um Halbleiterbauelemente mit Nanodrähten zu produzieren. Dadurch erleichtert die planare Geometrie der erfindungsgemäß vorgeschlagenen Halbleiterbauelemente die Kontaktierung der Nanodrähte sowie deren Verbindung untereinander und/oder deren Verbindung mit weiteren, monolithisch auf demselben Substrat integrierten Bauelementen, auch solchen, in welchen sich kein eindimensionales Elektronengas ausbildet.According to the invention was recognized that the crystal quality of a low-dimensional Semiconductor material, such as a nanowire, opposite The prior art can be improved if the semiconductor material arranged substantially on the surface of the substrate and not buried in the substrate. Furthermore, the proposed according to the invention, planar geometry the semiconductor device, the use of conventional manufacturing methods, to produce semiconductor devices with nanowires. This facilitates the planar geometry of the inventively proposed Semiconductor devices contacting the nanowires as well as their connection with each other and / or their connection with further, monolithically integrated on the same substrate components, even those in which there is no one-dimensional electron gas formed.
Völlig überraschend hat sich gezeigt, dass der räumliche Einschluss des Halbleitermaterials in den Gräben der Maskierungsschicht zu einer Verbesserung der Kristallqualität des Halbleitermaterials führt. Das erfindungsgemäß verwendete Substrat kann beispielsweise Silizium, Siliziumkarbid, Saphir, Diamant, Magnesiumoxid oder Zinkoxid enthalten. Die Maskierungsschicht enthält bevorzugt SixNy und/oder SiO2.Quite surprisingly, it has been found that the spatial confinement of the semiconductor material in the trenches of the masking layer leads to an improvement in the crystal quality of the semiconductor material. The substrate used according to the invention may contain, for example, silicon, silicon carbide, sapphire, diamond, magnesium oxide or zinc oxide. The masking layer preferably contains Si x N y and / or SiO 2 .
Das erfindungsgemäß verwendete Halbleitermaterial enthält bevorzugt einen III-V-Halbleiter, beispielsweise InN, GaN, AlInGaN oder auch Elementhalbleiter wie beispielsweise Silizium oder Germanium.The semiconductor material used according to the invention preferably contains a III-V semiconductor, For example, InN, GaN, AlInGaN or elemental semiconductors such as silicon or germanium.
Das Einbringen von mindestens einem Graben in die Maskierungsschicht kann in einer Ausführungsform der Erfindung mittels Elektronenstrahllithographie und/oder UV-Lithographie und/oder einem Nanodruckverfahren erfolgen. Hierzu kann ein Fotolack verwendet werden, welcher in einem nachfolgenden trocken- oder nasschemischen Ätzschritt Teilflächen der Maskierungsschicht vor dem Angriff des Ätzmittels schützt.The Introducing at least one trench into the masking layer may in one embodiment of the invention by means of electron beam lithography and / or UV lithography and / or a nanoprinting process. For this purpose, a photoresist can be used, which in a subsequent dry or wet-chemical etching step partial surfaces protects the masking layer from the attack of the etchant.
In einer Weiterbildung der Erfindung kann vor dem Abscheiden der Maskierungsschicht eine Isolationsschicht mit einer ersten Seite und einer zweiten Seite abgeschieden werden, wobei die zweite Seite der Isolationsschicht auf der ersten Seite des Substrats angeordnet ist und die zweite Seite der Maskierungsschicht auf der ersten Seite der Isolationsschicht angeordnet ist. Bei dieser Ausführungsform der Erfindung ist das Halbleitermaterial bzw. der Nanodraht vom Substrat getrennt, so dass der Einfluss des Substrats auf die Kristallstruktur und/oder die elektrischen Eigenschaften des Halbleitermaterials verringert werden kann. Die Isolationsschicht kann dabei eine Dicke von etwa 100 nm bis etwa 10 μm aufweisen. Die Isolationsschicht kann beispielsweise AlN, AlGaN, AlInN, GaN, Al2O3, SiC oder Diamant enthalten. Bevorzugt ist die Isolationsschicht nominal undotiert, was jedoch nicht ausschließt, dass Fremdatome in der Schicht nachweisbar sein können, beispielsweise als unvermeidbare Verunreinigungen. Die Isolationsschicht kann elektrisch isolierend oder semi-isolierend ausgebildet sein. Die Isolationsschicht kann heteroepitaktisch oder homoepitaktisch auf dem Substrat abgeschieden werden. Auf diese Weise kann eine Oberfläche mit gegenüber der Oberfläche des Substrats verbesserter Qualität zur Aufnahme des Halbleitermaterials bereitgestellt werden. Auf diese Weise kann die Kristallqualität des Halbleitermaterials weiter gesteigert werden.In one development of the invention, an insulating layer having a first side and a second side can be deposited before the deposition of the masking layer, wherein the second side of the insulating layer is arranged on the first side of the substrate and the second side of the masking layer on the first side of the insulating layer is arranged. In this embodiment of the invention, the semiconductor material or the nanowire is separated from the substrate, so that the influence of the substrate on the crystal structure and / or the electrical properties of the semiconductor material can be reduced. The insulating layer may have a thickness of about 100 nm to about 10 microns. The insulating layer may contain, for example, AlN, AlGaN, AlInN, GaN, Al 2 O 3 , SiC or diamond. Preferably, the insulating layer is nominally undoped, but this does not preclude that impurities in the layer may be detectable, for example, as unavoidable impurities. The insulating layer may be formed electrically insulating or semi-insulating. The insulating layer can be deposited heteroepitactically or homoepitaxially on the substrate. In this way, a surface with improved quality with respect to the surface of the substrate for receiving the semiconductor material can be provided. In this way, the crystal quality of the semiconductor material can be further increased.
In einer Weiterbildung der Erfindung kann vorgesehen sein, dass nach dem Entfernen der Maskierungsschicht eine unterhalb des Halbleitermaterials liegende Teilfläche des Substrats und/oder der Isolationsschicht entfernt wird. Auf diese Weise wird das Halbleitermaterial zumindest abschnittsweise freigestellt, so dass der Nanodraht in diesem Abschnitt keinen Kontakt zum Substrat bzw. zur Isolationsschicht mehr aufweist.In a development of the invention can be provided that after removing the masking layer one below the semiconductor material lying partial surface of the substrate and / or the insulating layer Will get removed. In this way, the semiconductor material is at least partially released, leaving the nanowire in this section has no contact with the substrate or the insulating layer more.
In einer anderen Ausführungsform der Erfindung kann vorgesehen sein, dass nach der Entfernung der Maskierungsschicht eine Trennstelle in das zusammenhängende Halbleitermaterial des Nanodrahtes eingebracht wird. Die Trennstelle kann beispielsweise durch Materialabtrag mit einem fokussierten Ionenstrahl eingebracht werden. Insbesondere kann die Trennstelle eine Breite von 10 nm bis etwa 100 nm aufweisen. Die Trennstelle kann beispielsweise dazu verwendet werden, einen isolierenden Bereich zwischen zwei Halbleitermaterialien vorzusehen. Hierzu kann die Trennstelle mit einem dielektrischen Festkörper oder einem dielektrischen Gas aufgefüllt sein.In Another embodiment of the invention may be provided be that after the removal of the masking layer, a separation point in the coherent semiconductor material of the nanowire is introduced. The separation point can, for example, by material removal be introduced with a focused ion beam. Especially For example, the separation site may have a width of 10 nm to about 100 nm. The separation point can be used, for example, a provide insulating area between two semiconductor materials. For this purpose, the separation point with a dielectric solid or a dielectric gas filled.
Sofern zumindest eine Teilfläche des Substrats und/oder der Isolationsschicht unterhalb des Nanodrahtes entfernt und eine Trennstelle in das Halbleitermaterial eingebracht wurde, kann in einer Ausführungsform der Erfindung zumindest ein Teilabschnitt des Nanodrahtes mechanisch bewegbar ausgeführt sein. In einer Weiterbildung der Erfindung kann die aktuelle Position eines solchen Nanodrahtes bestimmt und/oder beeinflusst werden. Dies kann beispielsweise durch eine kapazitive Anregung und/oder eine kapazitive Abstandsmessung erfolgen. Auf diese Weise kann das erfindungsgemäße Halbleiterbauelement eine Nanowaage und/oder ein mechanisch bewegbares Schaltelement enthalten.Provided at least a partial surface of the substrate and / or the insulating layer removed below the nanowire and a point of separation into the semiconductor material may be incorporated in one embodiment of the invention at least a portion of the nanowire mechanically movable be executed. In a further development of the invention determines the current position of such a nanowire and / or to be influenced. This can be done for example by a capacitive Excitation and / or a capacitive distance measurement done. On this way, the semiconductor device according to the invention a nanobay and / or a mechanically movable switching element contain.
Eine Weiterbildung der Erfindung kann vorsehen, nach dem Aufbringen zumindest eines Nanodrahtes in einer ersten Strukturierungsebene weitere Nanodrähte in weiteren Strukturierungsebenen aufzubringen, wobei die einzelnen Strukturierungsebenen durch Isolationsschichten voneinander getrennt sein können. Auf diese Weise können dreidimensionale Strukturen erzeugt werden, wie beispielsweise photonische Kristalle, mehrlagige nanoelektromechanische Systeme oder dreidimensional strukturierte elektronische Bauelemente.A Development of the invention may provide at least after application a nanowire in a first structuring level more nanowires in other structuring levels, with the individual Structuring levels be separated by insulation layers can. In this way, can be three-dimensional Structures are generated, such as photonic crystals, multilayer nanoelectromechanical systems or three-dimensionally structured Electronic Components.
Nachfolgend soll die Erfindung anhand von Figuren ohne Beschränkung des allgemeinen Erfindungsgedankens näher erläutert werden. Dabei zeigen diefollowing the invention is based on figures without limitation of the general inventive idea explained in more detail become. The show
In
der dargestellten Ausführungsform wird auf die Oberfläche
des Substrats
Die
Isolationsschicht
Die
Isolationsschicht
Im
dargestellten Ausführungsbeispiel sollen auf der Oberfläche
der Isolationsschicht
Zur
Erzeugung der Nanodrähte wird eine Maskierungsschicht
In
die Maskierungsschicht
Die
Gräben
Das
Einbringen von mindestens einem Graben
Das Ätzen
der Maskierungsschicht
Das
Halbleitermaterial wird bevorzugt mittels einer Gasphasenabscheidung
in die Gräben
Das
Halbleitermaterial
Im
Anschluss an diesen Verfahrensschritt kann die Maskierungsschicht
Nach
dem Entfernen der Maskierungsschicht
Weiterhin
ist im Querschnitt ein Kontaktelement
Ein
solchermaßen freigestellter Nanodraht
Die
Bewegung des beweglichen Nanodrahtes
In
einer weiteren Ausführungsform der Erfindung kann der Nanodraht
Die
zur Aufnahme von Kontaktelementen
Zwischen
der Stirnseite des ersten Nanodrahtes
Im
nachfolgenden Verfahrensschritt wird der Nanodraht
Ein
solcher Feldeffekttransistor kann beispielsweise als Sensor verwendet
werden, wenn die elektrischen Eigenschaften des Kanals
In gleicher Weise wie vorstehend beschrieben können weitere Isolationsschichten mit weiteren, darauf aufgebrachten Nanodrähten erzeugt werden, um auf diese Weise eine Vielzahl von elektrischen und/oder mechanischen und/oder optischen Bauelementen übereinander herzustellen.In the same way as described above can further Insulation layers with further, applied thereto nanowires be generated in this way a variety of electrical and / or mechanical and / or optical components on top of each other manufacture.
Selbstverständlich ist die Erfindung nicht auf die dargestellten Ausführungsbeispiele beschränkt. Vielmehr können mit dem offenbarten Verfahren zur Herstellung von Nanodrähten eine Vielzahl unterschiedlicher elektromechanischer und/oder elektronischer Bauelemente oder Sensoren hergestellt werden, welche zumindest einen solchen Nanodraht enthalten. Daneben können die Bauelemente selbstverständlich weitere, an sich bekannte Strukturen enthalten. Die nachfolgenden Ansprüche sind daher so zu verstehen, dass ein genanntes Merkmal in zumindest einer Ausführungsform der Erfindung vorhanden ist. Dies schließt die Anwesenheit weiterer Merkmale nicht aus. Sofern die Ansprüche „erste” und „zweite” Merkmale definieren, so dient diese Bezeichnung der Unterscheidung zweier gleichartiger Merkmale, ohne eine Rangfolge festzulegen.Of course the invention is not limited to the illustrated embodiments limited. Rather, can be revealed with the Method of making nanowires a variety different electromechanical and / or electronic components or sensors are made, which at least one such Contain nanowire. In addition, the components can of course contain further structures known per se. The following Claims are therefore to be understood that a named Feature in at least one embodiment of the invention is available. This does not exclude the presence of further features out. If the claims "first" and "second" features define, this designation serves the distinction of two similar characteristics without setting a ranking.
ZITATE ENTHALTEN IN DER BESCHREIBUNGQUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.
Zitierte Nicht-PatentliteraturCited non-patent literature
- - V. Lebedev et. al.: ”Fabrication of one-dimensional trenched GaN nanowires and their interconnections”, Phys. Stat. Sol. (A) 204, No. 10, 3387 (2007) [0003] - V. Lebedev et. al .: "Fabrication of one-dimensional trenched GaN nanowires and their interconnections", Phys. Stat. Sol. (A) 204, no. 10, 3387 (2007) [0003]
Claims (18)
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DE112010001934.7T DE112010001934B4 (en) | 2009-06-05 | 2010-05-17 | Semiconductor component and method for its production |
PCT/EP2010/056690 WO2010139546A1 (en) | 2009-06-05 | 2010-05-17 | Semiconductor structural element and method for the production thereof |
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-
2009
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DE19504117A1 (en) * | 1994-02-08 | 1995-08-10 | Mitsubishi Electric Corp | Prodn. of quantum wire for semiconductor lasers |
US6100104A (en) * | 1997-09-19 | 2000-08-08 | Siemens Aktiengesellschaft | Method for fabricating a plurality of semiconductor bodies |
US20080318003A1 (en) * | 2004-08-31 | 2008-12-25 | Agency For Science, Technology And Research | Nanostructures and Method of Making the Same |
WO2007120493A1 (en) * | 2006-04-04 | 2007-10-25 | Micron Technology, Inc. | Nanofin tunneling transistors |
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CN109782526A (en) * | 2017-11-14 | 2019-05-21 | 爱发科成膜株式会社 | Mask blank and its manufacturing method, half-tone mask and its manufacturing method |
CN109782526B (en) * | 2017-11-14 | 2023-12-01 | 爱发科成膜株式会社 | Mask blank and method for manufacturing the same, halftone mask and method for manufacturing the same |
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