DE102008050057A1 - Multi-chip memory element i.e. dynamic RAM, has chip including group of code pads to impress individual identification i.e. binary code, for concerned chip by external engagement of group of code pads - Google Patents

Abstract

The element (100) has a memory circuit integrated on a set of chips. The circuit has a set of addressable memory cells and control devices for adjusting operating conditions and writing and reading data bits in the cells. One side of each of pads is connected with associated nodes of the circuit and the other side is connected with associated outer contacts of the element for applying electric potentials to the nodes over the contacts. Each chip has a group of code pads (PG3) to impress individual identification i.e. binary code, for the concerned chip by external engagement of the pad group.

Description

The The invention relates to a memory module having a plurality of similar Contains chips, on each of which a RAM memory circuit having a plurality of Memory cells is integrated. The acronym "RAM" (Random Access Memory) stands known for Data storage with the possibility direct read and write access to addressed memory cells. An important but not exclusive field of application of the invention are dynamic RAMs (DRAMs).

at The mass production of memory chips are many similar Memory circuits on defined surface areas of a disk of semiconductor material, the so-called "wafer" integrated. The single ones integrated circuits included in addition to the required circuit components (Memory cell arrays and control circuits for operation) a variety exposed contact surfaces, the so-called "pads" that come with associated nodes of the memory circuit are connected to the necessary for operation supply voltages, clock or timing signals, Create command bits and address bits from the outside and the memory data input and output. A selected one Group of pads is used to receive special "wake-up" commands, by means of which the responsiveness of the chip in question all other external signals are optionally switched on and off can.

To Completion of the integration will be the individual memory circuits on the wafer usually various tests (wafer test) by selecting selected pads over fine Needles of a test machine can be contacted to send by test signals and detecting the response signals any malfunctions in to recognize the memory circuits. Based on the test results, the individual memory circuits, so the individual samples of the Wafers to be classified, e.g. B. by appropriate colored markings on the wafer or by registering in a cartographic Directory. The respective classification can be done so that not only roughly differentiated between faultless and faulty test specimens is, but that with faulty examinees also type and place of respective errors are logged.

In some cases it is possible, detected defects on the wafer repair by z. B. faulty Circuit parts of a test object be replaced by existing redundant parts of the device under test. Such Repairs can be done by destroying and / or wiring existing melting bridges (so-called "fuse elements") z. B. make by laser.

It there are also cases in which a detected during the wafer test and non-repairable error affects the function of only part of the affected memory circuit, such that the circuit is used with limited function could. This applies, for example, if such an error is only a definable one Part of the memory cell field concerns. It is possible one to configure such memory circuit by external intervention so that the subarea containing the error is excluded from access in later operation and only the error-free residual area remains accessible. The memory a so configured "partially good" memory circuit smaller than that of a "good" copy. A partially good memory circuit can thus be classified as such and later be used as a correspondingly "smaller" good memory circuit.

To the described processes The wafer is placed along the boundaries between the memory circuits divided into individual "chips". The usable chips are made according to their Determination further processed. These are the chips in question on a carrier mounted, and then the so-called "bonding" takes place by the individual pads with associated contact pieces of the carrier be electrically connected. Subsequently, the entire arrangement so encapsulated that only the contact pieces mentioned remain accessible as "external contacts" from the outside. The thus created "building blocks" become then re-tested (block test) for possible malfunction find out when cutting the wafer or later (about due to lack of bonding or by the process of encapsulation) may have originated. The blocks identified as faultless can be sold for use be either as individual pieces or to several pieces united in a "memory module".

In memory modules, the storage capacity, ie the number of memory cells, plays an important role. With the same packing density of the cells, the larger the storage capacity, the greater the area of a memory chip and thus also the horizontal spatial extent of a finished module. However, this spatial extent is often limited, especially if several modules are to be placed side by side on a standard module board space. For this reason, building block designs have been conceived for some time which contain two or more chips one above the other, either in the form of two he or more stacked and individually encapsulated individual chip components (so-called "stack" components) or in the form of two or more stacked chips within a common encapsulation (so-called "multiple-die" blocks). As a collective term for both types of stacks, the term "multichip" component is used below. Multi-chip memory devices, which contain m = 2 functioning chips, each having a storage capacity of n bits, have a total capacity of m × n bits (the symbol × is the symbol for multiplication); However, their space requirement is not greater than that of an n-bit single-chip chip.

at Multichip memory devices are the corresponding pads almost all of the different chips are connected in parallel, that means with each one a common external contact of the device. This concerns in particular the pads for the power supply (Supply potentials), the pads for the address bits and the data bits and the pads for all control signals and command bits, except for the pads for the above mentioned "wake-up" commands. Each wake-up command pad each chip is customizable with one assigned external contact bonded. The wake-up commands are z. A chip select bit CS, which depending on its binary value sensitizes or desensitizes the address decoder of the chip, and, in the case of DRAM chips, a clock enable bit CKE, which depends on its binary either the chip receptive to the external Clock signal CLK or instead makes an internally generated clock signal becomes effective (for the self-refresh in non-awakened, so "sleeping" chip).

In a multi-chip memory device whose chips in the above described are bonded, can be on each chip two distinguish disjoint groups of pads: a first pad group, each of which element is parallel to the corresponding elements the other chip is connected to a common external contact, and a second pad group, viz the group of wake-up commando pads whose elements are personalized assigned external contacts are connected. Accordingly, two components can be attached to the module disjoint groups of external contacts A first group comprises the "collecting" external contacts, ie all those where corresponding pads of all chips are connected in parallel are. A second group comprises the "chip-selective" external contacts for the wake-up commands.

at intended use a multichip memory chip, the chips in the above are each bonded only one of the chips awakened by the wake-up commands only to those chip-selective External contacts laid connected to the wakeup command pads of the chip in question are. The block can then over the group of collecting external contacts operated like a single chip chip. An advantage is that the number of external contacts necessary for the useful operation of the block and Thus, the number of necessary external leads relatively low is. Only the number of external leads for the Wake-up commands are multiplied by the number of chips, while the Number of other external leads not higher is than with a single-chip device.

For one Component tests are usually very complicated and expensive test machines used universally for various building blocks can be used. Such test machines, z. B. known under the acronym ATE (Automatic Test Equipment), contain a variety of channels, in which needed Test signals (including the supply voltages) for generates the block and the associated response signals of the block are processed. A test machine is usually designed so that he can test several blocks simultaneously, but independently. The total number of test channels is correspondingly high.

Around Such a test machine to each module to be tested adapt, so-called "base plates" as an intermediate adapter used on one side, here referred to as the top, have a contact pattern that matches the pattern of the external contacts of the one to be tested Block corresponds, so that these "upper" socket contacts when placing of the block with assigned external contacts of the block in touch come. On the opposite Side of the base plate, here referred to as the bottom, are located "lower" socket contacts in a pattern corresponding to the pattern of the one to be used for the test channels of the test machine corresponds. The upper and lower base contacts are hardwired together so that the desired electrical connections between the channels and the device contacts arise when the base plate together with the block on the test machine sitting.

Since the external contacts for the wake-up commands in a multi-chip memory module are multiple available (one wake-contact set for each chip), in such a block, the total number of external contacts to be connected not only for the Nutzbetrieb but also for a test operation is slightly larger than with a single-chip chip. For economic reasons, however, it is desirable to keep the number of test channels used in the test machine per module as small as possible. This is especially true in the case where multiple memory devices are to be tested simultaneously to increase throughput and efficiency. Therefore, it is advantageous to be able to test a multichip memory module via the same set of test channels as a single-chip component whose memory chip resembles the chips of the multichip component. This can be achieved by a special design of the base plate, which also parallel the chip-specific contact sets for the wake-up commands.

A appropriately designed base plate has on its top a Contact pattern corresponding to the pattern of all external contacts of a multichip module matches while the bottom socket contacts the pattern of test channels for testing of a single-chip device. Through a fixed wiring on the base plate is for ensured that also the corresponding chip-selective contacts for the wake-up commands the individual chips are each connected to the same test channel become. In this type of connection, therefore, the chips of the multichip memory module are "fully parallel" connected, so that for one let such block use the same base plate as for one Single-chip module.

Next this advantage offers the "full-parallel" connection inherent also the possibility to operate all chips of the device in parallel. This is advantageous for the Power up and initialization the chips. With a parallel operation of the chips can also be Perform some test sequences with considerable savings in the test time. in the Case of a DRAM device for this purpose z. B. the test sequences for the ACTIVATE process (activation of word lines), the REFRESH process (refresh the memory cells), WRITE operation (execution of a write command) and the PRECHARGE process (preloading various internal data transmission lines).

These Advantages, however, are associated with the problem that the test machine is no longer able to chip through the usual chips Wake-up commands over the connected test channels to wake up selectively. Thus, some test sequences, the require an individual configuration of the chips, not without perform further. These include u. a. all test sequences where memory information for error checking on the data connections the chips are read out. When parallel operation of all chips will it often occur that a misinformation on a data terminal of a chip is covered by error-free information to the appropriate data ports the other chips. Thus, the misinformation remains unrecognized. This is just an example of the problems associated with full-parallel connection of the chips too are expected.

The The object of the invention is a multichip memory module in such a way that with full parallel connection of all chips one different configuration of the chips is possible. This task will by those in the independent claims 1 and 20 described embodiments of the block solved.

According to one In the first aspect, the invention is implemented on a memory device. which contains a plurality m = 2 of individual chips of the same design each of which has a memory circuit integrated therein, which is a plurality addressable memory cells and control means for adjustment of operating conditions and writing and reading data bits on the memory cells and a plurality of pads as contact elements, each of which on the one hand with an associated node of the memory circuit and on the other with an associated external contact of the memory module is connected to electrical potentials the circuit node over the external contacts create and / or feel. The chip-to-chip corresponding elements of a first Group of pads are each with a common external contact a first external contact group connected. A second group of external contacts contains m subgroups, each one with the pads of a second pad group of an individual associated chip is connected to wake-up command bits to turn the responsiveness of the chip in question. Each contains according to the invention Chip in addition a group of codepads, which by external intervention one for the concerned Chip individual identifier is imprinted in the form of a binary code.

at Such a module can be the selection of the chips for the desired individual configuration based on the individual identifier carried out on the codepads. Thus, the Configure chips individually despite full parallel connection.

According to a second aspect of the invention, the invention is implemented on a memory module which contains a plurality of m = 2 individual chips (# 0: 3) of the same design, on each of which a memory circuit is integrated, which a plurality of addressable memory cells and control means for setting len of operating states and for writing and reading data bits to the memory cells and includes a plurality of pads as contact elements, each of which is connected on the one hand to an associated node of the memory circuit and on the other hand with an associated external contact of the memory module to electrical potentials to the circuit node via create and / or feel the external contacts. The chip-to-chip corresponding elements of a first group of pads containing inter alia the data pads are each connected to a common external contact. On each chip there is provided a test circuit which, after performing a memory test, provides a test result bit which has a first logic value in the case of a positive test result and a second logic value in the case of a negative test result. According to the invention, a test configuration circuit is provided on each chip, which can be addressed via a selected subgroup of the first pad group by a binary-coded configuration address in order to activate the test circuit. One of those external contacts connected to data pads is selected as an external test evaluation port, and on each chip the data pad connected to that external contact is controlled by a test result bit-controlled switch with a source of one logic potential and a resistor to a source of the one connected to other logic potential.

at Such a module is made the selection of the chips for one individual configuration, namely for the Setting of the mentioned Switch, based on the respective test result bit. This allows a Test compression in full parallel connection of all chips: the Logic value of a single bit at the external test evaluation port palpable is the blanket test result for the whole building block.

The Invention will be described below with reference to the embodiments attached Drawing figures explained.

1 shows a perspective view of the spatial arrangement of the chips of a multi-chip memory chip according to the invention with chip identifier in the binary number code;

2 illustrates the electrical connections between the memory device after 1 and a test machine;

3 shows details of circuit means on the chips of the memory device 1 for programming and use of the chip identifier;

4 illustrates another variant of the circuit means for programming the chip identifier;

5 shows the scheme of a multi-chip memory chip with a chip identifier in 1-out-of-m binary code;

6 shows details of circuit means for using the chip identifier in the 1-bin binary code;

7 shows an example of a configuration circuit for chip-selective data readout;

8th shows the structure of the decoder of the configuration circuit 7 ;

9 shows an embodiment of the chip-selective data readout switching device;

10 illustrates a first variant for configuring the chips for compressed test mode;

11 shows an example of the circuit implementation of the multiplexer in a configuration circuit 10 ;

12 illustrates a second variant for configuring the chips for compressed test mode;

13 illustrates means for permanently disabling an arbitrary selectable chip in full parallel connection of all the chips;

14 shows the means for rewiring of chip terminals of a 4-chip chip, suitable for all sorts of cases in which up to three arbitrary chips are defective;

15 shows the means for rewiring of chip terminals of a dual-chip package, suitable for the case that any one of the two chips is defective.

In the different figures are circuit parts and signals the same or similar Function denoted by the same alphanumeric symbols (decimal numbers or capital letters). For individual distinction of elements of similar function are the Each of the symbols concerned has different further alphanumeric Added characters; where the character i or j stands for "arbitrary". Binary logic values are in quotation marks as "0" and "1" written.

The in 1 shown multi-chip memory module 100 contains m = 4 stacked similar chips # 0: 3, each with an integrated memory circuit (the colon ":" stands here and below for the word "to"). The chip stack # 0: 3 is on a carrier 110 made of insulating material and is encapsulated with this in a plastic housing (not shown).

The 1 Gives a glimpse of the top of only the top chip # 0 of the stack. Like this chip # 0, all other chips # 1: 3 also have a multiplicity of integrated contact surfaces, the so-called "pads", which are shown as small white squares and via which the access to different circuit points of the respective memory circuit can take place Details are not shown. For example, assume that each chip is a double data rate synchronous DRAM (DDR-SDRAM) with a total memory capacity of 64 Mb on 4 memory banks and an 8-bit data port (8 × configuration).

The pads are associated with contact surfaces of the wearer 110 connected, which are shown as small black squares. Each of these carrier contact surfaces is connected to an individually associated external contact, which is on the underside of the carrier 110 protrudes freely from the housing (in 1 not recognizable). The external contacts are therefore electrically equivalent to the carrier contact surfaces; Therefore, only the term "external contacts" will be used in the following. For the identification of the different external contacts, the same abbreviations are used as for the respectively assigned pads.

The graphic representation in 1 only shows the electrical scheme of the connections between the pads and the external contacts. In practice, each chip may be disposed on an intermediate carrier having contact pieces connected to the pads. These intermediate contacts may be located at the edges of the intermediate carrier and are in turn connected via wires to the outer contacts of the carrier 110 bonded. Alternatively, the intermediate contacts can be arranged on the underside of the intermediate carrier or of the chip substrate, wherein the connection with the pads is produced via feedthroughs (through-connection).

• – ein Pad für das Taktsignal CLK;
• – drei Pads für die Kommandobits RAS, CAS und WE,
• – zwei Pads für Bank-Adressbits BA0:1 (zur selektiven Adressierung einer von 4 Speicherbänken im Chip);
• – dreizehn Pads für Adressbits A0:12 (zur Zeilen- und Spaltenadressierung an der adressierten Speicherbank);
• – zwei Pads VSS und VDD für das negative bzw. positive Potential der Versorgungsspannung;
• – acht Pads DQ0:DQ7 für die Eingabe/Ausgabe von acht Speicherbits im Parallelformat.

In the 1 shown pads are divided into three disjoint groups, which are defined in the drawing by a respective frame. A first pad group PG1 comprises all those pads which are permanently connected in parallel across all chips # 0: 3, that is, in each case connected to a common external contact. These include, for the exemplary 64Mb × 8 memory chip model:

• A pad for the clock signal CLK;
• - three pads for the command bits RAS, CAS and WE,
• Two pads for bank address bits BA0: 1 (for selectively addressing one of 4 memory banks in the chip);
• Thirteen pads for address bits A0: 12 (for row and column addressing on the addressed memory bank);
• Two pads VSS and VDD for the negative or positive potential of the supply voltage;
• - eight pads DQ0: DQ7 for input / output of eight memory bits in parallel format.

The external contacts to which the pads of the first pad group PG1 are connected are in the 1 also defined by a frame and referred to as the first external contact group BG1.

In addition to the pads listed above, the first pad group PG1 may contain a plurality of other pads, which are not shown for reasons of clarity, as well as the respectively associated further external contacts. For this purpose, z. B. a pad for a command for data masking and a pad for a reference potential belong. Pads for VSS and VDD may be present multiple times to facilitate the application of the respective potentials to a plurality of different nodes of the memory circuit. Furthermore, a plurality of reserve contacts (NC) may be present on the carrier to use the same support structure for other chips having a larger variety of pads (eg, higher memory capacity chips requiring a larger number of address bits).

• – ein Pad für das Chip-Selektionssignal CS;
• – ein Pad für das Signal zum Einschalten/Ausschalten des internen Taktoszillators (Clock Enable) CLK.

A second pad group PG2 includes those pads that are addressed in the useful operation of the memory chip "chip-selective" to wake individual chips individually. These include in the example shown:

• A pad for the chip selection signal CS;
• - A pad for the signal to turn on / off the internal clock oscillator (Clock Enable) CLK.

The second pad groups PG2 of the different chips # 0, # 1, # 2, # 3 are connected to individually assigned subgroups WEX0, WEX1, WEX2, WEX3 of a second external contact group BG2 on the carrier 110 connected. Each subgroup WEXi consists of a contact pair, which serves to create the wake-up command bits CSi, CKEi for the relevant chip #i.

A feature according to a first aspect of the invention is the presence of a third pad group PG3, whose elements are referred to herein as "code pads" CP. These codepads do not need to be connected to any external contacts of the device. For example 1 For example, the third pad group contains two code pads CP0 and CP1 to which a two-digit binary code can be impressed to give each of the four chips # 0: 3 an individual identifier. This identifier should allow to address each individual chip individually, even if the chips are fully connected in parallel, including the pads for the wake-up command bits CS and CKE. As mentioned above, such full parallel connection is advantageous when the device 100 be tested by means of a test machine using a reduced number of test channels. The 2 illustrates the scheme of the connections realized between the in 1 shown memory module 100 and a test machine.

In the 2 are the four chips # 0: 3 of the building block 100 drawn as circuit blocks next to each other to more clearly represent all the connections between the pads of the chips and the external contacts. The parallel-connected connecting lines between the pads of the first pad group PG1 and the "common" external contact group BG1 are simplified drawn as wide strands of wire. All external contacts of the module are visible as external contacts on the underside of the module. For use, the device is placed on a suitable board, the external contacts coming into contact with corresponding contacts of the board.

In the lower part of the 2 is schematically a subsection of a test machine 300 shown a first group TG1 of test channels for communication with the contact group BG1 of the memory module 100 contains and a second group TG2 of test channels for sending the wake-up commands CS and CKE. The electrical connections between the test channels and the external contacts of the device 100 be over a base plate 200 manufactured, which has on its upper side a contact pattern corresponding to the device contacts and on its underside a contact pattern for engagement of the test channels. By hard wiring inside the base plate 200 is ensured that the CS contacts CS0: 3 of the block 100 be connected in parallel with a common CS channel of the tester and that the CKE contacts CKE0: 3 of the block 100 be connected in parallel with a common CKE channel of the test machine. As a result, all chips # 0: 3 of the block 100 fully paralleled, and the total amount of test channels used to test the multichip device 100 required is not greater than the total required for testing a single-chip device.

It is common Practice, control commands for configuring and setting various Operating modes of memory modules (in particular of DRAM modules) by entering a specific pattern of control bits, the to selected external connections be created. These "controllable" ports basically belong all connections with the exception of those for fixed potentials (eg the supply potentials VDD, VSS) are provided and those responsible for inputting and outputting the memory data are provided (data or DQ connections). "Controllable" are not just the actual ones Command connections RAS, CAS, WE but also the address ports that are in the write and read operation be used for addressing the memory cells (ie the connections to the Bank, row and column addressing). This can be the bit pattern the command ports specify whether the bits of the address ports are either for cell addressing or as part of control commands should.

The mentioned individual identifier of the individual chips of a multichip module by means of the codepad group PG3 allows, despite the full parallel connection of all the chips in the test mode each chip on the individually addressing said "controllable" ports to selectively establish a desired configuration within the respective chip. The 3 shows an example of an inventive design of the chips to create this possibility.

In the upper part of the 3 is schematically part of the # 0 chip in the 1 and 2 shown block 100 comprising the data pads DQ0: 7, the supply pads VDD, VSS, the pads CS and CKE for the wake-up command (pad group PG2), the pad for the clock signal CLK and a subset PG1a of the pad group PG1. This subgroup comprises the "controllable" pads, in the example shown it is the command pads RAS, CAS, WE and the address pads BA0, BA1, A0: 12. Shown is also the code pad group PG3 with the two code pads CP0 and CP1. A configuration circuit 20 is used to configure a specific operating characteristic of the chip depending on logic potentials of the pads of the subgroup PG1a and the code pad group PG3.

For example 3 the chip # 0 is assigned the identifier "00", characterized in that a potential which represents the logic value "0" is impressed on both code pads CP0, CP1. This can be done according to the 3 be achieved in that both codepads with the VSS external contact of the block 100 be bonded, which receives the zero potential of the external supply voltage both in Nutzbetrieb and in test mode.

The other three chips # 1: 3 are exactly the same as the chip # 0. In the 3 In each case only the code pads of these chips and their connection connections are shown. The chip # 1 is assigned the identifier "01" by bonding the code pad CP0 to the VSS external contact and bonding the code pad CP1 to the VDD external contact, which receives the positive potential of the external supply voltage in both the useful and the test mode Logic value "1" represents. The chip # 2 is assigned the tag "10" by bonding the cod pad CP0 to the VDD outer contact and bonding the cod pad CP1 to the VSS external contact. The chip # 3 is assigned the identifier "11" by bonding both code pads CP0 and CP1 to the VDD external contact.

The programming of the respective chip identifier on the code pads by the bonding described above can be done in stacking the chips before the device 100 is encapsulated. Instead of the described bonding can be used for programming the chip identifier and electrically influenced melt bridges, so-called e-fuses, as shown schematically in FIG 4 is illustrated. The 4 shows the chips # 0: 3 in the same representation as the 3 , with the only difference being that the electrical connections between on the one hand the code pads CP0, CP1 and on the other hand the "0" potential (VSS pad) or the "1" potential (VDD pad) by selectively melting e-fuses within one Fuse Bank FB are made. The melting takes place by applying an overvoltage pulse (burning voltage V _B ) to the assigned pads before encapsulating the module.

In the 4 For example, the E-fuses within bank FB are schematically represented by simple switching paths drawn either as "conductive" (continuous, if not fused) or as "non-conductive" (open when fused).

The configuration circuit 20 in each chip is designed to recognize a codeword which can be applied as a bit pattern to the pads of the subgroup PG1a of all chips and contains a common configuration address for selecting the operating characteristic of all chips to be configured and also a chip address. In the example shown 3 or 4 For example, the bits on the RAS, CAS, WE, BA0, BA1, A0: 10 pads, with the exception of one pad (eg, Pad A8), are used as the "Configuration Address Bits." The excluded pad is used for a separate operation bit OPD, by which the effectiveness of a decoder within the configuration circuit 20 is turned on or off, as described in more detail below. The bits on pads A11 and A12 are used as "chip address bits".

If the memory device described here as an example 100 in the in 2 shown way with a test machine 300 connected, ie with all chips # 0: 3 in full parallel connection, the test machine can be made to send a codeword to all the chips via the controllable connections (pad subgroup PG1a) whose configuration address bits determine which operating feature is to be configured. and its chip address bits determine in which chip in each case a desired configuration of this operating feature is to take place.

The example described above is that the number m of memory chips equals four, so that only two bits suffice for the selective addressing of a single arbitrary chip in the binary number code gene, so two code pads for the chip identifier and two address bits for the chip addressing, as in the 1 to 4 shown. For m = 2 ^{X, it} is generally understood that X codepads and X address bits in the binary number code are required to select a single chip at a time. For some cases, however, it may be desirable to simultaneously select not only a single but an arbitrarily selectable plurality of the m chips. In this case, m address bits and as many code patches are required, coding for a 1-out-of-m code.

The 5 shows in a similar representation as 2 a multi-chip device with m = 4 chips # 0: 3, each of which contains a code pad group PG3 with m = 4 code pads CP0: 3, to which an identifier in a 1-out-of-4 binary code is assigned. In the case shown, the chip # 0 has the identifier 1000, the chip # 1 has the identifier 0100, the chip # 2 has the identifier 0010, and the chip # 3 has the identifier 0001. The 6 shows in a similar representation as the 3 and 4 one of the in 5 shown chips. The bit pattern of the identifier at the code pads CP0: 3 is in 6 not shown, as well as connection connections for impressing the identification bits. This imprint can be done in the same way as above based on the 3 or the 4 described.

In the embodiment of the 5 and 6 m = 4 bits are required for the chip address word. For this purpose, four selected pads of the pad subgroup PG1a can be used, e.g. As the address pads A9: 12, as in 6 shown. The chip address word can either address only a single chip or multiple chips simultaneously, depending on which address bits have the logic value "1". So z. For example, only chip # 2 is addressed if the chip address word is "0010". With the chip address word "0011" the chips # 2 and # 3 are addressed simultaneously.

In the configuration circuit 20 Each chip is compared with the chip address word coded in the manner described above with the chip identifier programmed on the pads CP0: 3. A comparative comparator (in 6 not shown) may be configured to compare each bit of the chip identifier with an individually assigned bit of the chip address and the configuration circuit 20 causes a first configuration to be given to the operating feature to be configured, if one bit of the identifier and the associated bit of the chip address word both have the logic value "1".

Otherwise, the comparator causes the configuration circuit 20 to give the operating feature a second configuration. By any combination of "ones" in the 4-bit chip address word according to the 6 Thus, any chips can be selected at the same time to the configuration circuit 20 in all of these selected chips to configure the associated operating feature in the desired manner.

It There are several operating characteristics, their chip-specific configuration during test operation of a multichip memory module under full Parallel connection of the chips can be advantageous. Some examples are described below.

Chip-selective configuration the data reading

As mentioned above, is a reliable one Error detection on the read-out data only possible if in read mode in each case only a single chip transmits its memory data to the device contacts, while the data transfer is blocked from the other chips.

In order to enable such a chip-selective read operation, the configuration circuit in each chip can be designed so that it is placed in a switching state blocking the data transmission in the read mode when that of the test machine 300 ( 2 ) supplied configuration codeword includes the data blocking targeting configuration address and includes a chip address that matches the identifier of the chip. An exemplary embodiment of a circuit arrangement suitable for this purpose is described in 7 illustrated.

According to the 7 contains the configuration circuit, here with the reference number 20A is called a decoder 21A , a comparator 22A , a logic circuit 23 and a switching device 30A , The pad subgroup PG1a and the code pad group PG3 are each shown as a block only. The two multi-bit connections which supply the configuration address bits from the pad subgroup PG1a and the chip address bits from the cod pad group PG3 to the configuration circuit 20A are each represented as a strand. The connection connections for the stamping of the chip identifier on the code pads are in 7 not shown, you can according to 3 or according to 4 be educated. Also shown are pads for the data lines DQ0: 7.

The decoder 21A sets an output "decoder bit" DCA to a preselected "active" logic value (eg, "1") if and only if the configuration address bits address the configuration of the DQ data transmission and the operation bit OPD is "active" (e.g. "1"). An exemplary embodiment of the decoder is shown in FIG 8th shown.

According to the 8th contains the decoder 21A an equivalent gate 211 which compares the configuration address with a configuration identifier that is permanently programmed in the decoder. This identifier identifies the configuration circuit 20A as the one responsible for the configuration of the DQ data transmission. The configuration identifier is a bit pattern consisting of the same number of bits as the configuration address. It is provided in the example shown by a bit pattern source 212 in the form of a crossbar arrangement, in which the lines of the tag bits are selectively contacted either with a VDD rail whose potential represents the logic value "1", or with a VSS rail whose potential has the logic value "0 "(The contacts are represented by circles filled with black). If the configuration address matches the configuration identifier, the gate returns 211 a "1" at its exit.

The decoder 21A also includes a data flip-flop (D flip-flop) 213 whose data input D receives the operation bit OPD. This bit is set by the test machine to "1", simultaneously with (or shortly before) the creation of the configuration address. The from the gate 211 delivered "1" triggers the Flopflop 213 at its trigger input T, leaving the Q output of the flip-flop 213 supplying the mentioned decoder bit DCA, goes to the active logic value "1".

The above-described operation of the decoder 21A takes place in all chips # 0: 3 in parallel and at the same time. In all chips, so the decoder bit DCA in the configuration circuits 20A is set to "1" and remains in this state until a reset is commanded by the tester, as described below.

The comparator 22A compares the chip address bits with the chip identifier provided on the cod pad group PG3 and provides a "comparator bit" VGA having a preselected "active" logic value (eg, "1") if and only if the chip address bits match that chip bit Address the chip.

In the case of a binary number coding (according to the 2 to 4 ) is the comparator 22A is designed to drive the comparator bit VGA to the active logic value (eg, "1") if and only if all 1d (m) address bits match all 1d (m) bits of the identifier. This can be z. B. reach through 1d (m) equivalent gates (XNOR gates) whose outputs are fed to an AND gate.

In the case of a 1-out-of-m coding (according to the 5 and 6 ) is the comparator 22A is adapted to drive the comparator bit VGA to the active logic value (eg, "1") if and only if the chip address word consisting of m bits has a "1" at the bit position corresponding to the position of the "1" Bit in the identifier matches. This can be z. B. reach through m AND gates whose outputs are fed to an OR gate.

The logic circuit 23 links the decoder bit DCA to the comparator bit VGA to generate at its output a "switch bit" SWA which contains the configuration switch means 30A depending on its logic value in a first or a second switching state sets to that of the switching device 30A assigned operating characteristic to give a first or a second configuration. In the embodiment shown, the logic circuit 23 a NAND gate which receives the decoder bit DCA and the inverted comparator bit VGB and the output of which supplies the switch bit SWA with the logic value "0" at exactly the time when DCA has the logic value "1" and VGA has the logic value "0". That is, the switching bit SWA for selectively blocking the DQ data transmission is equal to "0" in all those chips that are not selected via the chip address.

The switching device 30A for selectively blocking the DQ data transfer is shown schematically as a bank of several on-off switches, the switches being symbolically drawn like mechanical switches located in the way of the internal data lines leading to the data pads DQ0: 7. In reality, the switches are of course formed by semiconductor elements and may be integrated at any suitable location within the chip where, depending on their switching state, they allow or block the transfer of data bits to the data pads. As a switch z. Transmissi Ons gates are used, one with the output of the logic circuit 23A connected control input to turn it on or off depending on the logic value of the switching bit SWA. Such an arrangement is in 9 shown.

According to the 9 For example, each transmission gate includes a PFET (P-channel field effect transistor) and an NFET (N-channel field effect transistor) whose channels are arranged in parallel with each other between the internal data line and the associated DQ pad. The switching bit SWA is applied to the gate terminal of the NFET directly and to the gate terminal of the PFET via an inverter. In the case of SWA = "0", PFET and NFET are both disabled so that DQ data transfer is blocked. In the case of SWA = "1", PFET and NFET are both conductive so that the DQ data transfer works.

If So it is desired is to configure the multichip memory device so that the Data read only takes place on a selected chip, then becomes the test machine initiates the relevant configuration address together with a "1" of the operation bit OPB to send all the chips and the selected chip by means of Chip address too address. Only in this addressed chip then goes the switching bit SWA to "1" and allowed thus the DQ data transmission. In the other (non-selected) chips is the DQ data transfer blocked.

In all other cases, even in normal operation of the memory module, the switching bit SWA remains for the switching devices 30A in all chips to "1", so that the DQ data transmission is nowhere blocked.

Because of the storing effect of the D flip flop 213 in the decoder 21A remains the means of the configuration circuit 20A received configuration. Thus, the pads to which the configuration address and the operation bit OPD have previously been applied may be otherwise used. Thus, in the conventional manner, the test machine can use all pads of group PG1 in order to perform the desired memory tests with all chips in full parallel connection, but the data is only read out on the chip which has been previously selected by the chip address.

A reset of the set configuration can be done simply by re-applying the previously sent configuration address, this time with the logic value "0" of the OPD operation bit. The Q output of the D flip flop 213 in the decoder 21A and thus the decoder bit DCA in the previously addressed chip are hereby reset to Q = "0". A new chip addressing is not required. In the previously unaddressed chips, the decoder bit DCA remains at "0". Thus, the switching bits SWA all chips have the logic value "0", so that the DQ data transfer is blocked in any chip.

In the embodiment according to 7 All chips operate during the test mode in full read operation, with the blocking of the data output to the non-selected chips is done only by blocking the respective data outputs. This means that the power consumption of the entire memory module and thus its self-heating in test reading mode is many times higher than ever expected in later use, where only a single chip operates at full power.

To reduce the power consumption in the test reading mode, instead of the in 7 shown switching device 30A alternative means may be provided to block the DQ data transmission by turning on the power-saving "power-down" state of the respective chips. In this state, the whole chip is kept in a sleep mode in which it drives no data and autonomously ensures the preservation of the storage charge in the memory cells (so-called "self-refresh"). Only a fraction of the active current is needed here. The power-down state can be triggered by means known per se by a corresponding command bit.

In the 7 dashed is an exclusive OR gate (XOR gate) 30A ' drawn, which instead of the switching device 30A may be provided to provide the mentioned power-down command bit PDB. The XOR gate links that from the NAND gate 23 coming switching bit SWA with that of the decoder 21A upcoming decoder bit DCA.

Error detection in the compressed test mode

Another operational feature, the chip-selective configuration of which may be advantageous in test operation of a multi-chip memory device with the chips fully connected in parallel, relates to memory chips designed to perform a compressed test mode. Such chips include a test pattern generator which generates an internally programmed pattern of the data bits to be written for the test and a data comparator that compares the data read with the programmed pattern. This data comparator provides a test result bit which has the logic value "1" meaning "good" if and only if all read data bits match the programmed pattern. Otherwise the test result bit has the other logic value "0" with the meaning "defective".

In such a compressed test mode, e.g. In the mode known by the abbreviation ACTM (Advanced Compression Test Mode), the test result bit is output at a data terminal of the chip selected therefor. For example, with the × 8 chip shown here as an example, it may be any of the data pins DQ0: 7, hereafter referred to as the "evaluation pin." If all the chips of the multichip memory module are fully connected in parallel during the test, thus also with regard to the evaluation connections, a special configuration and configuration of the chips is required, so that the tester can clearly identify whether all evaluation connections have a "good" result, ie a "good" result. 1 "deliver. A first embodiment of this is in 10 illustrated.

The 10 shows the details provided for an ACTM operation of the m = 4 chips # 0: 3 of the memory device 100 , All chips are also identical in this respect. The pad subgroup PG1a, which in the test mode receives the code word for selecting the operating characteristic to be configured (ie the "configuration address"), is shown only as a block. Also shown are the pads of the group PG2 receiving the wake-up command bits CS and CKE, the pad for the clock signal CKL, the data pads DQ0, DQ1, DQ2, DQ3, ..., the supply pads VDD, VSS, and Group PG3 of the code pads. All corresponding pads of chips # 0: 3, with the exception of the code pads, are connected in parallel, as illustrated by the bonding lines on the left and right of the chips. In the example shown, the cod pad group contains two code pads CP0 and CP1, which represent the chip identifier in binary number code, as generally described in US Pat 2 to 4 is shown.

Each chip contains a configuration circuit 20B with a decoder 21B and with a configuration switching device 30B , The decoder 21B is exactly like the one in 8th shown decoder 21A but with a different programming of the configuration identifier in the bit pattern source 212 , The identifier in the decoder 21B identifies the configuration circuit 20B as the one responsible for configuring the ACTM test mode. The decoder 21B drives a decoder bit DCB to an "active" logic value if and only if the configuration address received at the pad subset PG1a addresses the ACTM operation and the operation bit OPB is at "1". The decoder bit DCB becomes the switching device 30B which also receives the chip identifier from the codepad group PG3.

The switching device 30B contains an ACTM configurator 31 which is activated by the active decoder bit DCB at its enable input EN to perform the above-described compressed test and generate the test result bit TRB. This bit is in a latch element 32 (so-called "Fail Latch") locked.

The switching device 30B also contains a switching network 33 whose structure is detailed in 11 is shown. To the operation of this network 33 To understand better, it is in the 10 in a clear equivalent form, comprising an AND gate and a double-branched multiplexer operating like a two-arm selector, and in FIG 10 how one is drawn. The AND gate has two inputs, the first of which is for receiving the latched test result bit TRB from the latch element 32 connected. The one (upper) switching branch of the multiplexer is connected on its "fixed" side to the output of the AND gate, and the other (lower) switching branch is connected on its fixed side to the second input of the AND gate. The switching network 33 has a capability input EN to receive the decoder bit DCB from the decoder 21 , As long as this bit is inactive, ie "0", the multiplexer remains locked.

With active decoder bit DCB (logic value "1") at input EN, the switching network can 33 take one of m = 4 possible switching states, controlled by the m = 4 possible bit pattern of the chip identifier to connect its two switching branches each having a certain pair of m + 1 = 5 terminals. These five ports include four preselected data pads, in the example shown the pads for the data lines DQ0: 3, and a terminal providing a fixed bit with the logic value "1". In each chip takes the switching network 33 if enabled by the decoder bit DCB, a different switching state, depending on the bit pattern of the chip identifier, as in 10 drawn.

In each chip is the switching network 33 the same, only its switching state is determined by the chip identifier. In the embodiment according to 11 contains the network 33 four AND gates GAT0: 3 with five inputs a, b, c, d, e. The output of each gate GATi is connected to an individually assigned data pad DQi of the four data pads DQ0: 3. The a-input of the "lowermost" gate GAT3 is connected to a source of logic potential "1", and the a-inputs of the bottom-up gates GAT2, GAT1, GAT0 are connected to the output of the respective previous gate.

The b inputs of all gates GAT0: 3 receive the test result bit TRB from the latch 32 , These inputs are thus "1" in all chips that have been classified as "good" by the ACTM Configurator.

Of the c input and the d input of each of the four gates GAT0: 3 received the two bits of the chip identifier from the code pads CP0 and CP1, and though in some cases inverted (each illustrated by inverter icon in front of the respective Input), so that only at that gate GATi, whose ordinal number i corresponds to the ordinal number of the chip #i, the c input and the d input are both at "1".

The e inputs of all gates GAT0: 3 receive the decoder bit DCB from the decoder 21E , These inputs are thus all at "1", in all chips # 0: 3, when the ACTM mode has been effectively set via the configuration address and the OPD operation bit.

The circuits 33 of all chips # 0: 3 and the parallel connection of the respectively identically named DQ pads together form a so-called "daisy chain" functioning chain circuit across all chips # 0: 3. The input of this chain is the a-input of the gate GAT3 of the chip # 3 held at fixed logic potential "1". The output of the string is chip # 0 data pad DQ0. This output provides a logic "1" only if the test result bits TRB in all the chips have the logic value "1", that is, if all the chips are "good". Only in this case does one of the gates GAT0: 3 deliver a "1" in all chips, which sets all DQ pads in all chips to "1", including all DQ0 pads. If at least one of the chips is "defective", that is, generates a test result bit TRB = "0", the chain will become within each switching network 33 interrupted, so that all DQ0 pads a "0" appears.

The external DQ0 connection included in the 10 and 11 is drawn as a small black square, so can serve as a "common" evaluation connection in the compressed test of the multichip memory module. Thus, the compressed test can be performed exactly as in a single-chip device.

The 12 shows another embodiment of the configuration circuit for performing the compressed test on the multi-chip device with full parallel connection of all the chips.

The embodiment according to 12 differs from the variant 10 only by details of the configuration switching device, which in 12 with the reference number 30C is designated. The difference is that the output of the latch 32 where the locked test result bit TRB appears, only via an inverter 35 and a driver is connected to the data pad selected for the evaluation port; In the example shown, it is the DQ0 pad, as in the case of 10 , The driver contains an NFET (field effect transistor with N-channel) 36 whose gate connection is via the inverter 35 receives the inverted test result bit TRB from the latch. The source terminal of the NFET 36 is connected to a fixed "0" logic potential (that is, to the more negative supply potential VSS), and the drain terminal is to the DQ0 pad and via a high-impedance pull-up resistor 37 is connected to a fixed "1" logic potential, which in the example shown is more positive than the "0" potential. The pull-up resistor may be formed by a long channel field effect transistor.

When the test machine ( 2 ) selects the ACTM operation, ie sends the configuration address for this mode to the pad subgroup PG1a in all chips, then activates that from the decoder 21B delivered decoder bit DCB the ACTM configurator 31 , When all chips # 0: 3 are "good", the gate terminals of the transistors receive 36 in all chips a "0" potential, so these transistors lock and the DQ0 pads of all chips are driven via the associated pull-up resistors to "1". At the common DQ0 connection of the block, a "1" appears. If at least one of the chips is "defective", the gate terminal of the transistor receives 36 in this chip a "0", so that this transistor conducts and connects its source terminal low resistance to the "0" potential. This low-impedance connection drives all DQ0 pads to "0" even though other chips are "good" and their transistors remain off. At the common DQ0 connection of the block, a "0" appears, whereby the entire block is classified as "defective".

A prerequisite for this operating behavior is that the pull-up resistors 37 are so high impedance that they give a resistance in parallel, which is much higher than the passage Resistance of each of the transistors 36 , This ensures that even a "0" test result in a single chip is sufficient to overwrite any number of "1" test results of other chips. The embodiment according to 12 does not require any individual identification of the chips and in itself does not require any code pads. It is thus much easier to implement than the embodiment according to 10 ,

The above based on the 10 . 11 and 12 described ACTM configurations allow a quick test of a multi-chip memory device with full parallel connection of all chips. However, in such a test can only be recognized if all chips are "good". In the case of a "defective" rated chip, however, it can not be recognized which chips are good and which are defective. In addition, it can not be recognized which part of the cell field of a defective chip is faulty. Such findings are possible, however, if the chips are designed so that they can be selectively read out, as described above on the basis of 7 and 8th has been described.

Permanent shutdown of one defective chip

If when testing a multichip memory chip by chip-selective Reading the memory data has been detected that one of the building blocks is broken, then it would be It's actually a waste, the whole building block as a committee to reject. Would be advantageous it, a possibility to shut down any defective chip in the block permanently and the building block only with existing good chips as a building block reduced storage capacity to operate.

The following is based on the 13 describe how each chip can be formed within a multi-chip device to permanently turn off any chip recognized as defective, with all chips in full parallel connection. As an example, the in the 1 and 2 considered memory chip containing m = 4 chips, each chip has an individual identifier which is programmed by the bit pattern of the code pads in the pad group PG3, z. B. in the basis of 3 or 4 described way.

The 13 shows a configuration circuit 20D which contains a configuration address, the operation bit OPB and a chip address from the test machine ( 2 ) receives via the pad subgroup PG1a and also receives the chip identifier from the pad group PG3. A decoder 21D activates a decoder bit DCD if the configuration address addresses the option "Switch off the chip" and the OPB operation bit has the logic value "1" at the same time. The decoder 21D is exactly like the one in 8th shown decoder 21A but with a different programming of the configuration identifier in the bit pattern source 212 , The identifier in the decoder 21D identifies the configuration circuit 20D as the one responsible for the permanent shutdown chip.

A comparator 22D activates a comparator bit VGD when the chip identifier is hit by the chip address. If both conditions are met, ie DCD and VGD are active, an AND gate is generated 24 a switching bit SWD with the logic value "1", which is a switching device 30D causes the chip to be permanently disconnected from the power supply.

According to the 13 the permanent disconnection of the power supply takes place by intervention in the control loop 40 which is commonly included in each chip to obtain a stabilized internal supply voltage from the external supply voltage applied across the VDD and VSS pads which powers all circuits of the chip. The control loop 40 is in the case shown a series regulator with an NFET 43 , whose channel is a variable resistor between the VDD line and an internal supply line 41 is switched. This line 41 provides the stabilized internal positive supply voltage VINT against the more negative VSS potential, which is via an internal VSS line 42 transmits the common zero potential for all circuits in the chip.

The control loop 40 contains a differential amplifier 45 , which measures the deviation between VINT and a fixed reference potential VREF and provides a control potential to the gate voltage of the NFET 43 and thus to control its impedance in the sense of minimizing the control deviation. Between the VINT line 41 and the VSS line 42 is a smoothing capacitor 44 arranged.

The in the configuration circuit 20D included switching device 30D has a switch 51 on, which is switchable between two switching states. In the first switching state, the in 13 bold, the switch connects 51 the gate of the NFET 43 with the output of the differential amplifier 45 so that the control loop 40 according to its purpose works to stabilize the chip Supply voltage. In the second switching state, the in 13 dashed lines, connects the switch 51 the gate of the NFET 43 with the zero potential VSS, so the NFET 43 is locked and all circuits of the chip are disconnected from the power supply. The internal supply voltage between the VINT line 41 and the VSS line 42 is then 0 volts.

The switching device 30D contains means to the switch 51 to put in the second switching state and keep permanently in this state, after that of the AND gate 24 delivered switching bit SWD has been temporarily switched to the active logic value "1". These means comprise a first inverter 52 whose input receives the switching bit SWD and whose output via a pull-down resistor 53 with the VDD line 42 is connected and via an e-fuse 54 with the VINT line 41 connected is. The signal from the output of the first inverter 52 is via a second inverter 55 and a delay element 56 to the control input changeover switch 51 transfer.

Normally, SWD = "0", and the E-fuse 54 is conductive. Thus, a "1" appears at the output of the first inverter 52 , and the second inverter 55 returns a "0" via the delay element 56 to the control input of the changeover switch 51 is transmitted. This will change the switch 51 held in the bold drawn switching position, in which he the NFET conductive and thus the control loop 40 keeps effective, so the line 41 is held on VINT.

When the switching bit SWD temporarily goes to "1", the output of the first inverter drops 52 to "0", ie to a negative potential compared to VINT, so that the E-fuse is burned and thus non-conductive. At the same time, the output of the second inverter goes 55 to "1". Because of the time delay in the element 56 remains the control input of the switch 51 but still enough time to "0" to the loop 40 and thus the positive potential VINT of the line 41 not switch off before burning the E-fuse. Only after expiry of the delay time does the changeover switch 51 in the dashed line switching state.

After the firing of the E-fuse 54 becomes the output of the first inverter 52 through the pulldown resistor 53 permanently on the potential of the line 42 and thus kept at "0". From now on, as soon as the external supply voltage is applied to the VDD and VSS pads of the chip, the second inverter will be used 55 and the delay element 56 always a "1" to the control input of the switch 51 to permanently switch off the internal supply voltage VINT.

It should be noted that the first inverter 52 must be designed strongly asymmetric, so that the effective pull-down resistor of its output stage is much lower impedance than the internal pull-up resistor (not shown), resulting in appropriate assessment of the resistance 53 can be achieved. This design is such that the inverter 52 in response to the activation of the switching bit SWD delivers a "0" that is sufficiently "strong" to burn the E-fuse 54 is, and that the output of the inverter 52 Also zuküftig remains at "0" remains when the switching bit SWD again inactive (ie to "0"). That is, the strong "0" of the low-impedance pull-down path overwrites the weak "1" of the higher-ohm pull-up path.

Redistribution to a "partially good" multichip memory module

Around a multichip memory device that has one or more defective ones Contains chips, after switching off one or more selected chips as a "partially good" component to be able to use have to certain redistribution of the chips are made. If z. B. in a memory module containing m = 4 chips, at most two chips are detected as defective, the device should be like a Dual-chip device can be used. For this, the internal lines for the wake-up commands CS and CKE of the good chips with those external contacts of the carrier connected to a "real" dual-chip device for this Commands are specified. The following is the usual case suppose that this is the two "first" external wake-up contact pairs WEX0 and WEX1 are. In the case that three chips are broken, the should Chip can be used as a single-chip device. For this have to the internal wake-up command lines of the good chip to the first external wake-up contact pair WEX0 rewired can be.

In a particular embodiment of the invention, each of the chips is designed so that the necessary rewiring can be carried out with full parallel connection of all the chips by addressing a particular configuration circuit in the chips. An embodiment in the case of a 4-chip device will be described below with reference to 14 described.

The 14 shows the formation of a chip #i, which is assembled together with three other similar chips (not shown) to form a 4-chip chip and is suitable for rewiring his in "wake-up line pair" WINi, which comprises the internal lines CSi / int and CKEi / int for the wake-up command bits. The group PG2 of wake-up command pads of each chip #i contains m = 4 subgroups PG2-0: 3 each consisting of a CS pad and a CKE pad. Group BG2 of the external contacts for the wake-up command bits also contains m = 4 subgroups WEX0: 3, each consisting of a CS contact and a CKE contact.

The "first" pad subgroups PG2-0 of all four chips are with the "first" external wake-up contact pair WEX0 which contains the external contacts CS0 / ext, CKE0 / ext where normally the wake-up command bits for the "first" chip # 0 should be created. Corresponding assignments also apply to the others Pad subgroups: in general, the j-th pad subgroups PG2-j of all the chips are included, respectively the j-th Weck contact pair WEXj bonded, which external contacts CSj / ext, CKEj / ext contains, where usually the wakeup command bits for the jth chip #j are created should be.

The chip identifier consists of 2 bits, which are programmed on two code pads CP0, CP1 of the chip group PG3. Each chip #i contains a rewiring configuration circuit 20E with a switching device 30E and a decoder 21E that the basis of the 15 described decoder 21E like. The decoder bit DCF at the output of the decoder 21F is switched to active level (logic value "1") when the rewiring configuration address and a 2-bit chip address corresponding to the ID of the chip #i are applied via the pad subgroup PG1. The chip #i also contains the shutdown configuration circuit 20D according to 13 , in the 14 just drawn as a block.

Furthermore, each chip can additionally with a configuration circuit 20B be provided for compressed test mode, as the basis of the 10 and 11 has been described, and with a configuration circuit 20A for chip selective blocking of the read operation, as determined by the 7 has been described. These additional configuration circuits 20A , B are in 14 not shown separately. All shown configuration circuits are connected to the pads of the group PG1a and to the code pads CP0: 1 to receive a configuration address, the operation bit OPB and a chip address from the tester and to receive the respectively hard coded chip identifier from the codepad.

The decoder 21E is the same as the decoder 21A to 8th and is programmed to set the decoder bit DCE to "1" at its output if and only if the configuration address addresses the "rewiring" feature and the chip address matches the chip #i tag.

The switching device 30E the rewiring configuration circuit 20E contains a multiplexer 70 operating like a 2-pole 4-way switch, and a multiplexer control circuit 80 , The control circuit 80 provides a 2-bit control signal to the control input s of the multiplexer 70 to place the multiplexer in a selected one of four 0: 3 switching states, thereby establishing connections between each of a selected one of the pad subgroups PG2-0: 3 and the internal wake-up pair WINi of the chip.

• – zwei Kennungsbits a0, a1, welche die individuelle Kennung des Chip #i repräsentieren, die an den Codepads CP0, CP1 fest programmiert ist;
• – ein Umverdrahtungs-Aktivierungsbit b, dessen Logikwert durch den Zustand einer Aktivierungs-Fuseschaltung 60-b bestimmt wird;
• – ein Umleit-Adressbit c, dessen Logikwert durch den Zustand einer Adress-Fuseschaltung 60-c bestimmt wird und das angibt, auf welches der beiden externen Weck-Kontaktpaare WEX0, WEX1 interne Weck-Leitungspaar WINi des Chip #i verdrahtet werden soll.

The multiplexer control circuit 80 is a logic circuit with four inputs to receive four bits:

• Two tag bits a0, a1, which represent the unique identifier of the chip #i, which is hard-coded on the code pads CP0, CP1;
• A rewire enable bit b, its logic value by the state of an enable footswitch 60-b is determined;
• A bypass address bit c, its logic value by the state of an address latch circuit 60-c is determined and indicating which of the two external wake-up contact pairs WEX0, WEX1 internal wake-up pair WINi chip #i is to be wired.

• X = ignorieren

The logic function of the control circuit 80 and the associated wiring states are listed in Table 1 below: Table 1 b c a1 a0 s State of 70 WINi on: 0 X 0 0 00 0 WEX0 0 X 0 1 01 1 WEX1 0 X 1 0 10 2 WEX2 0 X 1 1 11 3 WEX3 1 0 X X 00 0 WEX0 1 1 X X 01 1 WEX1

• X = ignore

The foot circuits 60-b . 60-c are equal to each other. In the 14 is for reasons of space only the Fuseschaltung 60-b drawn in detail. Accordingly, each Fuseschaltung contains an e-fuse 64 one side of which is the parallel connection of a resistor 65 and a switch 66 is connected to the VDD pad to which the more positive potential of the supply voltage is applied representing the logic value "1". The other side of the E-fuse 64 is connected to the VSS pad to which the more negative potential of the supply voltage is applied representing the logic value "0". The state of the switch 66 is controlled by a binary control signal. With inactive control signal (logic value "0") is the switch 66 open (non-conductive), and with active control signal (logic value "1"), the switch is closed, so that it the resistance 65 bridged. The connection point between the E-fuse 64 and the resistance 65 is the signal output of the footer circuit.

In the original state of each Fuseschaltung is the relevant E-Fuse 64 not fired, so conductive. Even after the supply voltage has been applied to the supply pads VDD, VSS, the E-fuse remains 64 conductive, as long as the control signal of the switch 66 remains at "0" and thus the switch 66 kept open. The resistance 65 acts in this case as a dropping resistor, which is the current flowing out of the supply pads via the E-fuse 64 flows so far that it is insufficient to melt the E-fuse. The signal output of the footer circuit is received via the conductive E-fuse 64 the VSS potential, so it is at "0".

When the control signal of the switch 66 goes to "1", the switch is 66 closed, so that the series resistor 65 the E-fuse is bridged. This causes the E-fuse 64 burned, so becomes non-conductive. As a result, the signal output of the Fuseschaltung goes to "1", because he has the resistance 65 the VDD potential is received.

In the original state of the memory module, therefore, all fuse circuits deliver a "0". Thus, the b input is the control circuit 80 to "0", so that the bit c is ignored and the control signal s in each chip corresponds to the relevant chip identifier a0, a1. In this case, take the multiplexers 70 in each chip #i, that state in which the internal wake-up line pair WINi is connected to the originally assigned wake-up contact pair WEXi (see Table 1). So there is no rewiring.

When the #i chip is to be rewired, the configuration circuit becomes 20E of the chip in question. For this purpose, the rewiring configuration address, the operation bit OPB and the chip address for the chip #i are sent via the pad subgroup PG1a, so that the decoder bit DCE goes from "0" to "1". This bit, which is the switch 66 in the footfall 60-b controls, closes this switch, leaving the e-fuse 64 is burned. This causes the signal output of this fuse and thus the b input of the multiplexer control circuit 80 staying at "1". This causes the control circuit 80 In the future, the tag bits a1, a2 are ignored and instead the bypass address bit c is taken into account (see Table 1).

Simultaneously with the described activation of the configuration circuit 20E the redirect address bit c is sent via the pad subgroup PG1a. The active decoder bit DCE switches a transmission gate 90 a, whereby the bypass address bit to the Fuseschaltung 60-c is placed. With the logic value "0" of the bypass address bit, the E-fuse in the fuse circuit remains unburned (ie conducting), so that this fuse circuit continues to be a "0" to the c input of the control circuit 80 sets. Does the bypass address bit have the Logic value "1", then the E-fuse of the fuse circuit 60-c burned, so this Fuseschaltung a permanent "1" to the c input of the control circuit 80 supplies. As a result of this operation, the bit c is on the control circuit 80 permanently programmed to the bypass address, so that the internal wake-up line pair WINi of the relevant chip #i in the future wired to that of the two external wake-up contact pairs WEX0, WEX1, which has been determined by the bypass address.

Of course, the decision as to whether individual chips of the module should be rewired and the decision as to which external wake-up contact pair (WEX0 or WEX1) the rewiring should take depends on the result of the previous function tests of the individual chips. These tests can be the z. B. with the help of in 7 shown configuration circuit 20A be performed individually on each chip. From the test result, it also depends on which chips with the help of in 13 shown configuration circuit 20D should be switched off permanently. For a 4-chip device, the following generally applies:
If one or two chips are defective, the device can be used as a dual-chip device. For this, it must be ensured that two good chips are connected to the first two external wake-up contact pairs WEX0 and WEX1. All other chips must be turned off, whether they are good or broken. Of course, if a good chip belongs to the group of the first two chips # 0: 1, a rewiring of this chip is not necessary. If the first two chips # 0 and # 1 are good, there is no need for rewiring.

If three chips are broken, the device can be used as a single-chip device be used. For this, it must be ensured that the good chip is connected to the first external wake-up contact pair WEX0. All other (ie all defective) chips must be switched off. If the good chip is the first chip # 0, it does not require any rewiring.

Above, the means for permanent rewiring of individual chips were explained using the example of a 4-chip module. Of course, the described principle is generally applicable to memory devices containing any number m = 2 ^x of devices, where x is a natural number = 1. For x> 2, the number of subgroups in the pad group PG2 and the switching variations of the multiplexer 70 expand accordingly, and accordingly also the bit depths of the Umleit address and the chip identifier, the number of "address Fuseschaltungen" 60-c and the number of c inputs of the multiplexer control circuit 80 , So z. Example, in an 8-chip device, an 8-way multiplexer, two bits for the Umleit address, two "address Fuseschaltungen" for the diversion programming and accordingly two c inputs to the control circuit 80 necessary to provide the possibility, in the case of a necessary rewiring the multiplexer in any of the four "first" switching positions 0: 3 of the total of 8 switching positions 0: 7 set.

Generally, with rewiring configuration circuits of the invention, it is possible to configure a "half-good" (2 ^x ) chip device as a "good" (2 ^xy ) chip device, where y <x. The number of subgroups in the pad group PG2 and the number of possible switching positions of the multiplexer must be equal to 2 ^x . The number of bits of the chip identifier must be equal to x. The number of bypass address bits, the address strobe circuits and the c inputs of the multiplexer control circuit correspond to the necessary address space for the desired number of different bypass addresses.

In the case of a dual-chip memory module, that is, when m = 2 and x = 1, there is no need either a Umleit-address or an address Fuseschaltung to configure the chip as a "good" single-chip device, if one the two chips is broken. This will be explained below on the basis of 15 explained.

The 15 shows the formation of a dual-chip device with two chips # 0, # 1, which are designed specifically for use in such a device. Each chip #i contains means for rewiring the respective internal "wake-up line pair" WINi. The group PG2 of wake-up command pads of each chip #i contains two subgroups PG2-0: 1, each consisting of a CS pad and a CKE pad. The first pad subgroup PG2-0 is bonded to a first external wake-up contact pair WEX0, and the second pad subset PG2-1 is bonded to a second external wake-up contact pair WEX1. Any additional external wake-up contact pairs will remain free ("non-connected"). Each #i chip also contains the shutdown configuration circuit 20D according to 13 and may also include the configuration means 20A and 20B according to the 8th and 10 contain. All these facilities are in the 15 just drawn as blocks.

The chip identifier consists of a single bit which is programmed on the (single) code pad CP of the chip group PG3. Each chip #i contains a rewiring configuration circuit 20F with a switching device 30F and a decoder 21F , The decoder 21F A decoder bit DCF turns to active level (logic "1") when it receives the rewiring configuration address and the operation bit. This will cause the e-fuse 64 the activation footswitch 60 in the switching device 30F burned, so that the b input of a multiplexer control circuit 81 goes from "0" to "1" and is always "1" for the future as soon as the chip's power is turned on.

This control circuit 81 receives at its a input the chip identifier from the cod pad CP and supplies a control bit s to a multiplexer 71 functioning as two-pole switch with two switch positions 0 and 1. In its 0 position, the multiplexer connects 71 in each chip #i, the internal wake-up line pair WINi of the relevant chip via the pad subgroup PG2-0 with the "first" external wake-up contact pair WEX0. In its 1-position the multiplexer connects 71 the internal wake-up line pair WINi via the pad subgroup PG2-1 with the "second" external wake-up contact pair WEX1.

• *) Chip ist abgeschaltet

Table 2 lists the four possible quality states of the memory module and the respectively required wiring of the internal wake-up line pair WIN: Table 2 Chip # 0 Chip # 1 Verdraht. Chip # 0 Verdraht. Chip # 1 first case: Good Good WIN0-WEX0 WIN1-WEX1 second case: Good malfunction WIN0-WEX0 none *) third case: malfunction Good none *) WIN1-WEX0 fourth case: malfunction malfunction Discard block

• *) Chip is switched off

In order to realize the three different wiring patterns for a good device (first case) or for a half good device (second and third case), the control circuit is 81 in each chip #i is formed as an exclusive-OR gate (XOR gate). The truth table of this gate 81 and each of the set wiring state are listed in Table 3. Table 3 a b s State of 71 WINi on: 0 0 0 0 WEX0 0 1 1 1 WEX1 1 0 1 1 WEX1 1 1 0 0 WEX0

The original state of the memory module is the E-fuse 64 in each chip #i unburned (conductive), so that b = "0". Thus, the switching state of the multiplexer corresponds 71 in each chip, the logic value of the tag bit of the particular device. That is, chip # 0 is wired to WEX0 and chip # 1 is wired to WEX1. If both chips are good (first case), this original state is preserved and the device can be used as a dual-chip device.

If the chip # 0 is good and the chip # 1 is defective (second case), can the device used without further manipulation as a single-chip device after the broken chip # 1 has been turned off.

Only if the chip # 0 is defective (and switched off) and the chip # 1 is good, so only in the third case, it requires a further manipulation, namely a rewiring of the good chip # 1 of WEX1 on WEX0 to the device as a single chip To use block. For this, the rewiring configuration address and the operation bit OPB are sent, so that the decoder bit DCF of the chip # 1 goes to "1". The decoder 21F Chip # 0 remains ineffective because this chip is turned off as a defective chip. The E-fuse 64 the chip # 1 is burned, and the b input of the XOR gate 81 is brought from "0" to "1". According to Table 3 above, the desired rewiring of the chip # 1 on WEX0 thus takes place.

All embodiments of the invention, as described above by way of examples with reference to 1 to 15 have a common advantage: it is possible to give the individual chips individual configurations without having to individually select them via the wake-up commands CS and CKE. Thus, individual configurations can be implemented with full parallel connection of all chips. The module can therefore be used for setting all configurations on the base plate 200 according to the 2 remain in order to carry out the various functional tests and, if desired, individual shutdowns and rewirings by means of a test machine.

It it should be mentioned that various elements of the circuits shown in the figures too Their operation must have more leads, for reasons of clarity the drawings are not shown. These include supply lines to power the relevant elements and, if the elements clock-controlled work, leads for applying the clock signals.

20

configuration circuits

21

decoder

22

comparator

23

AND gate

24

AND gate

30

Configuration switching devices

31

ACTM configurator

32

latch

33

Switching network

35

inverter

36

transistor switch

40

loop

41

internal supply line

42

Zero potential line

43

regulator transistor

44

smoothing capacitor

45

Setpoint / actual value comparator

51

switch

52

inverter

53

resistance

54

E-Fuse

55

inverter

56

delay element

60

Fuse circuits

64

E-Fuse

65

dropping resistor

66

switch

70

multiplexer

71

multiplexer

80

Multiplexer control circuit

81

Multiplexer control circuit

90

transmission gate

100

memory chip

110

Block-support

200

plinth

211

equivalent gate

212

Bitmusterquelle

213

D flip-flop

300

test Machine

BG

External contact groups

CP

Codepads

PG

Pad groups

TG

Test channel groups

WEX

external Wake-contact pairs

WIN

internal Wake-line pairs

Claims (20)

Memory module ( 100 ) having a plurality m = 2 of individual chips (# 0: 3) of the same type, each having integrated therein a memory circuit including a plurality of addressable memory cells and control means for setting operating conditions and writing and reading data bits to the memory cells, and A plurality of pads as contact elements, each of which is connected on the one hand to an associated node of the memory circuit and on the other hand with an associated external contact of the memory module to apply electrical potentials to the circuit node via the external contacts and / or to feel, the chip-to-chip each other corresponding elements of a first group of the pads (PG1) are each connected to a common external contact of a first external contact group (BG1); and wherein a second group (BG2) of the external contacts comprises m subgroups (BG-0: 3) each of which is connected to the pads of a second pad group (PG2) of an individually assigned chip to turn on wake-up command bits (CS, CKE) the responsiveness of the relevant chip to create; and wherein each chip additionally comprises a group of code pads (PG3), which are impressed by external intervention an individual identifier for the respective chip in the form of a binary code. Memory device according to claim 1, wherein the code pads (PG3) each chip in one for the chip in question unique pattern with those external contacts the first external contact group (BG1) are connected, which for applying the two supply potentials (VDD, VSS) to the memory chip. Memory chip according to claim 1, wherein on each chip a set of p = 1 configuration circuits ( 20 ) is provided, which are individually addressable via a selected subgroup (PG1a) of the first pad group (PG1) by a binary coded configuration address and a binary coded chip address and each configure an operating feature determined by the configuration address in a manner desired for that chip, if the chip is selected by matching preselected bits of the chip address with preselected bits of the chip identifier. Memory module according to claim 3, the Identification each chip is encoded in binary code and where a chip is selected if all the bits encoded in the binary number code Chip address with all bits match the identifier of the chip. Memory module according to claim 3, the Identification of each chip is encoded in a 1-out-of-m binary code, the one first logic value ("1") on only one for the respective chip has specific bit position, and where a Chip is selected when a chip address consisting of m bits and the identifier the first logic value ("1") at the same bit position to have. A memory device according to claim 3, wherein the set of configuration circuits on each chip comprises a data block configuration circuit ( 20A ) which, in response to its addressing, blocks transmission of stored data to the data pads (DQ) contained in the first pad group (PG1) when the chip in question is selected. A memory device according to claim 3, wherein said data blocking configuration circuit ( 20A ) a switching device ( 30A ) which interrupts the signal paths between the memory cells and the data pads (DQ) of the selected chip. A memory device according to claim 3, wherein said data blocking configuration circuit ( 20A ) a switching device ( 30A ' ), which places the selected chip in the power-down state. A memory device according to claim 3, wherein the set of configuration circuits on each chip comprises a shutdown configuration circuit ( 20D ) which permanently turns off the power supply of the selected chip in response to its addressing. A memory device according to claim 9, wherein the shutdown configuration circuit ( 20D ) a switching device ( 30D ) with an E-fuse ( 54 ), which burns in response to the addressing of this configuration circuit, thereby disrupting the internal power supply circuit ( 40 ) of the selected chip is deactivated. A memory device according to claim 10, wherein the internal power supply circuit of each chip comprises a control circuit ( 40 ) with a control transistor ( 43 ) for stabilizing the internal supply voltage (VINT) and wherein the switching device ( 30D ) the shutdown configuration circuit ( 20D ) contains: - a switch ( 51 ), which in a first state, the control terminal of the control transistor ( 43 ) with the output of a setpoint / actual value comparator ( 45 ) of the control loop ( 40 ) and in a second state of the control terminal of the control transistor to a blocking potential (VSS) connects; A control circuit ( 52 . 53 . 55 . 56 ), the switch ( 51 ) holds in the first state, if the E-fuse is not burned out, and which delays the switch after the E-fuse has blown ( 54 ) into the second state. Memory chip according to one of Claims 9 to 11, wherein the second pad group (PG2) of each chip (#i) consists of m equally powerful disjunctive subgroups (PG2-0, PG2-1, ...), each of which is assigned an individual associated with m external wake-up contact groups (WEX0, WEX1, ...) forming m subgroups of the second external contact group (BG2), and wherein the set of configuration circuits on each chip (#i) is a rewiring configuration circuit ( 20E ; 20F ) with a rewiring switching device ( 30E ; 30F ), which is switchable between different switching states, to connect the internal wake-up command lines (WINi) of the relevant chip (#i) with different external wake-up contact groups (WEX0, WEX1, ...). Memory chip according to claim 12, wherein the rewiring switching device ( 30E ; 30F ) if addressing of the rewiring configuration circuit ( 20E ; 20F ) is maintained in a normal state, in which it connects the internal wake-up command lines (WINi) of the relevant chip (#i) with that subgroup (PG2-i) of the second pad group (PG2) that corresponds to the external wake associated with that chip Contact group (WEXi) is connected, and wherein the rewiring configuration circuit ( 20E ; 20F ) in response to its addressing, the switching device ( 30E ) in a permanent rewiring state, in which it connects the internal wake-up command lines (WINi) of the relevant chip (#i) with another subgroup of the second pad group (PG2). Memory device according to claim 13, wherein the rewiring configuration circuit ( 20E ) each chip (#i), in response to its addressing, associates the tag of the chip with a redirect address received at pads of the first pad group (PG1) to match the internal wake-up command lines (WINi) of that chip with one through the Divert address specific subgroup of the second pad group (PG2) to connect. A memory device according to claim 13, wherein m = 2, and wherein the rewiring configuration circuit (15) 20E ) each chip (#i), in response to its addressing, connects the internal wake-up command lines (WINi) of the respective chip to that subgroup of the second pad group (PG2) which is connected to the external wake-up contact group associated with the other chip. Memory module according to one of claims 13 to 15, wherein the rewiring switching device ( 30E ; 30F ) one or more e-fuses ( 64 ), which melt according to the respective desired switching state of the switching device to fix the switching state. A memory device according to claim 12, wherein a ranking for the external wake-up contact groups (WEX0, WEX1, ...) is predetermined, and wherein a subset of the chips consisting of k <m chips is configured to switch off their power supply, and wherein the switching states the rewiring switching devices ( 30E ; 30F ) of the remaining m - k chips are set such that the internal wake-up command lines (WIN) are connected to those external wake-up contact groups (WEX) which occupy the first m-k slots in the predetermined ranking order. Memory chip according to claim 1, wherein on each chip a configuration circuit ( 20B ) is provided, which is addressable via a selected subgroup (PG1a) of the first pad group (PG1) by a binary-coded configuration address to a switching network determined by the configuration address ( 33 ) in a condition determined by the chip identifier. A memory device according to claim 18, wherein a test circuit ( 31 ) which, after performing a memory test, provides a test result bit (TRB) having a first logic value ("1") in the case of a positive test result and a second logic value ("0") in the case of a negative test result, and wherein Switching network ( 33 ) each chip has m + 1 signal terminals, the first of which is connected to a source of the first logic potential ("1") and the remainder of which are connected to m data pads (DQ0: 3) belonging to the first pad group (PG1), and wherein Switching network ( 33 ) Each chip is switchable between m different states depending on the identifier of the relevant chip in order to establish a signal path between a pair of signal terminals selected by the identifier, such that a signal path chain is formed over the data pads of the m chips (# 0: 3) resulting from the first signal terminal of the switching network one of the chips (# 3) to that of the m data pads (DQ0), which is designed to output the test result, and wherein each signal path in each chip via a controllable switching element (GAT) leads, which blocks the signal path when the test result bit (TRB) of the chip in question has the second logic value ("0"). Memory module ( 100 ) having a plurality m = 2 of individual chips (# 0: 3) of the same type, each having integrated therein a memory circuit including a plurality of addressable memory cells and control means for setting operating conditions and writing and reading data bits to the memory cells, and A plurality of pads as contact elements, each of which is connected on the one hand to an associated node of the memory circuit and on the other hand with an associated external contact of the memory module to apply electrical potentials to the circuit node via the external contacts and / or to feel, the chip-to-chip each other corresponding elements of a first group of the pads (PG1), which among other things contains the data pads (DQ), are each connected to a common external contact; and wherein on each chip a test circuit ( 31 ) which, after performing a memory test, provides a test result bit (TRB) having a first logic value ("1") in the case of a positive test result and having a second logic value ("0") in case of a negative test result Chip a test configuration circuit ( 20C ) which is addressable via a selected subgroup (PG1a) of the first pad group (PG1) by a binary-coded configuration address in order to connect the test circuit ( 31 and one of those external contacts connected to data pads is selected as the external test evaluation terminal, and on each chip the data pad (DQ0) connected to this external contact is connected via a switch controlled by the test result bit (TRB) (FIG. 36 ) with a source of one logic potential ("0") and a resistor ( 37 ) is connected to a source of the other logic potential ("1").