DE102007061161A1 - Electronic packing structure e.g. electronic three dimensional package, for manufacturing e.g. micro electronic, signal contact formed on side of structure connected with contact to form canal between contact and inner switching circuit - Google Patents
Electronic packing structure e.g. electronic three dimensional package, for manufacturing e.g. micro electronic, signal contact formed on side of structure connected with contact to form canal between contact and inner switching circuit Download PDFInfo
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- DE102007061161A1 DE102007061161A1 DE102007061161A DE102007061161A DE102007061161A1 DE 102007061161 A1 DE102007061161 A1 DE 102007061161A1 DE 102007061161 A DE102007061161 A DE 102007061161A DE 102007061161 A DE102007061161 A DE 102007061161A DE 102007061161 A1 DE102007061161 A1 DE 102007061161A1
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Abstract
Description
Gebiet der ErfindungField of the invention
Die vorliegende Erfindung bezieht sich auf elektronische Packungsstrukturen und insbesondere auf eine Packungseinheit mit einem leitenden Trägersubstrat, das ein Multi-Chip-Stapeln über Signalkontakte auf beiden Seiten der Einheit erreichen kann.The The present invention relates to electronic packaging structures and in particular to a packaging unit with a conductive carrier substrate, this is a multi-chip stacking via signal contacts on both Can reach pages of unity.
Hintergrund der ErfindungBackground of the invention
Da die Nachfrage nach Funktionen und Anwendungen von elektronischen Produkten schnell wächst, ist die Packungstechnologie fortlaufend zu einer extremhohen Dichte, Miniaturgröße und vom Einzel-Chip zum Multi-Chip, vom 2D- zum 3D-Maßstab fortgeschritten. Somit gibt es zur Zeit fortschrittliche Packungsstrukturen (d. h. extrem hochdichte Packungsformen), wie Waferebenenpackungen, 3D-Packungen, Multi-Chip-Packungen und System-in-Packungen (SIP), die sich von konventionellen Packungen in ihrer Gestaltung, Herstellung und Materialverwendung merklich unterscheiden. Die idealste Situation ist, alle Schaltkreise in einem einzigen Siliciumchip unterzubringen, was System-on-Chip (SoC) ist. Ein Integrieren von immer komplizierter werdenden Schaltkreisfunktionen in einen einzigen Chip wird jedoch die Chipgröße vergrößern, das Chipherstellungsverfahren komplizieren und verursacht verringerte Ausbeute und erhöhte Kosten, neben technischen Schwierigkeiten. Daher ist, verglichen mit der SoC-Technologie, SIP, das kleine Größe, hohe Frequenz, hohe Geschwindigkeit, einen kurzen Herstellungszyklus und geringe Kosten hervorhebt, das bevorzugte Verfahren, um die obengenannten Ziele zu verwirklichen und Chips mit verschiedenen Schaltkreisfunktionen zu integrieren. Beruhend auf den Anforderungen verschiedener Anwendungen kann eine Packung in ein planares Multi-Chip-Modul (MCM), eine Multi-Chip-Packung (MCP) und eine gestapelte 3D-Packungsstruktur mit Multichips eingestuft werden, die Packungsgebiete wirksamer verringern und weiterhin dünne Chips verwenden, um die Dicke und das Gewicht der gestapelten Packung herabzusetzen. Daher kann die Anforderung an geringes Gewicht, Dünnheit und Kleinheit für fortschrittliche Packungsstrukturen bewerkstelligt werden.There the demand for functions and applications of electronic As products grow rapidly, the packaging technology is ongoing to an extremely high density, miniature size and from single chip to multi-chip, from 2D to 3D scale advanced. Thus, there are currently advanced packaging structures (i.e., extremely high density packages), such as wafer-level packages, 3D packages, Multi-chip packages and system-in-packages (SIP) that differ from conventional packages in their design, manufacture and use of materials noticeably different. The most ideal situation is all circuits in a single silicon chip, giving system-on-chip (SoC) is. Integrating increasingly complex circuit functions however, the chip size becomes a single chip enlarge, complicate the chip manufacturing process and causes reduced yield and increased costs, besides technical difficulties. Therefore, compared to SoC technology, SIP, the small size, high frequency, high speed, highlights a short manufacturing cycle and low cost, that preferred methods to achieve the above objectives and integrate chips with different circuit functions. Based on the requirements of different applications, one can Package in a planar multi-chip module (MCM), a multi-chip package (MCP) and classified a stacked 3D packing structure with multichips will reduce the packing areas more effectively and continue to thin Use chips to increase the thickness and weight of the stacked pack decrease. Therefore, the requirement for light weight, thinness and smallness for advanced packaging structures.
Eine
Ausgangsverzweigung-Waferebenenpackungsstruktur und ein Verfahren
dafür werden in dem
Eine
elektronische Packungsstruktur, die eine profilierte Metallschicht
verwendet, um eine I/O-Ausgangsverzweigungscharakteristik zu erzielen,
wird in
Folglich, da eine System-on-Chip-Packung(SoC) eine Tendenz wird, um mehrere Chips, wie Mikroelektroniken, Hochfrequenzkommunikations- oder Betätigungssensoren herzustellen, und die Technologiekosten der gestapelten Packung zu verringern und Packungsvolumenverkleinerung zu erzielen, ist es ein dringendes Erfordernis, eine Struktur mit hoher Dichte, hoch zuverlässiger Struktur und elektrischen Eigenschaften zu entwickeln und eine Packungsstruktur mit mehreren mikroelektronischen Elementen zu gestalten und zusammenzusetzen, die eine flexible Anpassung je nach geforderten Anwendungsfunktionen machen kann.Consequently, since a system-on-chip (SoC) package tends to produce multiple chips, such as microelectronics, radio-frequency communication or actuation sensors, and others It is an urgent need to develop a high-density structure, highly reliable structure and electrical properties, and to design and assemble a packaging structure with multiple microelectronic elements that provide flexible adaptation as required, to reduce stacked package technology costs and to achieve package volume reduction Application functions.
Zusammenfassung der ErfindungSummary of the invention
Angesichts der obigen Nachteile beim Stand der Technik und einer zunehmenden Tendenz für eine System-on-Chip(SoC)-Packung, mehrere Chips herzustellen, wie Mikroelektroniken, Hochfrequenzkommunikations- oder Betätigungssensoren, werden die Vorteile der vorliegenden Erfindung wie folgt gezeigt: Die vorliegende Erfindung schlägt eine elektronische Packungsstruktur vor, und es ist der Vorteil, eine Waferebenenpackungseinheit mit mehreren mikroelektronischen Elementen zu liefern, wobei die leitenden Bahnprofile auf den oberen und unteren Oberflächen eine einzige oder mehrere verkleinerte gestapelte Packungsstrukturen flexibel erfüllen können, je nach den Anforderungen der Anwendungsumstände und -funktionen, um die Signalübertragungswege und -zeit zu verringern und dadurch die Arbeitsfrequenz und Leistungsfähigkeit des gestapelten Packungsmoduls zu steigern.in view of the above disadvantages of the prior art and an increasing Tendency for a system-on-chip (SoC) package to make multiple chips such as microelectronics, radio frequency communication or actuation sensors, the advantages of the present invention are shown as follows: The present invention proposes an electronic packaging structure before, and it is the advantage of a wafer-level packing unit with to provide multiple microelectronic elements, wherein the conductive Track profiles on the upper and lower surfaces one single or multiple miniaturized stacked packing structures can meet flexibly, depending on the requirements the application circumstances and functions to the signal transmission paths and time and thereby the working frequency and performance of the stacked packing module.
Es ist ein anderer Vorteil der Erfindung, eine elektronische Packungsstruktur zu liefern, wobei alle Packungseinheiten auf den Wafern oder Substraten seriell hergestellt werden und um so die Herstellungskosten von jeder individuellen Packungseinheit zu verringern.It Another advantage of the invention is an electronic packaging structure to deliver, with all packaging units on the wafers or substrates serial and so the manufacturing cost of each individual Packing unit to reduce.
Es ist noch ein anderer Vorteil der Erfindung, eine elektronische Packungsstruktur zu liefern, wobei das leitende Trägersubstrat verwendet wird, um eine Signalübertragung für die elektronischen Elemente zu liefern, und das Trägersubstrat als Erdanschluss für die angeordneten elektronischen Elemente verwendet werden kann, um elektrische Charakteristiken der elektronischen Elemente zu steigern. Das Trägersubstrat ist weiterhin auch ein guter Wärmeleiter, der durch die elektronischen Elemente erzeugte und in der Packung gespeicherte Wärmeenergie wirksam zur Außenseite der Packung entlang des Substrats abgeben und so die Zuverlässigkeit der Packungsstruktur steigern kann.It Yet another advantage of the invention is an electronic packaging structure with the conductive carrier substrate used becomes a signal transmission for the electronic To provide elements, and the carrier substrate as a ground terminal for the arranged electronic elements can be used to increase electrical characteristics of the electronic elements. The carrier substrate is also a good conductor of heat, that generated by the electronic elements and in the pack stored heat energy effective to the outside the packaging along the substrate and so the reliability can increase the packing structure.
Um die oben diskutierten Vorteile zu erreichen, umfasst die vorgeschlagene elektronische Packungsstruktur der Erfindung ein einziges oder mehrere leitende Trägersubstrate. Ein einziges oder mehrere elektronische Elemente sind über den Oberflächen der obigen Trägersubstrate verteilt, und die Gebiete der Trägersubstrate können größer als, gleich wie oder kleiner als die der elektronischen Elemente sein. Eine einzige oder mehrere Füllzonen sind um die obigen elektronischen Elemente gebildet, es bestehen ein einziges oder mehrere Durchgangslöcher innerhalb der Füllzonen, und leitende Materialien sind in die Durchgangslöcher oder Lochwände gefüllt, um eine Signalverbindung zwischen den Oberflächen der Füllzonen und den obigen Substraten zu bilden. Ein einziger oder mehrere Signalkontakte sind auf wenigstens einer Seite der elektronischen Packungsstruktur gebildet, und die Oberflächengebiete der Signalkontakte können größer als, gleich wie oder kleiner als die der elektronischen Elemente sein. Ein einziger oder mehrere Signalkanäle sind auf wenigstens einer Seite der obigen elektronischen Packungsstruktur gebildet und jeweils mit den obigen Signalkontakten verbunden, um Kanäle zwischen den Signalkanälen und den inneren Schaltkreisen der obigen elektronischen Elemente zu bilden. Mehrere Fixierungsstrukturen (UBM: under bump metallization-Unterstoßmetallisation) sind auf den obigen Signalkontakten gebildet.Around To achieve the advantages discussed above, includes the proposed electronic packaging structure of the invention, one or more conductive carrier substrates. A single or multiple electronic Elements are above the surfaces of the above Carrier substrates distributed, and the areas of the carrier substrates can be greater than, equal to or less be that of the electronic elements. One or more Filling zones are formed around the above electronic elements, There is a single or multiple through holes within the filling zones, and conductive materials are in the through holes or perforated walls filled to a signal connection between the surfaces of the filling zones and the form the above substrates. A single or multiple signal contacts are formed on at least one side of the electronic packaging structure, and the surface areas of the signal contacts can greater than, equal to, or less than that of be electronic elements. A single or multiple signal channels are on at least one side of the above electronic packaging structure formed and respectively connected to the above signal contacts to Channels between the signal channels and the inner ones Form circuits of the above electronic elements. Several Fixation Structures (UBM: under bump metallization-impact metallization) are formed on the above signal contacts.
Die oben genannten Merkmale und Vorteile werden von der folgenden genauen Beschreibung einer bevorzugten Ausführungsform zusammen mit den begleitenden Zeichnungen klar.The Above features and benefits are detailed by the following Description of a preferred embodiment together clear with the accompanying drawings.
Kurze Beschreibung der ZeichnungenBrief description of the drawings
Die bevorzugten Ausführungsformen der Erfindung werden in der folgenden Beschreibung und den begleitenden Zeichnungen weiter erläutert, und wobei:The preferred embodiments of the invention are described in the following description and the accompanying drawings, and wherein:
Genaue Beschreibung einer bevorzugten AusführungsformExact description of one preferred embodiment
In der vorliegenden Erfindung wird eine elektronische Packungseinheit offenbart. Die Erfindung liefert insbesondere eine Packungseinheit mit einem leitenden Trägersubstrat, das Multi-Chip-Stapeln über die Signalkontakte auf beiden Seiten der Einheit erreichen kann. Die Ausführungsformen der Erfindung werden unten genau beschrieben, und die bevorzugte Ausführungsform dient nur zur Erläuterung und nicht zu Zwecken der Beschränkung der Erfindung.In The present invention is an electronic packaging unit disclosed. The invention provides in particular a packing unit with a conductive carrier substrate, the multi-chip stacking over can reach the signal contacts on both sides of the unit. The embodiments of the invention will be detailed below described, and the preferred embodiment is only for explanation and not for the purpose of limitation the invention.
Das
obige Trägersubstrat
Ein
mögliches Herstellungsverfahren für die obige
erste Packungseinheit
Die
erste Deckschicht
Es ist klar von dem Vorangehenden, dass spezifische Ausführungsformen der Erfindung hier zu Zwecken der Darstellung beschrieben worden sind, dass aber verschiedene Änderungen und Abwandlungen von Fachleuten gemacht werden können, ohne von dem Sinn und Umfang der Erfindung abzuweichen. Die Erfindung ist daher nicht beschränkt, außer durch die angehängten Ansprüche.It is clear from the foregoing that specific embodiments the invention has been described herein for purposes of illustration but that are different changes and modifications can be made by professionals without the sense and scope of the invention. The invention is therefore not limited, except by the attached Claims.
ZITATE ENTHALTEN IN DER BESCHREIBUNGQUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- - TW 5431255 [0003] - TW 5431255 [0003]
- - US 6288905 [0004] - US 6288905 [0004]
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE102007061161A DE102007061161A1 (en) | 2007-12-17 | 2007-12-17 | Electronic packing structure e.g. electronic three dimensional package, for manufacturing e.g. micro electronic, signal contact formed on side of structure connected with contact to form canal between contact and inner switching circuit |
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Application Number | Priority Date | Filing Date | Title |
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DE102007061161A DE102007061161A1 (en) | 2007-12-17 | 2007-12-17 | Electronic packing structure e.g. electronic three dimensional package, for manufacturing e.g. micro electronic, signal contact formed on side of structure connected with contact to form canal between contact and inner switching circuit |
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DE102007061161A1 true DE102007061161A1 (en) | 2009-06-18 |
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Cited By (1)
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CN107200300A (en) * | 2017-04-26 | 2017-09-26 | 歌尔股份有限公司 | MEMS and encapsulating structure preparation method |
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DE19744297A1 (en) * | 1997-10-07 | 1999-04-15 | Fraunhofer Ges Forschung | Stackable, encapsulated electronic component |
US6288905B1 (en) | 1999-04-15 | 2001-09-11 | Amerasia International Technology Inc. | Contact module, as for a smart card, and method for making same |
DE102004033057A1 (en) * | 2003-12-03 | 2005-06-30 | Advanced Chip Engineering Technology Inc. | Fan-out type wafer level package structure and method for making the same |
-
2007
- 2007-12-17 DE DE102007061161A patent/DE102007061161A1/en not_active Ceased
Patent Citations (3)
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DE19744297A1 (en) * | 1997-10-07 | 1999-04-15 | Fraunhofer Ges Forschung | Stackable, encapsulated electronic component |
US6288905B1 (en) | 1999-04-15 | 2001-09-11 | Amerasia International Technology Inc. | Contact module, as for a smart card, and method for making same |
DE102004033057A1 (en) * | 2003-12-03 | 2005-06-30 | Advanced Chip Engineering Technology Inc. | Fan-out type wafer level package structure and method for making the same |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN107200300A (en) * | 2017-04-26 | 2017-09-26 | 歌尔股份有限公司 | MEMS and encapsulating structure preparation method |
CN107200300B (en) * | 2017-04-26 | 2023-07-21 | 潍坊歌尔微电子有限公司 | MEMS device and packaging structure manufacturing method |
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