DE102007019795A1 - Chip module and method for manufacturing this chip module - Google Patents
Chip module and method for manufacturing this chip module Download PDFInfo
- Publication number
- DE102007019795A1 DE102007019795A1 DE102007019795A DE102007019795A DE102007019795A1 DE 102007019795 A1 DE102007019795 A1 DE 102007019795A1 DE 102007019795 A DE102007019795 A DE 102007019795A DE 102007019795 A DE102007019795 A DE 102007019795A DE 102007019795 A1 DE102007019795 A1 DE 102007019795A1
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- chip
- contact
- wire
- stabilizing material
- chip module
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Chipmodul mit: - einem Trägersubstrat, das eine Chipoberfläche und eine der Chipoberfläche gegenüberliegende Kontaktfeldoberfläche aufweist, - einem Chip, der auf der Chipoberfläche des Trägers befestigt ist und mindestens einen Chipanschlusskontakt aufweist, - zumindest einem Kontaktfeld, das an der Kontaktfeldoberfläche ausgebildet ist, - zumindest einem Durchgang, der im Trägersubstrat zwischen der Kontaktfeldoberfläche und der Chipoberfläche ausgebildet ist und - einem Stabilisierungsmaterial, das in den Durchgang eingebracht ist.A chip module comprising: a carrier substrate having a chip surface and a contact pad surface facing the chip surface, a chip mounted on the chip surface of the carrier and having at least one chip pad, at least one contact pad formed on the pad field surface, at least a passage formed in the support substrate between the contact pad surface and the chip surface; and a stabilizing material introduced into the passage.
Description
Die Erfindung betrifft ein Chipmodul mit auf einem Trägersubstrat aufgebrachten Kontaktfeldern, wobei Chipanschlusskontakte mit den Kontaktfeldern elektrisch leitend verbunden sind.The The invention relates to a chip module with on a carrier substrate applied contact fields, wherein chip connection contacts with the Contact fields are electrically connected.
Chipkarten haben einen breiten Anwendungsbereich, beispielsweise zur Datenspeicherung, zur Zugangskontrolle oder im Zahlungsverkehr.smart cards have a wide range of applications, for example for data storage, for Access control or in payment transactions.
Zwischen einem Schreib-Lese-Gerät und einer Chipkarte erfolgt beispielsweise ein kontaktbasierter Datentransfer. Hierfür sind auf einer Seite der Chipkarte zum Kontaktieren durch das Schreib-Lese-Gerätes Kontaktfelder ausgebildet. Alternativ kann ein Datentransfer auch kontaktlos erfolgen. Hierbei wird ein elektromagnetisches Feld zur Übertragung der Informationen moduliert und in einer im Chipkartenkörper integrierten Empfangsspule empfangen. Eine Kombination aus diesen beiden Datentransfermöglichkeiten besitzt die so genannte Dual-Interface-Karte, die sowohl über Möglichkeiten zum kontaktbasierten, als auch zum kontaktlosen Übertragen von Informationen verfügt.Between a read-write device and a chip card, for example, a contact-based Data transfer. Therefor are contact fields on one side of the chip card for contacting by the read / write device educated. Alternatively, a data transfer can also be made contactless. in this connection becomes an electromagnetic field for transmitting the information modulated and in a receiving coil integrated in the chip card body receive. A combination of these two data transfer options owns the so-called dual-interface card, both over Ways to contact-based, as well as for the contactless transmission of information features.
Zur Herstellung einer Chipkarte, wird üblicherweise ein Chipmodul in eine Kavität eines Chipkartenkörpers eingebracht und beispielsweise durch ein Klebemittel mit dem Kartenkörper der Chipkarte verbunden. Das Chipmodul umfasst dabei üblicherweise ein Trägersubstrat, auf welchem Kontaktfelder aufgebracht sind, wobei die Vorderseiten der Kontaktfelder nach der Montage des Chipmoduls in den Chipkartenkörper noch zugänglich sind, und einen Halbleiterchip, der auf einer der Kontaktfelder gegenüberliegenden Seite des Trägersubstrats auf das Trägersubstrat aufgebracht ist. Die Trägersubstratseite, auf der die Kontaktfelder aufgebracht sind, wird im Folgenden als Kontaktfeldoberfläche, die Trägersubstratseite, auf der der Chip befestigt ist, als Chipoberfläche bezeichnet. In das Trägersubstrat sind Durchgänge, auch als Durchkontaktierungen oder Bondlöcher bezeichnet, eingebracht, die es ermöglichen, die Chipanschlusskontakte des Halbleiterchips mit den Kontaktfeldern auf der Kontaktfeldoberfläche mittels Bonddrähten, hier fortlaufend als Draht benannt, elektrisch zu verbinden.to Production of a chip card usually becomes a chip module in a cavity a chip card body introduced and, for example, by an adhesive with the card body of Chip card connected. The chip module usually includes a carrier substrate, on which contact pads are applied, the front sides the contact fields after mounting the chip module in the chip card body yet are accessible, and a semiconductor chip located on one of the contact pads Side of the carrier substrate on the carrier substrate is applied. The carrier substrate side, on the contact pads are applied, is hereinafter referred to as the contact pad surface, the Carrier substrate side, on which the chip is mounted, referred to as the chip surface. In the carrier substrate are passages, also referred to as vias or bonding holes introduced, that make it possible for the Chip connection contacts of the semiconductor chip with the contact fields on the contact field surface by means of Bonding wires, here continuously called wire, electrically connect.
Zum Schutz des Chipmoduls beziehungsweise des Chips mit seinen empfindlichen Bonddrähten erfolgt eine Verkapselung um den Chip und den Drähte.To the Protection of the chip module or the chip with its sensitive bonding wires An encapsulation takes place around the chip and the wires.
Die Kontaktfelder sind meist als metallisierte Schichten ausgebildet sind, so ist beispielsweise auf eine Kupferschicht, eine Nickelschicht gefolgt von einer Goldschicht mittels galvanischen Verfahrens aufgebracht.The Contact fields are usually formed as metallized layers are, for example, on a copper layer, a nickel layer followed by a gold layer applied by electroplating.
Eine übliche Belastung im täglichen Gebrauch ist das Biegen der Chipkarte zum Beispiel beim Tragen der Chipkarte in einer Geldbörse in einer Hosentasche bzw. im Versand durch Sortieranlagen. Dabei kommt es zu dreidimensionalen Relativbewegungen des Trägersubstrates, welches im Folgenden als mechanischer Stress bezeichnet wird.A usual burden in the daily Use is the bending of the chip card, for example, while wearing the Chip card in a purse in a trouser pocket or in shipping through sorting systems. there it comes to three-dimensional relative movements of the carrier substrate, which is referred to below as mechanical stress.
Durch die Verkapselung ist der Draht fest in der Verkapselungsmasse verankert. Im Durchgang ist die Verkapselungsmasse beabstandet vom Kontaktfeld, bzw. konstruktionsbedingt unzureichend haftend mit dem Kontaktfeld verbunden. Durch den me chanischen Stress kommt es zu einer Delamination zwischen Trägersubstrat und Verkapselungsmasse. Durch die damit verbundene Vergrößerung des Abstandes der Verkapselungsmasse zum Kontaktfeld sowie der festen Verankerung des Drahtes in der Verkapselungsmasse wirken Zugkräfte auf den Draht im Durchgang. Eine übliche Drahtbondverbindung zwischen Draht und Kontaktfeld kann den Zugkräften des Drahtes im Extremfall nicht ausreichend standhalten. Der daraus resultierende Drahtabriss hat zumeist einen elektrischen Ausfall des Chips zur Folge.By the encapsulation, the wire is firmly anchored in the encapsulant. In the passage, the encapsulant is spaced from the contact pad, or structurally inadequate adhesion with the contact field connected. The mechanical stress causes delamination carrier substrate and encapsulant. Due to the associated enlargement of the Distance of the encapsulant to the contact field and the fixed Anchoring of the wire in the encapsulant have tensile forces the wire in the passage. A usual Wire bond between wire and contact pad can withstand the tensile forces of Wire in extreme cases can not withstand sufficient. The result The resulting wire tear usually has an electrical failure of the chip.
Es ist daher ein Chipmodul mit einem Trägersubstrat, das eine Chipoberfläche und eine der Chipoberfläche gegenüberliegende Kontaktfeldoberfläche aufweist, einem Chip, der auf der Chipoberfläche des Trägers befestigt ist und mindestens einen Chipanschlusskontakt aufweist, zumindest einem Kontaktfeld, das an der Kontaktfeldoberfläche ausgebildet ist, zumindest ein Durchgang, der im Trägersubstrat zwischen der Kontaktfelderoberfläche und der Chipoberfläche ausgebildet ist, ein Stabilisierungsmaterial, das in den Durchgang eingebracht ist und mindestens einer elektrischen Verbindung zwischen dem zumindest einen Chipanschlusskontakt und dem zumindest einen Kontaktfeld, vorgesehen. Dabei weist die elektrische Verbindung zumindest teilweise einen Draht auf, der durch das Stabilisierungsmaterial gegenüber dem Kontaktfeld fixiert ist.It is therefore a chip module with a carrier substrate having a chip surface and one of the chip surface opposing Contact Field surface comprising a chip mounted on the chip surface of the carrier and at least having a chip connection contact, at least one contact field, that at the contact field surface is formed, at least one passage in the carrier substrate between the contact field surface and the chip surface is formed, a stabilizing material in the passage is introduced and at least one electrical connection between the at least one chip connection contact and the at least one contact field, intended. In this case, the electrical connection has at least partially a wire formed by the stabilizing material opposite the Contact field is fixed.
Weiterhin ist ein Verfahren zum Herstellen einer elektrischen Verbindung zwischen einem Chip und einem Kontaktfeld vorgesehen, bei dem der Chip auf einer Chipoberfläche eines Trägersubstrates aufgesetzt wird, in einem Durchgang, der im Trägersubstrat zwischen der Chipoberfläche und der der Chipoberfläche gegenüberliegenden Kontaktfeldoberfläche angeordnet wird und ein Stabilisierungsmaterial eingebracht wird. Hier bei wird zur elektrischen Verbindungsherstellung zumindest teilweise eine Drahtverbindung ausgebildet, die an einem Chipanschlusskontakt des Chips angesetzt und in den Durchgang eingebracht wird und der Draht der Drahtverbindung durch das Stabilisierungsmaterial fixiert wird.Farther is a method of establishing an electrical connection between a chip and a contact pad provided, wherein the chip on a chip surface a carrier substrate is placed in a passage in the carrier substrate between the chip surface and the chip surface opposite Contact Field surface is placed and a stabilizing material is introduced. Here at at least partially for electrical connection production a wire connection formed on a chip connection contact the chips are placed and introduced into the passage and the Wire the wire connection is fixed by the stabilizing material.
Nachfolgend wird die Erfindung anhand von Ausführungsbeispielen mit Bezugnahme auf die Zeichnungen erläutert, wobei die Figuren gleiche oder gleich wirkende Bestandteile jeweils mit den gleichen Bezugszeichen gekennzeichnet sind. Die dargestellten Elemente sind nicht als maßstabsgerecht anzusehen, vielmehr können einzelne Elemente zum besseren Verständnis übertrieben groß beziehungsweise übertrieben vereinfacht dargestellt sein. Es zeigen:The invention is based on Embodiments explained with reference to the drawings, wherein the figures the same or equivalent components are each marked with the same reference numerals. The illustrated elements are not to be considered as true to scale, but individual elements may be exaggerated in size or exaggerated simplified for better understanding. Show it:
In
Der
im Trägersubstrat
Das
Stabilisierungsmaterial
Durch
das Aufbringen des Chips
Zum
Schutz des Chips
Bruchmechanisch robuste Chipkartenmodule erhält man beispielsweise, wenn die Verkapselung in der so genannten Transfer-Molding-Technologie ausgeführt wird.Mechanical fracture robust chip card modules receives For example, if the encapsulation is carried out in the so-called transfer molding technology.
Die Öffnung der
Durchgänge
In
Das Material des Drahtes ist beispielsweise Gold.The Material of the wire is, for example, gold.
Die
Kontaktierung des Drahtes
Unter
Bildung eines Bogens ist der Draht
Wesentlicher
Unterschied zu
Zur
Ausbildung der Kontaktfelder auf der Kontaktfeldoberfläche
Zur
Stabilisierung des Drahtes
Durch
die Verwendung von Lotmaterial ist eine Lötverbindung und damit auch
eine intermetallische Verbindung zwischen Stabilisierungsmaterial
Da
der Draht
Alternativ
können
die Kontaktfelder
In
Eine
elektrisch leitende Verbindung vom Chipanschlusskontakt
In
Wenn
das Chipmodul als eine Chipkarte mit Dual-Interface vorgesehen ist,
benötigt
man neben den dem ISO-Standard folgenden Kontaktfeldern
Ferner
umfassen diese Dual-Interface Chipkartenmodul eine Leiterbahnanordnung,
um die Empfangsspule zu kontaktieren. Auch diese Leiterbahnanordnung
umfassen Anschlusskontakte, die über
Drähte
Eine
weitere Ausgestaltung der Durchkontaktierung ist in
Zur
Verbindung der Kontaktfelder
Die
gezeigte Drahtbondverbindung
Es
sei darauf hingewiesen, dass die in den
- 11
- Trägersubstratcarrier substrate
- 22
- Chipoberflächechip surface
- 33
- KontaktfeldoberflächeContact Field surface
- 44
- Kontaktfeld, MetallisierungContact box metallization
- 4a4a
- Kupferbeschichtungcopper coating
- 4b4b
- Nickelbeschichtungnickel coating
- 4c4c
- Goldbeschichtunggold coating
- 55
- Drahtwire
- 66
- Durchgangpassage
- 77
- Stabilisierungsmaterialstabilizing material
- 8a8a
- Drahtbondverbindung, Wedge-KontaktWire bond, Wedge Contact
- 8b8b
- Drahtbondverbindung, Nailhead-KontaktWire bond, Nailhead contact
- 99
- ChipanschlusskontaktChip connection contact
- 1010
- Verkapselungencapsulation
- 1111
- Chipchip
- 1212
- KleberGlue
Claims (25)
Priority Applications (2)
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DE102007019795A DE102007019795B4 (en) | 2007-04-26 | 2007-04-26 | Chip module and method for manufacturing this chip module |
JP2008115763A JP2008277825A (en) | 2007-04-26 | 2008-04-25 | Chip module, and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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DE102007019795A DE102007019795B4 (en) | 2007-04-26 | 2007-04-26 | Chip module and method for manufacturing this chip module |
Publications (2)
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DE102007019795A1 true DE102007019795A1 (en) | 2008-11-06 |
DE102007019795B4 DE102007019795B4 (en) | 2012-10-04 |
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DE102007019795A Expired - Fee Related DE102007019795B4 (en) | 2007-04-26 | 2007-04-26 | Chip module and method for manufacturing this chip module |
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JP (1) | JP2008277825A (en) |
DE (1) | DE102007019795B4 (en) |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2047474A (en) * | 1978-10-19 | 1980-11-26 | Cii Honeywell Bull | A strip carrying devices for processing electrical signals, and a method of producing the strip |
US4701236A (en) * | 1985-04-12 | 1987-10-20 | U.S. Philips Corporation | Method of manufacturing an electronic identification card |
JPS63284831A (en) * | 1987-05-18 | 1988-11-22 | Nippon Inter Electronics Corp | Manufacture of hybrid integrated circuit |
JPH088284A (en) * | 1994-06-20 | 1996-01-12 | Hitachi Ltd | Wire bonding structure and its reinforcement method |
US5992725A (en) * | 1996-03-13 | 1999-11-30 | Kabushiki Kaisha Toshiba | Apparatus and method for producing electronic elements |
US6288904B1 (en) * | 1996-09-30 | 2001-09-11 | Infineon Technologies Ag | Chip module, in particular for implantation in a smart card body |
DE102004032605A1 (en) * | 2004-07-05 | 2006-01-26 | Infineon Technologies Ag | Semiconductor component with a semiconductor chip and electrical connection elements to a conductor structure |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS624331A (en) * | 1985-06-30 | 1987-01-10 | Toshiba Corp | Wire bonding method |
FR2624651B1 (en) * | 1987-12-14 | 1991-09-06 | Sgs Thomson Microelectronics | METHOD FOR SETTING UP AN ELECTRONIC COMPONENT AND ITS ELECTRICAL CONNECTIONS ON A SUPPORT AND PRODUCT THUS OBTAINED |
JPH03192744A (en) * | 1989-12-21 | 1991-08-22 | Matsushita Electric Works Ltd | Structure for mounting semiconductor device |
FR2733848B1 (en) * | 1995-05-05 | 1997-05-30 | Schlumberger Ind Sa | COATING PROCESS FOR AN ELECTRONIC COMPONENT AND DEVICE FOR IMPLEMENTING THE SAID PROCESS |
JP3176542B2 (en) * | 1995-10-25 | 2001-06-18 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
US5965867A (en) * | 1996-07-19 | 1999-10-12 | Gieseke & Devrient Gmbh | Data medium incorporating integrated circuits |
JP2000223618A (en) * | 1999-02-01 | 2000-08-11 | Fujitsu Ltd | Semiconductor device |
DE19922473A1 (en) * | 1999-05-19 | 2000-11-30 | Giesecke & Devrient Gmbh | Chip carrier module has cut-outs forming large-area setting material holders with boundary forming setting material flow barrier, bridges mechanically connecting adjacent contact areas |
JP2001267483A (en) * | 2000-03-16 | 2001-09-28 | Hitachi Cable Ltd | Semiconductor device, manufacturing method thereof, and electronic device |
JP2002176125A (en) * | 2000-12-06 | 2002-06-21 | Nikon Corp | Semiconductor device, mounting method of semiconductor element, alignment method thereof |
JP2002312746A (en) * | 2001-04-11 | 2002-10-25 | Toshiba Corp | Ic module, manufacturing method therefor and portable electronic device on which the ic module is mounted |
-
2007
- 2007-04-26 DE DE102007019795A patent/DE102007019795B4/en not_active Expired - Fee Related
-
2008
- 2008-04-25 JP JP2008115763A patent/JP2008277825A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2047474A (en) * | 1978-10-19 | 1980-11-26 | Cii Honeywell Bull | A strip carrying devices for processing electrical signals, and a method of producing the strip |
US4701236A (en) * | 1985-04-12 | 1987-10-20 | U.S. Philips Corporation | Method of manufacturing an electronic identification card |
JPS63284831A (en) * | 1987-05-18 | 1988-11-22 | Nippon Inter Electronics Corp | Manufacture of hybrid integrated circuit |
JPH088284A (en) * | 1994-06-20 | 1996-01-12 | Hitachi Ltd | Wire bonding structure and its reinforcement method |
US5992725A (en) * | 1996-03-13 | 1999-11-30 | Kabushiki Kaisha Toshiba | Apparatus and method for producing electronic elements |
US6288904B1 (en) * | 1996-09-30 | 2001-09-11 | Infineon Technologies Ag | Chip module, in particular for implantation in a smart card body |
DE102004032605A1 (en) * | 2004-07-05 | 2006-01-26 | Infineon Technologies Ag | Semiconductor component with a semiconductor chip and electrical connection elements to a conductor structure |
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JP2008277825A (en) | 2008-11-13 |
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