DE102007003634B3 - Hardware-protocol accelerator module for connection safety-protocol level i.e. data link layer, of transceiver, is configured to search data blocks from space to transfer data blocks to bit transmission-protocol level of transmitting unit - Google Patents

Abstract

The module (118) is configured to signalize a receipt of a data block determined by a transceiver at an external processor of the transceiver. An acknowledgment data block is produced and output within an acknowledgement time period predetermined by a connection safety protocol after receiving the data block determined by the transceiver. Data blocks selected for dispatch, are searched from a storage space to transfer the data blocks to a bit transmission-protocol level of an external transmitting unit of the transceiver. An independent claim is also included for a sensor node comprising a sensor detecting blood pressure value of a patient, and a transceiver.

Description

The The invention relates to a hardware protocol accelerator module for a connection backup protocol layer a transceiver. Furthermore, the invention relates to a transceiver with a hardware protocol accelerator and a sensor node with a sensor and a transceiver connected thereto. The The present invention is particularly, but not exclusively, suitable for Application under the protocol IEEE 802.15.3, which is the communication within short-range wireless networks with high transmission capacity.

The Protocol IEEE 802.15.3 allows wireless communication in a radio network in which the nodes network with data rates of 11-55 Mbit / s communicate with each other. The above standard describes a short-distance radio technology and is for typical distances between the network nodes between 0.2 and 50 m has been developed.

For many Applications is low energy consumption of network nodes in the foreground. For example, the Applicant develops one wireless communication system for monitoring health status of patients using a variety of biomedical sensors. It is a close body Radio network in which various such sensors are linked. The sensor nodes communicate with each other about their state of health of a patient. Each sensor node contains one or more sensors and a processing and a communication unit. The communication unit is also referred to herein as a transceiver.

The Power supply of the sensor nodes of such a network is about small Batteries over several weeks or months without battery change or charging be ensured. The thus available small amount of energy for radio communication places very high demands on the technical Implementation of the protocol in particular at the connection assurance level.

Common synonyms for the Connection protection protocol level (English: data link layer) according to the OSI model, the terms layer 2, media access level (medium access layer), data link layer, cut-off layer, Connection level and procedure level. The connection backup protocol level is a largely error-free transmission secure and controls access to the transmission medium (layer 1 or physical layer). The bitstream becomes this divided into data blocks. Furthermore, usually Block sequence numbers and block checksums added. The Layer 2 protocol is also responsible for corrupted or lost blocks by the receiver side Reclaim receipt and retry mechanisms. Data blocks are also called frames or frames.

A So-called flow control makes it possible for a recipient to be dynamic Controls the speed with which the far side sends data blocks may. Contains IEEE The Link Backup Log level has two sub-levels that are logical Connection control (LLC, Logical Link Control) or media access control (MAC, Media Access Control) are.

following becomes the connection backup protocol level after the protocol IEEE 802.15.3 closer described.

The IEEE 802.15.3 MAC Protocol (IEEE Standard 802, "Part 15.3: Wireless Medium Access Control (MAC)) and Physical Layer (PHY) Specifications for High Rate Wireless Personal Area Networks, "2003.) works on the following basic principle: In a radio network, the after This standard works, there is exactly one coordinator and one Set of associated devices , The coordinator sends so-called beacon data blocks to all at exactly regular intervals equipment in the web. These beacon data blocks Among other things, information about when the next beacon is sent and how the devices in time until this next one Beacon to access the channel.

It There are reserved slots (time slots) that are for exact a transmitter for a certain duration exclusively available. As reference time will be the beginning of the transmission of the beacon frame, d. H. the start time of the time slots is specified in microseconds after the start of the beacon. In addition, the Coordinator a competitive phase that follows immediately after the beacon, establish. In this competition phase, all devices may use a back-off procedure access the channel.

The protocol specifies that all transmitted data blocks have an error detection code be provided. For this purpose, a CRC (Cyclic Redundancy Check) algorithm is used, which calculates a 32-bit checksum over all data block data and places it at the end of the data block. The receivers of the data block in turn calculate the CRC checksum on the received data block data and compare the result with the sent, determined by the transmitter, value. If both checksums match, the data block has been transferred with a very high probability correctly, otherwise it is recognized as defective and discarded.

at the majority of the defined data block types, in particular the command data blocks, is from Sender of the data block expects the recipient to receive a confirmation message directly, d. H. exactly 10 microseconds after the end of the confirmed Data block to transmit to the sender if the received data block was received without errors.

Out the publication PANIC, G. [supra]: A System-on-Chip Implementation of the IEEE 802.11a MAC layer; in: Proceedings of the Euromicro Symposium on Digital System Design; ISBN: 0-7695-2003-0; 2003, pp. 319-324 is a hardware protocol accelerator module known.

According to a first aspect of the invention, a hardware protocol accelerator module is proposed for a connection assurance protocol level of a first transceiver, which is designed
to filter data blocks incoming via a bit transmission protocol layer of an external receiving unit from an external second transceiver with regard to a destination contained in the data blocks and to initiate a memory operation at a predetermined external memory location of the first transceiver relative to data blocks intended for the first transceiver;
check data blocks destined for the first transceiver for successful reception;
signal successful reception of a data block destined for the first transceiver to an external processor of the first transceiver;
after successfully receiving a data block destined for the first transceiver, generating and outputting a confirmation data block destined for the second transceiver within a confirmation period specified by the connection assurance protocol;
to extract time slot information about one or more transmission time slots assigned to the first transceiver to a received beacon frame;
manage a queue of data blocks to be sent and select data blocks of the queue for transmission within the assigned transmission time slot;
to read out data blocks selected for sending from a memory location known from the queue and to transfer them to a bit transmission protocol level of an external transmission unit of the first transmitter-receiver.

The Hardware Protocol Accelerator Module of the First Aspect of the Invention Based on the knowledge that certain time-critical requirements of the protocol, for example when transmitting an acknowledgment data block, which exactly 10 μs after the end of the confirmation Data block, such as the very high data rate, which supports which would require a very fast processor. estimates have shown that the clock frequency in the range above 1 GHz would have to lie.

In order to However, there is a very high energy demand and therefore only an extremely short one Battery life.

The inventive hardware protocol accelerator module for the In contrast, the Link Backup log level allows the To relieve processor and especially time-critical functionalities of Exercise the connection protection protocol level of the transceiver. There These time-critical protocol functions are no longer available from the processor accomplished Need to become, this can be operated at a lower clock rate and thus reduce its energy consumption.

following Be exemplary embodiments the hardware protocol accelerator module according to the invention described. The embodiments can be combined with each other, unless expressly contrary explained is.

In one embodiment, the hardware protocol accelerator module includes an interrupt unit configured to signal a successful receipt of a data block destined for the first transceiver to an external processor of the first transceiver by transmitting a corresponding first interrupt signal and configured to be received a confirmation message externally to send a corresponding second interrupt signal to the external processor via the successful receipt of a data block sent by the first transceiver.

at a further embodiment is a redundancy check unit provided, which is formed immediately after receiving a Data frame according to a predetermined algorithm of the cyclic redundancy check checksums incoming or outgoing data blocks or both incoming and outgoing data blocks as well as outgoing data blocks to calculate and the test result corresponding test signal within the confirmation period issue.

at another embodiment the hardware protocol accelerator module is formed, a back-off method to be implemented in a protocolled competition phase.

Prefers are in the hardware protocol accelerator module of the present invention different operations of the hardware protocol accelerator module each associated with individual circuits. The circuits are connected to a common clock and trained, in the same Clock cycle to be operated in parallel. That way too the clock frequency for the hardware protocol accelerator module is kept low, which allows for further energy savings.

In a further embodiment has the hardware protocol accelerator module a queue unit that has a reference list in one stored to the hardware protocol accelerator module external memory and data blocks to be sent having. With this training the queue unit eliminates the Need to separate space for data blocks in the protocol accelerator module and will not be additional internal processing capacity for the Storing and reading data claimed. The queue unit is formed, the reference list in the form of a variety of partial reference lists create and update. Each partial reference list takes references to data blocks of only one Data block type. In this way, access to the respective data blocks a type very fast.

Preferably The Queue Unit is additionally designed to suit everyone Entry in a partial reference list next to the mentioned reference to a data block additionally a second or third reference to either a subsequent one or a previous entry in the relevant sub-reference list assign. In one embodiment be at least part of the entries in a respective sub-reference list both mentioned additional Assigned references.

The Hardware protocol accelerator module has in a further embodiment a transmission duration calculation unit, which is formed, based on a predetermined data block length and a predetermined data rate, the duration of the transmission of a data block to calculate. The transmission duration calculation unit is connected to the scheduler and the queue unit.

According to one second aspect of the invention is a transceiver with a hardware protocol accelerator module according to the first Aspect of the invention or one of its embodiments mentioned herein proposed. The transceiver of the second aspect of the invention shares the advantages of the hardware protocol accelerator module of the first aspect of the invention.

According to one third aspect of the invention is a sensor node with a sensor and a transceiver associated therewith according to the second aspect of the invention proposed. The sensor node of the second aspect of the invention shares the benefits of the hardware protocol accelerator module of the first aspect of the invention.

Not only for reasons energy efficiency, but also in favor of the wearing comfort of a Patients will be able to achieve high integration of a sensor node ideally as a one-chip solution can be realized. This chip is referred to below as a sensor node platform designated. For example, a sensor node platform becomes a Processor included for the processing of an application software and also of non-time critical Sharing the connection backup protocol of the transceiver is responsible.

at preferred embodiments the sensor node is the sensor, a blood pressure value a carrier to capture the size of the sensor, an electrocardiogram of a vehicle of the sensor, or another size that is physiological State or process describes to capture and a value the size corresponding Output signal.

following become further embodiments explained with reference to the figures. Show it:

1 a schematic diagram of a body-area network with a sensor node;

2 a schematic block diagram of an embodiment of a hardware protocol accelerator module for the connection assurance protocol layer according to the IEEE 802.15.3 protocol in a transceiver.

A sensor node platform 100 is in 1 shown in the form of a schematic block diagram. Exemplary sensors used in 1 are a lung tone sensor 102 , an ECG sensor 104 , a blood pressure sensor 106 and an accelerometer 108 , The in the left part of the figure by dots 102 to 108 symbolized sensor nodes 102 to 108 are in the form of the sensor node 104 Represented in the right half of the figure with greater detail.

The sensor node 104 contains a processor 110 , here a LEON2 processor, which is designed for the processing of application software as well as non-time critical parts of the connection assurance protocol level of the protocol IEEE 802.15.3. Via a common AHB bus 112 is the processor with an AHB controller 114 , a memory controller 116 , a hardware protocol accelerator module 118 (Protocoll Accelerator), a baseband process control ("Base Band Processing") 120 , an RF frontend 122 and an AHB / APB bridge 124 connected. The AHB / APB bridge 124 is via an APB bus 126 with the memory controller 116 and timers 128 , Interrupt request controls (IRQCTRL) 130 , an input / output interface (I / O port) 132 and a UART interface 134 connected. Via the input / output interface 132 and the UART interface 134 is connected to one or more connected sensors 136 and 138 of the sensor node 104 communicated. The sensors are in the ECG sensor node 104 known ECG sensors. Furthermore, the sensor node contains 104 a first memory 140 , For example, an SRAM memory, and a second memory, such as a PROM memory 142 both via a memory bus 144 with the memory controller 116 are connected.

2 shows a schematic block diagram of the sensor node 1 in which the hardware protocol accelerator module ("Protocol Accelerator") 118 out 1 is shown in more detail.

• – Datenblöcke von der Bitübertragungsschicht 154 entgegen zu nehmen (Empfangsrichtung), zu filtern, die CRC-Prüfsumme auszurechnen und über direkten Speicherzugriff an einer vorher angegebenen Stelle im Speicher abzulegen,
• – den Prozessor 110 zu benachrichtigen (per Interrupt), wenn ein Datenblock erfolgreich empfangen wurde, sodass der Prozessor die Datenblockauswertung übernehmen kann,
• – empfangene Datenblöcke, für die eine Bestätigung (Immediate Acknowledgement Datenblock) gesendet werden muss, nach 10 Mikrosekunden zu bestätigen,
• – einen Beacon-Datenblock, und zwar sowohl das gesendete im Falle, dass das Gerät PNC (Piconet-Controller) ist, als auch das empfangene, hinsichtlich der reservierten Zeitschlitze auszuwerten,
• – eine Warteschlange mit notwendigen Information über abzusendende Datenblöcke zu verwalten,
• – entsprechend der verstrichenen Zeit seit Start des Beacon-Datenblocks und der im Beacon festgelegten Zeitschlitze zur vorgesehenen Zeit ein Datenblock aus der Warteschlange zum Absenden zu wählen,
• – das Backoff-Verfahren in der Wettbewerbsphase umzusetzen,
• – die Datenblockdaten über direkten Speicherzugriff zu holen, die CRC-Prüfsumme zu berechnen, an die Bitübertragungsschicht zu übergeben, ggf. auf die Bestätigung zu warten und den Prozessor per Interrupt über den Erfolg der Datenblockübertragung zu informieren.

The tasks of the protocol accelerator 118 consist in

• - Data blocks from the physical layer 154 to receive (receive direction), to filter, to calculate the CRC checksum and store it in memory via a direct memory access at a previously specified location,
• - the processor 110 to notify (via interrupt) if a data block has been successfully received so that the processor can take over the data block evaluation,
• - to acknowledge received data blocks for which an acknowledgment (Immediate Acknowledgment Data Block) must be sent, after 10 microseconds,
• A beacon data block, both the one sent in the event that the device is PNC (piconet controller), and the one received, with regard to the reserved time slots,
• To manage a queue with necessary information about blocks of data to be sent,
• According to the elapsed time since the start of the beacon data block and the time slots defined in the beacon at the designated time to select a data block from the queue for sending,
• - implement the back-off procedure in the competitive phase,
• To fetch the data block data via direct memory access, to calculate the CRC checksum, to pass it to the physical layer, if necessary to wait for the acknowledgment and to notify the processor by means of an interrupt about the success of the data block transmission.

That in the 2 illustrated hardware protocol accelerator module 118 communicates with the help of a receive data controller 150 and a transmit data controller 152 with functional blocks of an external physical layer relative to the hardware protocol accelerator module 154 the transceiver. Both controllers 150 and 152 are with CRC test units 156 respectively. 158 connected performing a cyclic redundancy check according to known algorithms.

About one in 2 not shown internal bus are the receive data controller 150 and the transmit data controller 152 with an interrupt unit 160 connected to the LEON2 processor 110 notified by interrupt if a data block was successfully received, so that it can take over the data block evaluation, or if a data block was successfully transmitted to a second, external transceiver.

The send data controller 152 and the receive data controller 150 are via a DMA (Direct Memory Access) unit 162 , a master interface 164 , the system bus, and the memory controller 116 with the to the protocol accelerator 118 external memory 140 (not shown here, but see 1 ), and can access data blocks at predetermined locations in memory via direct memory access 140 store, or data blocks of predetermined locations in the memory 140 recall.

A beacon analysis unit 166 is with the receive data controller 150 and the transmit data controller 152 connected and used to evaluate a beacon data block and for controlling the operation of the hardware protocol accelerator module 118 via a scheduler 168 and a timer 170 , The send data controller 152 accesses the scheduler 168 on a send queue 172 to, and ensures that in time for the predetermined in the beacon data block time slot transmission data from the send queue 172 and to the physical layer 154 to be forwarded for shipment.

Furthermore, the hardware protocol acceleration module results 118 in the competition phase envisaged by the IEEE 802.15.3, a back-off procedure.

In order to explain in more detail the mode of operation of the protocol accelerator and the interaction of its components, the sequence of sending a data block is shown below. It is assumed that a data packet, also referred to below as a packet, is sent as the data block. The description makes reference to the protocol IEEE 802.15.3, under which the protocol accelerator 118 serves to accelerate the MAC level.

The protocol accelerator 118 is in an already associated device in use, ie, beacon packets are received regularly. The data of the beacon, 16 bits in succession, from the physical layer 154 to the receive data controller 150 to hand over. This directs the received data stream into the CRC algorithm 156 and also via direct memory access (DMA) to a previously from the processor 110 certain memory address. If it is detected that the packet is a beacon - this information is contained in the protocol header - the data also goes to the beacon analysis unit 166 ,

The same happens in the send data controller 152 in the case of the coordinator sending and not receiving beacon packets.

In the beacon analysis unit 166 Among other things, the information about the time slots to which the device is allowed to send is extracted and stored locally in registers until the next beacon.

The scheduler 168 receives a control signal as soon as the end of the beacon packet has been reached - now the scheduler takes over 168 the control of the packages to be sent. The timer 170 is required to display the current time within the superframe from the beginning of the beacon transmission. The scheduler asks with this time information and the time slot information from the beacon analysis 168 at the send queue 172 at the beginning of a time slot and after the end of a packet transmission, a next packet to be sent.

Is there a matching packet in the send queue? 172 so becomes the transmit data controller 152 commissioned with its transmission. It is possible that several packet transmissions occur within a time slot.

An additional transmission duration calculation unit 174 (CalcDuration), calculates the actual duration of the transmission, based on the packet length and its data rate. The same transmission duration calculation unit 174 is also from the send queue 172 used to determine if the transmission still fits in the timeslot.

The timing by the timer 170 ensures that the scheduler 168 after transmission, the next packet either still for the same or the next time slot from the send queue 172 requests. The scheduler 168 also initiates sending the beacon at the beginning of the next superframe.

Below is the operation of the send queue 172 described in more detail.

That in the protocol accelerator 118 realized automatic sending of parcels - without the immediate control of the LEON2 processor 110 - in the interaction of scheduler 168 , Send queue 172 and direct memory access through the DMA unit 162 allows the processing speed and thus the power consumption of the processor 110 to reduce. A crucial role is played by the send queue 172 ,

The one for use in the protocol accelerator 118 provided send queue 172 contains a list or table of information about packets to be sent, but not the packets themselves. These are stored in memory, which is external to the protocol accelerator. The on the LEON2 processor 110 running log software fills this table according to the packet volume. A message to the processor 110 is sent as soon as a packet has been sent successfully or could not be transmitted several times. Then the table entry can be done by the processor 110 be replaced by a new entry. However, this does not happen immediately because there are enough other packets in the send queue 172 ready.

For example, the send queue can 172 contain eight table entries. However, it could also be significantly more table entries, z. For example, 32 or 64. To speed up a matching packet upon request by the scheduler 168 To be able to search out package lists for different types of packets, such as beacon packets or those that can be sent in the Contention Access Period. The initial list entry is stored, from where the entire list can be traversed by references to the next list element. In addition, there are also references to the previous element in order to efficiently support deletion operations.

The result is the structure of the table entries summarized in Table 1 below, which also contains list management fields in addition to the actual packet data. field name purpose Valid Validity of the entry, package still to be sent. status State of transmission (successful, aborted) rate data rate frame_type Package Type (IEEE 802.15.3) src_id, dest_id Source address, destination address stream_index Identifier for isochronous data streams Length packet length payload_ptr Address of the package in the memory Offset, frag_size, frag_num, last_frag_number Details for package fragmentation msdu_num Packet sequence number retry_count Counter for failed transfers prev_elem, next_elem Reference to next / previous list element (index in the table) extra_data Unused data field that the software can describe, for example, to remember the index in a software table.

Table 1: In each table entry the Send Queue Information

In T. H. Meng, B. McFarland, D. Su, and J. Thomson, "Design and implementation of all-CMOS 802.11a wireless LAN chipset, "IEEE Commun. Mag., vol. 41, no. 8, pp. 160-168, Aug. 2003 is the use in another context mentioned by package descriptors. However, it is not known from this, a send queue in package lists for different Subdivide package types.

To the hardware design of the protocol accelerator 118 not to set a specific data rate and time intervals between the successive packet transmissions, the protocol accelerator points out 118 Software programmable registers 176 to 180 inserted, which determines the timing of the protocol accelerator 118 determine. These registers are from the scheduler 168 read out if this determines the time of sending the next packet. The registers 176 to 180 contain the SIFS, MIFS, and backoff slot values, each in microseconds.

There is also a register 182 , with the aid of which the above-mentioned transmission duration calculation unit 174 the duration of the transmission is calculated for a given packet length: time = packet length / data rate. The transmission duration calculation unit 174 occurs only once in the protocol accelerator and is claimed by several other units via the system bus (not shown). An arbitration procedure ensures that only one unit at a time has exclusive access to the transmission duration calculation unit 174 receives.

Claims (12)

Hardware Protocol Accelerator Module for a Connection Backup Log Level first transceiver, that is trained above a bit transfer protocol level an external receiving unit from an external second transceiver incoming data blocks with regard to a destination address contained in the data blocks filter and refer for the first transceiver certain data blocks a memory operation at a predetermined external memory location of the first transceiver to induce; For the first transceiver certain data blocks to check for successful reception; a successful one Reception of a for the first transceiver certain data block to an external processor of the first transceiver signal; after successfully receiving one for the first Transmitter-receiver certain data block one for the second transceiver certain confirmation data block within a predetermined by the connection backup protocol Confirmation period to generate and output; a received beacon frame Time slot information about one or more transmit time slots assigned to the first transceiver refer to; to manage a queue of data blocks to be sent and data blocks the queue for transmission within the assigned transmission time slot select; to the Send selected data blocks read from a known from the queue storage space and to a bit transfer protocol layer an external transmitting unit of the first transceiver to pass. Hardware protocol accelerator module according to claim 1, with an interrupt unit formed by sending out a corresponding first interrupt signal a successful one Reception of a for the first transceiver certain data block to an external processor of the first transceiver signal, and which is formed upon receipt of a confirmation message externally via the successful reception of a message sent by the first transceiver Data block a corresponding second interrupt signal to the external To send processor. Hadware protocol accelerator module according to claim 1 or 2, with a redundancy check unit, the is formed immediately after receiving a data frame a predetermined algorithm of the cyclic redundancy check checksums incoming or outgoing data blocks or both incoming and outgoing data blocks as well as outgoing data blocks to calculate and the test result corresponding test signal within the confirmation period issue. Hardware protocol accelerator module according to claim 1, which is adapted to a back-off procedure in a protocol implementation of the planned competition phase. Hardware protocol accelerator module according to claim 1, which is used to implement a connection backup protocol level tasks formed according to the protocol IEEE 802.15.3 in a transceiver is. Hardware protocol accelerator module according to claim 1, in the various operations of the hardware protocol accelerator module each individual circuits are assigned, with a common clock connected and formed in the same Clock cycle to be operated in parallel. A hardware protocol accelerator module as claimed in any one of the preceding claims, comprising a queue unit having a reference list with references to data blocks stored in and external to the hardware protocol accelerator module, the queue unit being adapted to create the reference list in the form of a plurality of partial reference lists and to ak and each sub-reference list includes references to data blocks of a data block type. Hardware protocol accelerator module according to claim 7, in which the queue unit is formed, each entry into a partial reference list next to a reference to a data block a second or third reference to a subsequent and / or a preceding entry in the relevant sub-reference list assign. Hardware protocol accelerator module according to one of previous claims, with a transmission duration calculation unit, which is formed, based on a predetermined data block length and a predetermined data rate, the duration of the transmission of a data block to calculate. Transmitter-receiver with a hardware protocol accelerator module according to any one of the preceding claims. Sensor node with one sensor and one with this connected transceiver according to claim 10. Sensor node according to claim 11, wherein the sensor is formed, a blood pressure value of a carrier of the Sensors to capture appropriate size, an electrocardiogram of a vehicle of the sensor, or another size that is physiological State or process describes to capture and a value the size corresponding Output signal.