DE102007002961A1 - Memory device for electrical devices, mobile phones and personal digital assistants, has memory pack of stored memory chips, which are displaced in relation to each other - Google Patents
Memory device for electrical devices, mobile phones and personal digital assistants, has memory pack of stored memory chips, which are displaced in relation to each other Download PDFInfo
- Publication number
- DE102007002961A1 DE102007002961A1 DE102007002961A DE102007002961A DE102007002961A1 DE 102007002961 A1 DE102007002961 A1 DE 102007002961A1 DE 102007002961 A DE102007002961 A DE 102007002961A DE 102007002961 A DE102007002961 A DE 102007002961A DE 102007002961 A1 DE102007002961 A1 DE 102007002961A1
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Abstract
Description
HINTERGRUND DER ERFINDUNGBACKGROUND OF THE INVENTION
Die Erfindung betrifft eine Speichervorrichtung, welche zumindest einen Speicherstapel von gestapelten Speicherchips aufweist, die in Bezug zueinander versetzt sind.The The invention relates to a storage device which comprises at least one Memory stack of stacked memory chips, with respect to offset from each other.
Insbesondere betrifft die Erfindung einen Flash-Speicher mit zumindest einem Flash-Speicherstapel von gestapelten Flash-Speicherchips, die in Bezug zueinander versetzt gestapelt sind.Especially The invention relates to a flash memory with at least one Flash memory stacks of stacked flash memory chips that are related to each other staggered are staggered.
Die Marktanforderung für kleinere, leichtere und leistungsfähigere Mobiltelefone, PDAs und weitere elektronische Vorrichtungen treibt die Entwicklung von kompakteren elektronischen Baugruppen in einem Gehäuse bzw. Gehäusen mit erhöhter Funktionalität an. Zur Erhöhung von Funktionalität und Kapazität elektronischer Vorrichtungen werden Speicherchips übereinander gestapelt. Jeder Stapel weist zwei, drei und vier mit Draht gebondete Chips auf, welche in typischer Weise in einer Pyramide oder in einem Stapel gleichgroßer Chips in überhängender Bauweise angeordnet sind. In dieser herkömmlichen Lösung sind Chips entweder mit einem Abstandshalter oder mit einem Zwischenlager dazwischen übereinander gestapelt. Derzeit sind Chips mit einer Dicke von ungefähr 100 μm in Produktion. Bei herkömmlichen Speicherchipstapeln ist die Anzahl von Chips, welche übereinander gestapelt sind, auf Grund der Einschränkungen der zulässigen Baugruppenhöhe begrenzt. Wenn Chips übereinander gestapelt werden, wird das Bonden der Chip-Pads, die auf jedem Chip angeordnet sind, mit korrespondierenden Pads auf einem Substrat der Speichervorrichtung schwierig, und das Drahtbonden verbraucht mehr Raum bei erhöhter Anzahl von übereinander gestapelten Chips. Der Platzverbrauch für Drahtbonden erhöht sich insbesondere, wenn ein Pad oder ein Chip an unterschiedliche Pads auf dem Substrat gebondet wird. Außerdem erhöht sich bei zunehmender Anzahl von Drahtbonds ein Risiko von visuellen und elektrischen Kurzschlüssen.The Market requirement for smaller, lighter and more powerful mobile phones, PDAs and other electronic devices is driving the development of more compact electronic assemblies in a housing or housings with elevated functionality at. To increase of functionality and capacity electronic devices become memory chips on top of each other stacked. Each stack has two, three and four wire-bonded ones Chips, which are typically in a pyramid or in one Stack of equal size Overhanging chips are arranged. In this conventional solution are Chips either with a spacer or with an intermediate storage between them stacked. Currently, chips with a thickness of approximately 100 μm are in production. In conventional Memory chip stacks is the number of chips that are stacked on top of each other stacked, limited due to the limitations of the allowable assembly height. When chips are stacked on top of each other Be the bonding of the chip pads that are placed on each chip are, with corresponding pads on a substrate of the storage device difficult, and wire bonding consumes more space with an increased number stacked on top of each other Crisps. The space consumption for Wire bonding increased in particular, if a pad or a chip to different Pads is bonded to the substrate. It also increases as the number of Wire bonds a risk of visual and electrical short circuits.
ZUSAMMENFASSUNG DER ERFINDUNGSUMMARY OF THE INVENTION
Die
Erfindung stellt eine Speichervorrichtung bereit, welche zumindest
einen Speicherstapel von gestapelten Speicherchips aufweist, die
in Bezug zueinander versetzt sind,
wobei jeder gestapelte Speicherchip
des Speicherstapels längs
seines Rands Chip-Pads zum Bonden des gestapelten Speicherchips
an Substrat-Pads der Speichervorrichtung aufweist, die mit einem
Steuerkreis bzw. einer Steuerschaltung verbindbar sind,
wobei
jedes Chip-Pad eines gestapelten Speicherchips, welches den Speicherchip
mit einem Substrat-Pad, das mit der Steuerschaltung verbindbar ist, individuell
verbindet, einen vergrößerten Abstand
im Vergleich zu Chip-Pads des gestapelten Speicherchips aufweist,
welche den gestapelten Speicherchip parallel mit korrespondierenden
Chip-Pads von anderen gestapelten Speicherchips des Speicherstapels
mit korrespondierenden Substrat-Pads, die mit der Steuerschaltung
verbindbar sind, verbinden.The invention provides a memory device having at least one memory stack of stacked memory chips offset with respect to each other,
wherein each stacked memory chip of the memory stack has along its edge chip pads for bonding the stacked memory chip to substrate pads of the memory device connectable to a control circuit and a control circuit, respectively;
wherein each chip pad of a stacked memory chip that individually connects the memory chip to a substrate pad connectable to the control circuit has an increased distance compared to chip pads of the stacked memory chip that connect the stacked memory chip in parallel with corresponding chip -Pads of other stacked memory chips of the memory stack with corresponding substrate pads, which are connectable to the control circuit connect.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung ist ein Abstandsmuster der Chip-Pads längs des Rands eines gestapelten Speicherchips für alle gestapelten Speicherchips des gleichen Speicherstapels identisch.In an execution the memory device according to the present The invention is a spacing pattern of the chip pads along the edge of a stacked one Memory chips for all stacked memory chips of the same memory stack identical.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind die auf einem Substrat der Speichervorrichtung vorgesehenen Substrat-Pads in zumindest einer Reihe von Substrat-Pads angeordnet, welche im Wesentlichen parallel zu einem Rand des untersten gestapelten Speicherchips des Speicherstapels ausgerichtet sind, oder die Substrat-Pads sind in einer gekrümmten Linie zur Erhöhung der jeweiligen Zwischenräume angeordnet.In an execution the memory device according to the present Invention are provided on a substrate of the storage device substrate pads arranged in at least one row of substrate pads, which in the Essentially parallel to an edge of the lowest stacked memory chip of the memory stack, or are the substrate pads in a curved Line to increase the respective spaces arranged.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung weist jeder gestapelte Speicherchip einen Pad-Randbereich auf, in welchem die Chip-Pads des Speicherchips angeordnet sind.In an execution the memory device according to the present In the invention, each stacked memory chip has a pad edge region on, in which the chip pads of the memory chip are arranged.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind die Speicherchips in einer asymmetrischen versetzten Treppenanordnung übereinander gestapelt.In an execution the memory device according to the present Invention, the memory chips in an asymmetric offset Staircase arrangement on top of each other stacked.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung ist der vergrößerte Abstand gegeben durch: wobei N die Anzahl übereinander gestapelter Speicherchips in einer asymmetrischen versetzten Treppenanordnung ist, und ds ein minimaler Padabstand solcher auf dem Substrat der Speichervorrichtung vorgesehener Pads ist.In an embodiment of the memory device according to the present invention, the increased distance is given by: where N is the number of stacked memory chips in an asymmetric staggered arrangement of stairs, and d s is a minimum of such pad spacing on the substrate of the memory device provided pads.
In
einer Ausführung
der Speichervorrichtung gemäß der vorliegenden
Erfindung ist der minimale Padabstand ds solcher
auf dem Substrat der Speichervorrichtung vorgesehener Pads gegeben
durch: wobei hs ein
Abstand zwischen zwei korrespondierenden Chip-Pads von zwei versetzten Speicherchips
des Speicherstapels ist,
h0 der Abstand
zwischen Chip-Pads des untersten Speicherchips des Speicherstapels
und Substrat-Pads ist, die auf einem Substrat der Speichervorrichtung
vorgesehen sind, und
αmin ein minimaler Winkel ist, welcher verhindert,
dass ein Bonddraht ein anderes Chip-Pad kreuzt.In one embodiment of the memory device according to the present invention, the minimum pad spacing d s of such pads provided on the substrate of the memory device is given by: where h s is a distance between two corresponding chip pads of two staggered memory chips of the memory stack,
h 0 is the distance between chip pads of the lowest one Memory chips of the memory stack and substrate pad is provided on a substrate of the memory device, and
α min is a minimum angle which prevents a bond wire from crossing another chip pad.
In
einer Ausführung
der Speichervorrichtung gemäß der vorliegenden
Erfindung ist der minimale Winkel αmin gegeben
durch: wobei wp die
Breite eines Chip-Pads ist,
hp die
Länge eines
Chip-Pads ist, und
hs der Abstand zwischen
zwei korrespondierenden Chip-Pads von zwei versetzten Speicherchips
des Speicherstapels ist.In one embodiment of the memory device according to the present invention, the minimum angle α min is given by: where w p is the width of a chip pad,
h p is the length of a chip pad, and
h s is the distance between two corresponding chip pads of two staggered memory chips of the memory stack.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind die Speicherchips in einer symmetrischen versetzten wechselnden Anordnung übereinander gestapelt.In an execution the memory device according to the present Invention, the memory chips are in a symmetrical offset changing arrangement on top of each other stacked.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind die gestapelten Speicherchips so abwechselnd zueinander gestapelt, dass die Pad-Randbereiche von zwei Speicherchips, welche direkt übereinander gestapelt sind, in gegenüber liegenden Richtungen ausgerichtet sind.In an execution the memory device according to the present Invention, the stacked memory chips are so alternately to each other stacked that pad edge areas of two memory chips, which directly above each other are stacked in opposite are aligned lying directions.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind die Speicherchips zur Bildung einer Pyramide von gestapelten Speicherchips übereinander gestapelt.In an execution the memory device according to the present Invention are the memory chips to form a pyramid of stacked memory chips on top of each other stacked.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind die gestapelten Speicherchips direkt aufeinander angebracht.In an execution the memory device according to the present Invention, the stacked memory chips directly to each other appropriate.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind die gestapelten Speicherchips des Speicherstapels aneinander verklebt.In an execution the memory device according to the present Invention are the stacked memory chips of the memory stack glued together.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung ist ein Abstandshalter bzw. eine Zwischenla ge zwischen zwei gestapelten Speicherchips des Speicherstapels vorgesehen.In an execution the memory device according to the present Invention is a spacer or a Zwischenla ge between provided two stacked memory chips of the memory stack.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung ist der zumindest eine Speicherstapel in einer Baugruppe bzw. einem Gehäuse der Speichervorrichtung geformt.In an execution the memory device according to the present Invention is the at least one memory stack in an assembly or a housing the storage device shaped.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind die gestapelten Speicherchips als gestapelte Flash-Speicher ausgebildet.In an execution the memory device according to the present Invention, the stacked memory chips are formed as stacked flash memory.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung ist ein Chip-Pad des gestapelten Speicherchips, welches die Speichervorrichtung individuell mit der Steuerschaltung verbindet, zur Aufbringung eines Chipfreigabesignals auf den gestapelten Speicherchip vorgesehen.In an execution the memory device according to the present Invention is a chip pad of the stacked memory chip, which individually connecting the memory device to the control circuit, for applying a chip enable signal to the stacked memory chip intended.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung ist das Chip-Pad des gestapelten Speicherchips, welches die Speichervorrichtung individuell mit der Steuerschaltung verbindet, für ein Lese-/In-Betrieb-Signal vorgesehen.In an execution the memory device according to the present Invention is the chip pad of the stacked memory chip, which individually connecting the memory device to the control circuit, for a Read / in operation signal provided.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung ist eine Anzahl von gestapelten Speicherchips des Speicherstapels mindestens vier.In an execution the memory device according to the present Invention is a number of stacked memory chips of the memory stack at least four.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung ist eine Anzahl von gestapelten Speicherchips des Speicherstapels mindestens acht.In an execution the memory device according to the present Invention is a number of stacked memory chips of the memory stack at least eight.
Die
Erfindung stellt weiterhin einen Flash-Speicher bereit, welcher
zumindest einen Flash-Speicherstapel von gestapelten Flash-Speicherchips
aufweist, die in Bezug zueinander versetzt sind,
wobei jeder
gestapelte Flash-Speicherchip längs
einer seiner Ränder
Chip-Pads zum Bonden des gestapelten Flash-Speicherchips an Substrat-Pads aufweist,
die auf einem Substrat des Flash-Speicherstapels zur Verbindung
des Flash-Speicherstapels
mit einer auf dem Flash-Speicher vorgesehenen Steuereinrichtung
angeordnet sind,
wobei jedes Chip-Pad eines gestapelten Flash-Speicherchips,
welches zur individuellen Verbindung des gestapelten Flash-Speicherchips mit
der Steuereinrichtung vorgesehen ist, einen vergrößerten Abstand im
Vergleich zu Chip-Pads des gestapelten Flash-Speicherchips aufweist,
welche zur parallelen Verbindung des gestapelten Flash-Speicherchips
mit korrespondierenden Chip-Pads von anderen gestapelten Flash-Speicherchips
des Flash-Speicherstapels mit der Steuereinrichtung vorgesehen sind.The invention further provides a flash memory having at least one flash memory stack of stacked flash memory chips offset with respect to each other,
wherein each stacked flash memory chip has along one of its edges chip pads for bonding the stacked flash memory chip to substrate pads disposed on a substrate of the flash memory stack for connecting the flash memory stack to a controller provided on the flash memory are,
wherein each chip pad of a stacked flash memory chip, which is provided for the individual connection of the stacked flash memory chip with the control device, has an increased distance compared to chip pads of the stacked flash memory chip, which is used for the parallel connection of the stacked flash memory chip. Memory chips are provided with corresponding chip pads of other stacked flash memory chips of the flash memory stack with the controller.
In einer Ausführung des Flash-Speichers gemäß der vorliegenden Erfindung sind die Flash-Speicherchips in einer asymmetrischen versetzten Treppenanordnung übereinander gestapelt.In an execution the flash memory according to the present invention Invention are the flash memory chips in an asymmetric offset Staircase arrangement on top of each other stacked.
In einer Ausführung des Flash-Speichers gemäß der vorliegenden Erfindung sind die Flash-Speicherchips in einer symmetrischen versetzten wechselnden Anordnung übereinander gestapelt.In an execution the flash memory according to the present invention Invention are the flash memory chips in a symmetrical offset changing arrangement on top of each other stacked.
Die Erfindung stellt weiterhin eine Speichervorrichtung bereit, welche zumindest zu einem Speicherstapel von gestapelten Speicherchips korrespondiert, die direkt aufeinander gestapelt sind, und die in Bezug zueinander in einer symmetrischen wechselnden Anordnung versetzt sind.The invention further provides a memory device which corresponds at least to a memory stack of stacked memory chips which are stacked directly on top of one another and which are offset with respect to one another in a symmetrical alternating arrangement.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung weist jeder gestapelte Speicherchip Chip-Pads auf, welche auf einer oberen Seite des gestapelten Speicherchips in einem Pad-Randbereich längs eines Rands des gestapelten Speicherchips angeordnet sind.In an execution the memory device according to the present Invention, each stacked memory chip on chip pads, which on an upper side of the stacked memory chip in a pad edge area along a Rands of the stacked memory chip are arranged.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind die gestapelten Speicherchips so in Bezug zueinander versetzt, dass die Pad-Randbereiche von allen gestapelten Speicherchips wechselnde Vorsprünge des symmetrischen Speicherstapels bilden.In an execution the memory device according to the present Invention, the stacked memory chips are so in relation to each other offset the pad margins from all stacked memory chips changing projections form the symmetric memory stack.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind die gestapelten Speicherchips so in Bezug zueinander wechselnd gestapelt, dass die Pad-Randbereiche von zwei gestapelten Speicherchips, welche direkt aufeinander gestapelt sind, in gegenüber liegenden Richtungen ausgerichtet sind.In an execution the memory device according to the present Invention, the stacked memory chips are so in relation to each other Stacked alternately, that pad-edge areas of two stacked Memory chips stacked directly on each other in opposite directions are aligned.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind der oberste gestapelte Speicherchip und der direkt unter dem obersten gestapelten Speicherchip befindliche Speicherchip so aufeinander gestapelt, dass die Pad-Randbereiche von beiden gestapelten Speicherchips in der gleichen Richtung ausgerichtet sind.In an execution the memory device according to the present Invention are the top stacked memory chip and the direct memory chip located under the top stacked memory chip stacked on top of each other so that the pad margins of both stacked Memory chips are aligned in the same direction.
In einer Ausführung der Speichervorrichtung gemäß der vorliegenden Erfindung sind die Chip-Pads des obersten gestapelten Speicherchips an die korrespondierenden Chip-Pads des direkt unter dem obersten gestapelten Speicherchips befindlichen Speicherchips gebondet.In an execution the memory device according to the present Invention are the chip pads of the top stacked memory chip on the corresponding chip pads of the directly stacked under the top Memory chips located memory chips bonded.
Die Erfindung stellt weiterhin eine Flash-Speichervorrichtung bereit, welche zumindest einen Speicherstapel von gestapelten Flash-Speicherchips aufweist, die direkt aufeinander gestapelt sind, und die in Bezug zueinander in einer symmetrischen wechselnden Anordnung versetzt sind.The Invention further provides a flash memory device which at least one memory stack of stacked flash memory chips which are stacked directly on top of each other and in relation to each other offset from each other in a symmetrical alternating arrangement are.
Die
Erfindung stellt weiterhin ein Verfahren zum Herstellen eines Speicherstapels
bereit, welches die folgenden Verfahrensschritte aufweist: Bereitstellen
eines Speicherchips mit Chip-Pads, welche auf einer oberen Seite
des Speicherchips in einem Pad-Randbereich längs eines Rands des Speicherchips
angeordnet sind;
Drehen eines weiteren Speicherchips in Bezug
auf den vorhergehenden Speicherchip dergestalt, dass der Pad-Randbereich
von beiden Speicherchips in gegenüber liegenden Richtungen ausgerichtet
werden, und Anbringen des weiteren Speicherchips auf der oberen
Seite des vorhergehenden Speicherchips in einer versetzten Weise
dergestalt, dass der Pad-Randbereich des darunter liegenden vorhergehenden
Speicherchips unbedeckt bleibt; und
Wiederholen dieser Verfahrensschritte,
bis eine vorher festgelegte Anzahl von Speicherchips übereinander
gestapelt ist.The invention further provides a method for producing a memory stack, comprising the following method steps: providing a memory chip with chip pads, which are arranged on an upper side of the memory chip in a pad edge region along an edge of the memory chip;
Rotating another memory chip with respect to the previous memory chip such that the pad edge region of both memory chips are aligned in opposite directions, and attaching the further memory chip on the upper side of the preceding memory chip in a staggered manner such that the pad edge region the underlying previous memory chip remains uncovered; and
Repeating these steps until a predetermined number of memory chips are stacked one above the other.
In einer Ausführung des Verfahrens gemäß der vorliegenden Erfindung werden die Pads der beiden obersten gestapelten Speicherchips des Speicherstapels, deren Pad-Randbereiche beide unbedeckt sind, gleichzeitig in einem Drahtbonding-Verfahrensschritt an Pads eines Substrats gebondet.In an execution the method according to the present invention Invention, the pads of the two top stacked memory chips the storage stack whose pad margins are both uncovered, simultaneously in a wire bonding process step on pads of a substrate bonded.
In einer Ausführung des Verfahrens gemäß der vorliegenden Erfindung wird der weitere Speicherchip um 180° in Bezug auf den vorhergehenden Speicherchip gedreht.In an execution the method according to the present invention Invention, the further memory chip by 180 ° with respect to the previous memory chip turned.
In einer Ausführung des Verfahrens gemäß der vorliegenden Erfindung wird der weitere Speicherchip um 90° in Bezug auf den vorhergehenden Speicherchip gedreht.In an execution the method according to the present invention Invention, the further memory chip by 90 ° with respect to the previous memory chip turned.
In einer Ausführung des Verfahrens gemäß der vorliegenden Erfindung werden die Speicherchips aus Flash-Speicherchips gebildet.In an execution the method according to the present invention Invention, the memory chips are formed from flash memory chips.
In einer Ausführung des Verfahrens gemäß der vorliegenden Erfindung werden zumindest vier Speicherchips übereinander gestapelt.In an execution the method according to the present invention Invention, at least four memory chips are stacked on top of each other.
In einer Ausführung des Verfahrens gemäß der vorliegenden Erfindung werden zumindest acht Speicherchips übereinander gestapelt.In an execution the method according to the present invention Invention, at least eight memory chips are stacked on top of each other.
In einer Ausführung des Verfahrens gemäß der vorliegenden Erfindung werden die Speicherchips aneinander geklebt.In an execution the method according to the present invention Invention, the memory chips are glued together.
In einer Ausführung des Verfahrens gemäß der vorliegenden Erfindung werden die gestapelten Speicherchips in einer Baugruppe bzw. in einem Gehäuse geformt.In an execution the method according to the present invention Invention, the stacked memory chips in an assembly or in a housing shaped.
KURZE BESCHREIBUNG DER ZEICHNUNGENBRIEF DESCRIPTION OF THE DRAWINGS
DETAILLIERTE BESCHREIBUNG DER ERFINDUNGDETAILED DESCRIPTION THE INVENTION
Jeder
Chip-Pad
In
der Ausführung,
wie in
In
der in
In
der in
In
einer Ausführung
der Speichervorrichtung
In
einer noch weiteren Ausführung,
wie in
In
den in
In anderen Ausführungen ist es möglich, einen minimalen möglichen Padabstand dd auf dem Speicherchip 4-i vorzusehen, welcher geringer ist als der Padabstand auf dem Substrat ds, da es möglich ist, feinere Strukturen auf Silizium zu erzeugen als auf Substraten.In other embodiments, it is possible to provide a minimum possible pad spacing d d on the memory chip 4-i, which is less than the pad spacing on the substrate d s , since it is possible to produce finer structures on silicon than on substrates.
In
den in
In
anderen Ausführungen
weist die Speichervorrichtung
In
weiteren Ausführungen
ist es möglich, mehrere
Baugruppen von Speicherstapeln
Während einer
Herstellung der Speicherstapel
Wie
aus den in
Der
vergrößerte Abstand
di ist gegeben durch: wobei N die Anzahl von gestapelten
Speicherchips
Wie
aus
h0 ein Abstand zwischen Chip-Pads
αmin ein
minimaler Winkel ist, welcher vermeidet, dass ein Bonddraht
h 0 is a distance between chip pads
α min is a minimum angle, which avoids a bonding wire
Der
wie in
Die
Drahtbonds
In
der Ausführung,
die in
Bei
dem Drahtbondingschema, wie in
In
einer möglichen
Ausführung,
wie in
Die
Speicherschaltungsplatte
Wie
aus
Der
nächste
Speicherchip
Wie
in
In
der in
Die
Formdicke bzw. -stärke
kann wie folgt berechnet werden:
In
der in
In
dem gegebenen Beispiel ist die Abmessung der Chiplänge DL gegeben
durch:
Die Packungsbreite PW ist von der Chipbreite DW abhängig.The Pack width PW depends on the chip width DW.
In
der in
Für eine Packungsbreite PW von zum Beispiel 12 mm beträgt die Chipbreite DW 9,5 mm.For a package width PW of, for example, 12 mm the chip width DW 9.5 mm.
Folglich
ist der Bereich eines Speicherchips
Die
maximale Chipabmessung, welche in eine Packung bzw. ein Gehäuse TLBGA
In
der Ausführung,
die Speichervorrichtung
Die
Speicherchips
Mit
der Speichervorrichtung
Claims (42)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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DE102007002961A DE102007002961B4 (en) | 2007-01-19 | 2007-01-19 | Storage device and method for its production |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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DE102007002961A DE102007002961B4 (en) | 2007-01-19 | 2007-01-19 | Storage device and method for its production |
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DE102007002961A1 true DE102007002961A1 (en) | 2008-07-31 |
DE102007002961B4 DE102007002961B4 (en) | 2010-05-12 |
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Cited By (1)
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---|---|---|---|---|
CN108573972A (en) * | 2017-03-09 | 2018-09-25 | 三星电子株式会社 | Three-dimensional semiconductor device and forming method thereof |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
US5951304A (en) * | 1997-05-21 | 1999-09-14 | General Electric Company | Fanout interconnection pad arrays |
US6376904B1 (en) * | 1999-12-23 | 2002-04-23 | Rambus Inc. | Redistributed bond pads in stacked integrated circuit die package |
US6900528B2 (en) * | 2001-06-21 | 2005-05-31 | Micron Technology, Inc. | Stacked mass storage flash memory package |
-
2007
- 2007-01-19 DE DE102007002961A patent/DE102007002961B4/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5818114A (en) * | 1995-05-26 | 1998-10-06 | Hewlett-Packard Company | Radially staggered bond pad arrangements for integrated circuit pad circuitry |
US5951304A (en) * | 1997-05-21 | 1999-09-14 | General Electric Company | Fanout interconnection pad arrays |
US6376904B1 (en) * | 1999-12-23 | 2002-04-23 | Rambus Inc. | Redistributed bond pads in stacked integrated circuit die package |
US6900528B2 (en) * | 2001-06-21 | 2005-05-31 | Micron Technology, Inc. | Stacked mass storage flash memory package |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108573972A (en) * | 2017-03-09 | 2018-09-25 | 三星电子株式会社 | Three-dimensional semiconductor device and forming method thereof |
CN108573972B (en) * | 2017-03-09 | 2024-04-09 | 三星电子株式会社 | Three-dimensional semiconductor device and method of forming the same |
Also Published As
Publication number | Publication date |
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DE102007002961B4 (en) | 2010-05-12 |
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