DE102005035083B4 - Bond connection system, semiconductor device package and wire bonding method - Google Patents

Abstract

Connection system for a semiconductor device package with
A plurality of bond areas around a single chip area for connection to a respective one of a plurality of bond pads of a single chip to be mounted in the single die area, a first set of bonding areas along a first line segment for connection to adjacent bond pads of the bond area a single set (120a) of the bond areas is positioned along a second line segment (L2) for connection to a second plurality of adjacent bond pads of the single chip to be attached, the first and second line segments being discontinuous and spaced apart from the single chip area , and
A plurality of external terminals each connected to a corresponding one of the plurality of bonding areas,
characterized in that
- The first and the second line segment (L1, L2) at least partially overlap each other in the direction of the single chip area.

Description

The The invention relates to a connection system, the bonding areas for one Semiconductor device package includes, on an associated semiconductor device package and to a method of wire bonding such a package.

The Number of transistors on an integrated circuit chip can be formed with the trend to higher Integration continues. Accordingly, become integrated circuits are more sophisticated and require an increased number of Input and Output I / O Ports or lines. Therefore, the number of bond pads, which are placed at the edges of the individual chips, corresponding to, what restrictions for the Packing of chips means.

In In an integrated circuit die, the bond pads are common placed on the perimeter of the chip. The single chip is on a lead frame or package substrate, which in turn has a number of pins or lines for distributing the signals from the bond pad of the single chip to a circuit board containing the chip package is appropriate. The leadframe or package substrate include a number of wires, generally to the bond pads of the single chip are adjusted. The lines are over bonding wires with the Coupled bond pads.

1 is a plan view of a conventional bonding configuration. A single chip 1 includes a plurality of bond pads 3 along an edge of the single chip 1 , The bond pads 3 are with a plurality of corresponding lines 5 a lead frame over bonding wires 7 in bonding areas 9 coupled to the lead frame. The bond areas 9 Additionally, they are commonly referred to as "inner lead pads" for lead frames or "bond fingers" for package substrate configurations. The wires 5 are larger in size than the corresponding bond pads 3 , The angle under which the bonding wire 7 relative to an axis perpendicular to the edge of the single chip 1 is and through the appropriate contact point 3 runs, is referred to as "bond angle". Bond wires 7 that with the bond pads 3 are coupled in a central region of the edge of the chip, are spaced apart by a distance S2, while bonding wires 7 that with the bond pads 3 are coupled in a corner region of the edge of the chip, spaced apart by a distance S1. The distance S1 between the bonding wires in the corner regions of the single chip is due to the increased bonding angle of the wires in the corner regions, due to the larger dimension of the leads 5 less than the distance S2 between the bonding wires in the central area of the single chip. With the reduced distance S1 between wires in the corner regions, there is an increased likelihood of a short between bonding wires in the corner regions during the last stages of the chip bag, a costly time to introduce defects in the manufacturing process, since the manufacture of the chip is almost completed at this time ,

To avoid a wire-to-wire short in the corner areas, the distance between the bond pads becomes 3 made larger from the central areas of the single chip to the corner areas. 2 FIG. 12 is a plan view of a conventional bond configuration in which the pitch or "pitch" between bond pads 3 is enlarged in this way. This magnification of the pitch is generally referred to as the "corner rule". Using the corner rule turns off 2 it can be seen that the pitch P1 between the bond pads 3 in the central area smaller than the pitch P2 between the bond pads 3 in an intermediate region, which in turn is smaller than the pitch P3 between the bond pads 3 in the corner area is (P1 <P2 <P3). The corner rule applies to bonding pads along both the vertical and horizontal edges of the die and in all quadrants of the die. By increasing the pitch between bond pads in this way, the increase in the bond angle between the chip bond pads becomes 3 and the line bonding areas 9 toned down or eliminated. Examples of the use of the corner rule for chip-bond configurations are in the patent specification US 5,923,092 A , the contents of which are incorporated herein by reference.

A Bond configuration to which the corner rule applies results however, in an enlarged chip size, if the number of bond pads is to be maintained. This is in contrast to design integration and in contrast to manufacturing throughput, where an optimal "net single chip" number or number of Wished chips per wafer is. Accordingly, increase the production costs proportional.

In one in the patent US 5,952,710 A inner connecting sections of a conductor frame serving for chip contacting are provided as bonding regions arranged around a single chip region, which are connected via bonding wires to corresponding chip connections and specially designed such that a bonding wire extending in a corner region lies in the corner region of the chip de connection point with the associated inner conductor portion of the lead frame connects, shorter than an adjacent bonding wire. This is realized in that the corner-side inner conductor section extends slightly further inward in the direction of the chip than the adjacent inner conductor section. Concretely, the respective inner conductor portion protrudes by a length which is of the order of the mean distance of adjacent inner conductor portions.

In the patent EP 0 015 111 B1 For example, as a connection system for a semiconductor device package, there is disclosed a lead frame in which the leads form a pattern radiating from a chip mounting area. In this case, the leads extend from the square chip mounting region with an inner portion initially perpendicularly away from each of the four sides of the mounting region to the outside, and then bend over into a middle section, which in turn merges into an outer portion kinkend. In the outer portion of the leads are parallel to their associated inner portion, but they are widened. The bending angle at the transition from the middle to the outer portion is opposite to the bending angle at the transition from the inner to the middle conductor portion, wherein the bending angle for the leads in the central side regions is smaller and increases towards the corner regions of the chip mounting surface. The inflection points of the transition from the inner to the middle conductor section lie on a square that is rotated by 45 ° to that of the chip mounting surface, while the inflection points of the transition from the middle to the outer conductor section lie on an even larger square oriented the same to that of the chip mounting surface. In this way, chips of different sizes should be able to be mounted with the same leadframe structure.

In the published patent application DE 197 04 343 A1 discloses a leadframe interconnection system for a semiconductor device package in which individual conductors of the leadframe simultaneously serve as holding elements for mechanically holding the semiconductor chip.

The Laid-open publication US 2002/0140083 A1 discloses a connection system for the encapsulated integration of a semiconductor chip on a multilayer printed circuit board, the chip connections via bonding wires with Contact structures of the circuit board are connected, which also have vias may include.

In the aforementioned patent US 5,923,092 A discloses a leadframe structure, in which the leads lie with their one chip mounting surface facing inner ends on an octagon by the corresponding with the four corners of the square chip mounting area corner regions of the inner boundary of the lead frame structure are flattened there to the distance to the chip-side pads something To shorten.

The Laid-open JP 62-185331 A discloses a connection system for one Semiconductor device package in which one in an opening of the Pack received chip a bond pad configuration at the peripheral bond pads between every two Chipeckbereichen are arranged along a circular arc, while with a corresponding corner region corresponding bond pads are arranged in a row opposite to said circular arc for Chip corner is offset. In the same way are on a the chip opening surrounding packing area bonding areas, extending between corner areas the opening are located along a respective arc while using the respective corner region corresponding bond areas in one Row are arranged, in contrast, in the chip away direction is offset. This should be a respect the chip center as possible of radial Course of all the bond pads connecting to the bond areas Bond wires be achieved.

Of the Invention is the technical problem of providing a Connection system, an associated Semiconductor device package and an associated Drahtbondverfahrens based, which are capable, at least in part, of the difficulties mentioned above to avoid the prior art and by the particular the bond angles of the bonding wires within acceptable limits without increasing the size of the single-chip to cause.

The Invention solves this problem by providing a connection system with the features of claim 1, 2 or 5, a semiconductor device package with the features of claim 22 and a wire bonding method with the features of claim 27.

advantageous embodiments The invention are specified in the subclaims.

In accordance with the invention, leadframes and package substrates include leads, lead bonds, or bonding fingers that may be arranged to accept even pitch bond pad configurations even in the corner regions of the die. In this way, the occurrence of short circuits between adjacent bonding wires can be reduced or eliminated, and the components The net single chip number during production can be increased.

Advantageous, Embodiments described below of the invention and the conventional ones described above for their better understanding embodiments are shown in the drawings, in which:

1 a plan view of a conventional bonding configuration between a single chip and a lead frame,

2 a plan view of a conventional bonding configuration in which the distance or the "pitch" is increased between bond pads according to the corner rule,

3 a plan view of a connection board or a "lead frame" that is configured according to the invention,

4 an enlarged view of the first quadrant of the leadframe of 3 according to the invention,

5 an enlarged view of a bonding tip of a first line of a second group of lines of the leadframe of 4 according to the invention,

6 a plan view of the bonded to a single chip leadframe of 4 according to the invention,

7 an enlarged view of the first quadrant of a first alternative embodiment of a lead frame according to the invention,

8th an enlarged view of the first quadrant of a second alternative embodiment of a lead frame according to the invention,

9 an enlarged plan view of the bonded to a single chip leadframe of 8th according to the invention,

10 a diagram of bonding angles for bonding wires of a first group of lines and bonding wires of the second group of lines for the lead frame of 6 according to the invention,

11 a perspective view of a quad-flat-pack (QFP) having a first group of lines in a central region of the chip edge and a second group of lines in a corner region according to the invention,

12 a cross-sectional view of the QFP of 11 along a section line AA 'of 6 .

13 a cross-sectional view of a QFP, the in 8th illustrated embodiment of the invention, along the section line AA 'according to the invention,

14 a top view of a quad-flat non-lead package (QFN) according to the invention, which has a first group of lines in a central region of the chip edge and a second group of lines in a corner region according to the invention,

15 a cross-sectional view of the QFN of 14 along a section line BB of 14 .

16 a cross-sectional view of a ball grid array (BGA) package, the in 8th illustrated embodiment of the invention, along the section line A-A ',

17 a top view of a substrate of a substrate-based ball grid array (BGA) package according to the invention,

18 an enlarged view of the first quadrant of the substrate and bonding fingers of the BGA of 17 according to the invention,

19 a cross-sectional view of the substrate and bonding fingers of the BGA the 17 and 18 according to the invention,

20 a plan view of the first quadrant of the substrate bonded to a single chip and bonding fingers of the BGA of 17 to 19 according to the invention,

21 a diagram of the bonding angle for bonding wires of the first group of bonding fingers and bonding wires of the second group of bonding fingers for the substrate of the BGA of 20 according to the invention,

22 a cross-sectional view of a portion of the finished package of the bonded BGA of 20 according to the invention,

23 12 is a cross-sectional view of a portion of an alternative embodiment of a completed package of a bonded BGA according to the invention;

24A . 24B and 24C Bottom views of various BGA packages according to the invention.

3 is a plan view of a connection board or a "lead frame" 100 configured in accordance with the present invention. The ladder frame 100 of the present invention Hold a plurality of wires 102 , each one from an inner end 104 at an inner portion of the lead frame to an outer end 106 extend at an outer portion of the lead frame. The wires 102 of the ladder frame 100 include a conductive metal or a conductive alloy such as copper, aluminum or gold or other conductive materials or alloys. The inner ends 104 the leads of the lead frame 100 surround an area 130 in which a single chip pad or chip pad on the lead frame 100 is to be attached.

A plurality of connecting webs 132 extends from four corners of the leadframe. Inner ends 108 the connecting webs 132 extend into the single chip pad area 130 to carry a single chip pad or plate on which the single chip is mounted. The single chip contact area 130 has a center c. Four quadrants surround center c, with each quadrant containing two octanes a.

The example shown includes 256 lines 102 which form a low-profile 256-LPFP. Other types of leadframes with different lead numbers and configurations are equally applicable to the principles of the invention.

4 is an enlarged view of the first quadrant of the lead frame 100 from 3 , From this view, it can be seen that each octane a of the lines 102 in a first group 110 and a second group 120 is divided. The first group 110 of wires 102 provides bond pads of the single chip pad in the single chip pad area 130 which lie in a central area of the edge of the single chip. The second group 120 of wires 102 provides bond pads of the single chip pad in the single chip pad area 130 that lie in a corner area of the edge of the single chip. The term "supply" as used herein refers to conduits 102 (or bond finger 310 the following with reference to the 17 to 23 discussed, substrate-based embodiment) configured to be bonded by bonding wires to respective bond pads of a single die that are in the single-chip pad region 130 is appropriate.

In 4 includes the first group 110 of wires 102 cables 110 (1) , ..., 110 (s) , the outer ends 106 include, which terminate along the outer periphery of the lead frame. Inner ends 104 The first group of lines terminate at an inner area of the lead frame along a first line segment L1. The second group 120 of wires 102 includes cables 120 (1) , ..., 120 (m) , the outer ends 106 include, which terminate along the outer periphery of the lead frame. Inner ends 104 The second group of leads terminate at an inner region of the leadframe. The inner ends 104 of the second group of lines terminate along a second line segment L2. The second line segment L2 is spaced from the first line segment L1, for example in a position closer to the single chip pad region 130 lies as the first line segment L1.

The Line segments L1 and L2 are referred to in the art as "leader lines" and may be line segments include along straight lines, or may be optional include a series of line segments that are under different Angles go. Alternatively you can the guidelines along a segment of a curve, a sinusoidal or "spline" curve, or an arc, like a parabolic, elliptical or circular Bow lie. The term "leader" as used herein is, includes these and various other types of curves and Line segments.

According to the invention, the first line segment or the first guide line of bond areas of the line 102 independent of the second line segment or the second guide line L2. For example, the second guide line L2, which is connected to the second group of lines 120 (or bond fingers 320 from 17 below), which supplies bond pads in a corner region of the die, are at a position closer to the first guide line L1 than a first group of leads 110 (or bond fingers 310 from 17 ), which supplies bond pads in a central region of the edge of the die as in 4 shown.

The first and second leaders are also discontinuous in the sense that they do not intersect at their endpoints. The outermost line 110 (s) the first group 110 of leads ends, for example, in an inner region of the lead frame at the inner end 104 along the line segment of the guideline L1. In addition, the innermost line ends 120 (1) the second group 120 of leads at an inner portion of the lead frame at the inner end 104 along the line segment of the guide line L2. The outermost line 110 (1) the first group of wires 110 and the innermost line 120 (1) the second group of lines 120 provide adjacent bond pads in the single chip area 130 attached individual chips (for example bonding pads of the central region or the corner region), but the positions of the guide lines L1, L2 do not intersect yet in the Bondberei at the tips of these adjacent lines. Thus, the first and second guide lines L1, L2 are discontinuous.

The wires 102 go through a number of lateral deflections or bends 105 between the inner ends 104 and the outer ends 106 , The bends 105 or breakpoints serve to define the contact area between the conductive lead frame 100 and to increase the molding compound that may be cast around the leads to form the body of the package after the die pad in the die pad region 130 through the bonding wires to the lead frame 100 is bonded. The bends 105 also serve to bond the bond areas at the inner ends 104 the lines 102 to be positioned in a suitable orientation such that a longitudinal axis of the bonding region points substantially in the direction of a corresponding bond pad on the single chip in order to increase the contact region of the bonding wire between the corresponding bond pad of the single chip and the bond region of the lead.

Lines of the second group 120 ends along a guide line segment L2 which is positioned closer to the edge of the single chip than the first group of leads 110 that end along the line L1. In addition, at least a part of the second guide line segment L2 is positioned between the first guide line segment L1 and the bond pads of the single chip. In this way, the bond regions of the second group of leads are positioned closer to the bond pads in the corner regions of the die, and the bond angle in the corner regions of the die is reduced to an acceptable level. By effectively redefining the bond angle for the second set of wires 120 Therefore, the bond angle for each individual line is maintained at a value that is less than a maximum acceptable bond angle. In one example, a bond angle of less than about 30 degrees to 35 degrees is considered to be an acceptable maximum bond angle. This allows the chip to be bonded with high reliability without the need for applying the corner rule and therefore without the need for an increase in chip size to accommodate a gradual increase in pitch between adjacent bond pads. This leads to reduced manufacturing costs, an increase in the number of chips produced per wafer or "net single chips" and an increased production throughput.

An orientation of the bond area of the line 102 in the direction of the corresponding bond pad provides more efficient bonding. The bond area or bond area of a line is commonly referred to as a "bonding tip" in the case of a lead frame and as a "bonding finger" in the case of a packaging substrate based technology, such as those used in a ball grid array (BGA) package is used. An increase in efficiency is realized particularly in the case where ultrasonic bonding is used. In this case, orienting the longitudinal axis of the wire bonding tip substantially in line with the bond pad allows for optimal utilization of the ultrasonic energy for bonding, resulting in faster and more reliable bonding. In addition, in the case of a lead frame, the lead is more robust in the longitudinal direction than in the transverse direction, and therefore, orientation of the longitudinal axis of the bond tip of the lead in this manner gives the lead a stronger base structure for the bonding procedure.

5 is an enlarged view of a bonding tip 120a the line 120 (1) of the ladder frame 100 from 4 , From this view it can be seen that the line 120 (1) includes a bend at a point P1, the line making a bend at that point such that the lead 120 (1) with a first segment 123 away from the corner area of the single chip and toward the central area of the single chip. The bend at the point P1 is necessary to the first line 120 (1) the second group 120 of leads laterally around the bond tip 110a the last line 110 (s) the first group 110 from leads which lie along the line segment L1, around the bonding tip 120a the line 120 (1) between the single chip area and the bonding tips 110a the first group 110 of lines to position. Another bend in the pipe 120 (1) is at the point P2, where an additional second segment 125 the line 120 (1) The administration 120 (1) new in a direction to the corresponding bond pad of the single chip in the single chip area 130 oriented. Thus, the second segment 125 and the bond area of the lead located on the segment each have a longitudinal axis substantially oriented toward a respective bond pad on the single chip, which is referred to as an "opposing" configuration and leads to the advantages set forth above.

The remaining bond tips 120a the second group 120 of wires 120 (1) ... 120 (m) include similar first and second bending points P1, P2, resulting in bonding tips oriented in an "opposite" configuration with corresponding bond pads on the single chip. In the example of 4 For example, the angles α of the bending points P1, P2 in the leads supplying the central portion of the single chip are more pronounced than in leads supplying the corner portion of the single chip. When bond tips 110a the eu First lines, for example, the lines 110 (n-2) . 110 (n-1) . 110 (s) , the first group 110 begin to result in a bond angle approaching the critical bond angle, thus extending the next adjacent line, which is the first line 120 (1) the second group 120 of leads is, toward the center of the single chip, to the next set of leads and associated bond tips 120a , which are along the line segment L2, to reposition so that the bonding angle for those lines 120 set and effective to a suitable bonding angle for the set of the second group or lines 120 is redefined. This leads to a discontinuity between the bonding angle of the last line 110 (s) the first group of wires 110 (which is at or near the maximum allowed bond angle) and the bond angle of the first line 120 (1) the second group of lines 120 (which may be at or near a bond angle of zero, or is actually at an angle of opposite sign to that of the last line 110 (s) the first group 110 is). Thus, there is a discontinuity between the bonding angles of the adjacent lines 110 (s) and 120 (1) on the same side of the leadframe and its associated adjacent bond pads thereof in the single chip area 130 attached single chips.

6 is a plan view of the lead frame 100 from 4 , the bond pads of a single chip 140 is bonded. The single chip 140 and wires 110 . 120 are using conductive bonding wires 170a . 170b Bonded, such as gold or copper wire. It can be seen that the bonding tips 110a the first group 110 of lines lying along the line segment L1 and that the bonding wire 170a the first line 110 (1) the first group has a bond angle of about 0 degrees while the wire 170a the outermost line 110 (s) the first group has a bond angle approaching the maximum acceptable bond angle, for example, about 30 degrees. It can also be seen that the bonding tips 110b the second group 120 of wires lying along the line L2 and that the wire 170b the first line 120 (1) The second group has a bond angle of about 0 degrees and, in this example, actually has a negative bond angle of about -10 degrees, while the wire 170b the outermost line 120 (m) the second group has a bond angle which is below the maximum acceptable bond angle of 30 degrees. Thus, there is a discontinuity between the bond angles of adjacent lines 110 (s) the first group, which has a bond angle of about 30 degrees, and the line 120 (1) the second group, which has a bonding angle of about -10 degrees.

To achieve wire bonding in this configuration, the one for bonding the first wire group is used 110 used wires 170a a higher loop height than that for bonding the second line group 120 used wires 170b intended. This prevents a short circuit of the wires 170a . 170b for those lines of the first and the second group 110 . 120 that overlap.

In this way, all lines of the first group 110 and the second group 120 Bonding points which are positioned relative to their associated bonding pads so that they are within the maximum acceptable bond angle of the packing / single chip combination. The need to apply the corner rule to the single chip is thus eliminated, and maximum use of bond pads on the single chip can be realized, thereby providing a smaller area for the single chip. At the same time, the leads are also oriented such that the longitudinal axis of the segment on which the bond area is placed on the lead faces the associated bond pad in an "opposite" configuration, resulting in a stronger wire-line bond such as described above.

7 Figure 3 is an enlarged view of the first quadrant of a first alternative embodiment of a leadframe according to the invention. In this embodiment, the lead frame is the same as that of FIG 4 configured. The single chip contact point 130 ' however, in this embodiment is circular rather than square or rectangular. Such a circular or elliptical single chip pad is advantageous in certain applications for efficient heat dissipation of a single die attached thereto. The bond configurations of the present invention are equally applicable to these and other single chip pad shapes and orientations.

8th Figure 3 is an enlarged view of the first quadrant of a second alternative embodiment of a leadframe 200 according to the invention. In this embodiment, no single-chip pad is used, and therefore are not connecting webs 132 necessary. Instead, it is provided in this embodiment that the second group of lines 220 along elongated segments 220a in the single chip area 235 over their respective bond areas 220c extends, which lie along the line segment L2. The elongated segments 220a extend into the single chip area 235 and act as a vertical support for the single chip 231 , The single chip 231 is thus directly on the tops of the elongated segments 220a attached, and the bond contact points of the single chip 231 are to the bond areas 210a . 220c the first and the second group of lines 210 . 220 in the same manner as that described above with reference to 6 described wired. Again, the first guide line L1 and the second guide line L2 are discontinuous in this example.

9 is an enlarged view of the lead frame 200 from 8th that is attached to a single chip 240 is bonded. The single chip 240 and the wires 210 . 220 are using conductive bonding wires 270a . 270b Bonded, such as gold or copper wire. It can be seen that this embodiment has the same advantages in terms of a reduced bond angle and in terms of an opposite orientation of the bonding tips 210a . 220c offers, as in the embodiment of 6 the case is. One difference is that the bond tips 220c for the second group of wires 220 in the embodiment of 8th and 9 at an intermediate point of the lines 220 are positioned when the lines 220 further into the single chip area 235 extend into it, unlike the bond tips 120a the embodiment of the 3 to 5 in which the tips 120a at or near an inner end 104 the lines 120 are positioned. In addition, the single chip 240 in the present embodiment directly on the second group of lines 220 of the ladder frame 200 appropriate. Thus, when an epoxy or other fluid packing material compound is poured around the resulting structure, a stronger bond is provided directly between the single chip and the lead frame. This reduces the susceptibility of the package to temperature, mechanical stress and moisture that would otherwise result from the added component of the single chip pad.

10 is a graphical representation of bonding angles for bonding wires 170a the first group of wires 110 and for bonding wires 170b the second group of lines 120 for the ladder frame of 6 or 8th according to the present invention. The graphic representation 1 of 10 represents the incremental increase in bond angle from an angle close to zero degrees for the first lead bonding 110 (1) the first steering group 110 and an incremental progression to an angle at or below the maximum acceptable bond angle MAX for the last line 110 (s) the first steering group 110 dar. The next adjacent line, namely the first line 120 (1) the second steering group 120 (see graph 2), has a bond angle that is well within the acceptable range and actually has a bond angle one to that of the line 110 (s) has opposite sign. From there, take the bond angle of the second group of wires 120 incrementally to a positive value, and the last line 120 (m) the second group of lines 120 has a bond angle well within the maximum acceptable value MAX. The graphical representation of bond angles thus shows a discontinuity 127 between the bond angles of the leads of the first group (see Graph 1) and the bond angles of the adjacent leads of the second group (see Graph 2).

11 Figure 4 is a perspective view of a quad-flat pack (QFP) including a first group 1G of leads 110b and a second group 2G of lines 120b according to the present invention. This QFP is the same as in 6 illustrated embodiment of the present invention. 12 is a cross-sectional view of the QFP of 11 along a section line AA 'of 6 , The QFP includes a casting compound 180 which the single chip contact point 130 , the single chip 140 , the first and the second group of wires 110 . 120 associated bonding areas or tips 110a . 120a and bonding wires 170a . 170b surrounds and encloses. The single chip 140 is about an adhesive 160 with the single chip contact point 130 coupled. This view also shows that the first group 170a of bonding wires has a greater loop height LH1 than the loop height LH2 of the second group of bonding wires 170b has a short circuit between the wires 170a . 170b to avoid.

13 FIG. 12 is a cross-sectional view of a QFP similar to that in FIG 8th illustrated embodiment of the invention along a section line AA 'corresponds. The QFP includes a casting compound 280 that the single chip 240 , the first and the second group of wires 210 . 220 , associated bond areas 210a . 220c and bonding wires 270a . 270b surrounds and encloses. In this configuration, the wires include 220 the second group extension segments 220a that are under the single chip 240 extend as described above. The single chip 240 is right on the extension segments 220a the second group of lines 220 over an adhesive 260 attached, and thus no single chip pad is necessary in this embodiment. Again, the first group points 270a of bonding wires in this embodiment has a larger loop height LH2 than the loop height LH1 of the second group of bonding wires 270b on to make a short circuit between the wires 270a . 270b to avoid.

14 Figure 12 is a plan view of a quad-flat non-lead package (QFN) containing a first group 1G of leads 110b with associated bond pads in the central areas of the Single chips and a second group of 2G cables 120b having associated bonding pads in the corner regions of the single chip according to the present invention. This QFP is the same as in 6 illustrated embodiment of the present invention. 15 is a cross-sectional view of the QFP of 14 along a section line BB of 14 , The QFP includes a casting compound 180 which the single chip contact point 130 , the single chip 140 , the first and the second group of wires 110 . 120 , associated bonding areas or tips 110a . 120a and bonding wires 170a . 170b surrounds and encloses. The single chip 140 is with the single chip 130 over an adhesive 160 coupled. The wires 110 . 120 This configuration is in the form of metal contacts that terminate at the periphery of the package. Again, the first group points 170a of bonding wires has a greater loop height LH1 than the loop height LH2 of the second group of bonding wires 170b on to make a short circuit between the wires 170a . 170b to avoid. In addition, a recess G allows in a bottom of the single chip pad 130 and the line connections 110 . 120 is formed, that the casting compound 180 the single-chip pad and the lead terminals 110 . 120 more tightly, anchoring the components in the package with increased stability and reliability.

16 is a cross-sectional view of a ball grid array (BGA) package similar to that in FIG 8th illustrated lead frame embodiment of the invention along a section line AA 'corresponds. The BGA includes a casting compound 280 that the single chip 240 , the first and the second group of wires 210 . 220 and bonding wires 270a . 270b surrounds and encloses. In this configuration, the lines include the second group 220 extension segments 220a that are under the single chip 240 extend. The single chip 240 is right on the extension segments 220a the second group of lines 220 over an adhesive 260 attached, and thus no single chip contact point is necessary. Again, the first group points 270a of bond wires in this embodiment has a higher loop height LH2 than the loop height LH1 of the second group of bond wires 270b on to make a short circuit between the wires 270a . 270b to avoid. Exposed openings 285 at the outer end of lines 210b provide direct access to the lines 210b , sphere structures 290 are in the exposed openings 285 placed to provide external connections for the package.

17 Figure 10 is a plan view of a substrate of a substrate-based ball grid array (BGA) package according to the invention. The substrate 300 includes a plurality of layers of interconnects or vias, and includes a circuit board, a ceramic substrate, a polyimide film, a semiconductor substrate such as a silicon substrate, and the like. The substrate includes a central single chip pad area 330 and a plurality of bonding elements 310a . 320a , which are referred to in this technology as a "bond finger". A first group of bond fingers 310a provides bond pads one in the single chip pad area 330 attached chips, which are located in a central region of the edge of the single chip, in the same manner as the first group of lines 110 this in the above-described ladder frame of 4 reached. A second group of bond fingers 320b provides bond pads one in the single chip pad area 330 attached individual chips located in corner regions of the edge of the single chip, in the same manner as the second group of lines 120 this in the above-described surrounded leadframe of 4 reached. The bond fingers 310a . 310b become external terminals or leads of the package through the multilayer interconnects or vias of the substrate 300 guided.

18 FIG. 12 is an enlarged view of the first quadrant of the substrate of the BGA of FIG 17 according to the invention. In this view, point c is the center of the single chip pad 330 , The substrate or interconnect board 300 includes a plurality of first groups of structured circuits IG, the vias 310 (1) , ..., 310 (n) and associated bond fingers 310a (1) , ..., 310a (n) include, as well as a plurality of second groups of structured circuits 2G, the vias 320 (1) , ..., 320 (m) and associated bond fingers 320a (1) , ..., 320a (m) include. In this embodiment, each octand around center c includes both first and second groups 1G, 2G of bond fingers 310a . 320a , In the same way as in the ladder frame embodiments described above, the first group supplies 1G of bonding fingers 310 Bond pads of the single chip pad in the single chip pad region 330 which lies in a central area of the edge of the single chip. The second group 2G of bond fingers 320a provides bond pads of the single chip pad in the single chip pad area 330 which lies in a corner area of the edge of the single chip. The term "provide" as used herein refers to bond fingers 310a configured to be bonded by bonding wires to respective bond pads of a single chip that are in the single chip pad region 330 is appropriate.

19 FIG. 12 is a cross-sectional view of the substrate and bonding fingers of the BGA of FIG 17 and 18 according to the invention. As in 19 As shown, each of the first group is 1G of bond fingers 310a with connections 310c connected to the pack, the provide external interconnects for the package. Similarly, each of the second group is 2G of bond fingers 320a with connections 320c associated with the package providing external interconnections for the package. Interlayer vias 310b . 320b (collectively referred to as vias V1 of 19 shown) become the interconnection of the bonding fingers 310a . 320a and the associated connections 310c . 320c used. The interlayer vias are in the substrate 300 the connection board formed. A passivation layer 335 is on surfaces of the substrate 300 designed to protect underlying circuits and components. A via V2 may optionally be included and passes directly through the substrate 300 as a conduit for dissipating heat from that on the single chip pad 330 to be attached single chip. A performance ring and a mass ring 327 are also included to provide power and ground voltages for the single chip.

To 18 returning, are the bond fingers 310a of the first group 1G are positioned along a first guide line GL1. The bond fingers 320a of the second group 2G are positioned along a second guide line GL2. The second guide line GL2 is spaced from the first guide line GL1, for example, in a position closer to the single-chip pad area 330 lies as the first guideline GL1. In this example, the guide lines GL1, GL2 are in the form of an arc segment that is elliptical, parabolic, or circular. However, other configurations of leader shapes are equally applicable to the invention. In this example, the first guide line GL1 and the second guide line GL2 are discontinuous since they are at the location of the bond areas 310 (m) and 320a (1) do not cut, the adjacent bond pads one in the single chip area 330 supply the individual chips used.

The bond fingers 310a . 320a are formed by patterning and / or etching the substrate so that their longitudinal axes are oriented in the direction of the associated bond pads of the single chip. This results in more efficient and reliable bonding, especially in the case of ultrasonic bonding techniques as described above.

20 FIG. 12 is a plan view of the first quadrant of the substrate and bonding fingers of the BGA bonded to a single chip. FIG 17 to 19 according to the invention. The single chip 340 and the bond fingers 310a . 320a are using conductive bonding wires 370a . 370b Bonded, such as gold or copper wire. It can be seen that the bond fingers 310a of the first group 1G of lines lie along the guide line GL1 and that the bonding wire 370a the first contact 310 (1) the first group 1G has a bonding angle of about 0 degrees, while the wire 370a the outermost contact 310 (n) the first group 1G has a bond angle approaching the maximum acceptable bond angle, for example, about 30 degrees. It can also be seen that the bond fingers 320 (a) of the second group 2G of lines lie along the guide line GL2 and that the bonding wire 370b the first contact 320 (1) The second group 2G has a bond angle of about 0 degrees and, in this example, actually has a negative bond angle of about -10 degrees during the bonding wire 370b the outermost line 320 (m) the second group 2G has a bond angle which is below the maximum acceptable bond angle of 30 degrees. Thus, there is a discontinuity between the bonding angle of the last via / bonding finger 310 (n) of the first group 1G, which has a bonding angle of about 30 degrees, and the first via / bonding finger 320 (1) the second group, which has a bond angle of about -10 degrees.

As with the leadframe embodiments described above, to achieve a wirebond connection in the present substrate-based configuration, that for bonding the first via group is caused 310 used wires 370a have a greater loop height than the wires 370b for bonding the second via group 320 be used. This prevents a short circuit of the wires 370a . 370b for those lines of the first and second groups 1G, 2G that overlap.

On this way all lines of the first group 1G and the second group 2G bond fingers relative to their associated bond pads are positioned so that they are within the maximum acceptable Bond angles of the pack / single chip combination are. The need to apply the corner rule to the single chip is thus eliminated, and maximum use of bond pads on the single chip be realized, and thus can be effected that the single chip a smaller area having. At the same time, the lines are also oriented such that the longitudinal axis of the segment on which the bond area is placed on the line is, in the direction of the associated Bond contact point in a "each other opposite "configuration, what a stronger one Wireline bond leads, as described above.

21 FIG. 15 is a graph of bonding angles for bonding wires of the first group of bonding fingers and bonding wires of the second group of bonding fingers for the substrate of the BGA of FIG 20 according to the invention. A characteristic 1 of 21 represents the incremental increase in bond angle from an angle of nearly zero degrees to the bonding of the first bond fingers 310a (1) of the first group 1G with incremental progression to an angle at or below the maximum acceptable bond angle MAX for the last bond finger 310a (n) The next adjacent bond finger is the bond finger which is to be attached to the next adjacent bond pad in the row of bond pads of the single chip, specifically the first bond finger 320a (1) of the second group 2G (see characteristic 2) has a bonding angle which is well within the acceptable range, and in fact has a bonding angle which is of a sign that of the bonding finger 310a (n) is opposite. From there, the bond angles of the second group of bond fingers 2G incrementally decrease to a positive value, and the last bond finger 320a (m) The second group of lines 2G has a bond angle that is well within the maximum acceptable value MAX. The graphical representation of bond angles thus shows a discontinuity 127 between the bond angles of the lines of the first group (see characteristic curve 1) and the bond angles of the adjacent lines of the second group (see characteristic curve 2).

22 FIG. 12 is a cross-sectional view of the completed package of the bonded BGA of FIG 20 according to the invention. The BGA includes a casting compound 380 attached to a top of the substrate 300 from 19 attached to which the single chip 340 attached by the bonding wires 370a . 370b to the bond fingers 320a . 320b the first and the second group 1G, 2G is bonded. The first group 370a of bonding wires has a larger loop height LH2 than the loop height LH1 of the second group of bonding wires 370b on to make a short circuit between the wires 370a . 370b to avoid. sphere structures 390 are at the exposed terminals or ball pads 310c . 320c attached to provide external connections for the package.

23 Figure 12 is a cross-sectional view of an alternative embodiment of a completed package of a bonded BGA according to the invention. In this embodiment, a large heat sink 392 on a bottom of the single chip 340 attached, using a thermally conductive adhesive 396 bonded to the heat sink. The bond substrate or circuit board 300 is in the same way at the heat valley 392 attached and surrounds the single chip 340 as described above. The first and second bond fingers 310a . 320a of the substrate 300 are by appropriate bonding wires 370a . 370b in the manner described above at bond pads of the single chip 340 bonded. The BGA includes a casting compound 380 ' attached to a surface of the substrate 300 opposite to the heat sink 392 attached to which the single chip 340 attached by the bonding wires 370a . 370b to the bond fingers 320a . 320b the first and the second group 1G, 2G is bonded. The first group 370a of bonding wires has a larger loop height LH2 than the loop height LH1 of the second group of bonding wires 370b on to make a short circuit between the wires 370a . 370b to avoid. sphere structures 390 are at the exposed terminals or ball pads 310c . 320c attached to provide external connections for the package.

The 24A . 24B and 24C are bottom views of various BGA packages according to the invention. Each embodiment includes a passivation layer 335 through which a plurality of balls 390 attached, which consist for example of solder or gold material. The balls 390 are formed according to conventional procedures involving the conventional mounting method, the reflow method, the screen printing method or the photolithography method. In 24A are the balls 390 relatively small and include several lines along the circumference and several lines in a central area of the chip package. In 24B are the balls 390 relatively large and cover the entire bottom of the pack. In 24C are the balls 390 relatively small and include a number of rows along the circumference and a limited number of rows in a central area of the chip package.

A typical package process for a lead frame based package, such as that described above with reference to FIG 11 described QFP package, includes the well-known steps of taping, sawing, single chip attachment, wire bonding, casting, conductor trimming, wire plating and line formation. A typical package process for a substrate-based package, such as that described above with reference to FIG 22 described BGA package, includes the well-known steps taping, sawing, single chip attachment, wire bonding, casting, ball attachment and ball singulation.

During the step of wire bonding according to the present invention, a high-speed wire-stitching machine is used. A capillary of gold wire is attached to the target bond pad by a welding process wherein a molten ball of material is applied from a first end of the wire to the bond pad and the wire is formed or looped with it to form the bond region of the lead of the lead Lead frame or the bonding finger of the conductive path on the Substrate extends. The second end of the wire is rapidly bonded to the bond area by a stitchbonded connection using, for example, ultrasonic bonding techniques. After bonding, the wire is "pinched off" or broken off and the next bonding procedure begins.

For example, during the casting step, in the case of a leadframe-based package, an EMC bond is introduced into the component area through a high-pressure pouring port, for example, 2 tons / mm ² . As the material fills the mold, air is blown through corners of the mold. After curing the mold, leads outside the leadframe are trimmed, for example, using a dambar process. The external leads are then plated, for example using SnPb or SnAgCu materials. During the formation process, the exposed, trimmed, and plated leads are die-stamped into a suitable shape for soldering to a printed circuit board or substrate.

Claims (28)

A connection system for a semiconductor device package comprising - a plurality of bond areas around a single chip area ( 130 ) for connection to a respective one of a plurality of bond pads of a single chip to be mounted in the single chip area, a first set ( 110a ) of the bond areas is positioned along a first line segment (L1) for connection to adjacent bond pads of the single chip to be attached, and a second set ( 120a ) of the bond regions is positioned along a second line segment (L2) for connection to a second plurality of adjacent bond pads of the die to be attached, the first and second line segments being discontinuous and spaced apart from the die region, and a plurality of external leads each connected to a corresponding one of the plurality of bond areas, characterized in that - the first and second line segments (L1, L2) overlap each other at least partially in the direction of the single chip area. A connection system for a semiconductor device package comprising - a plurality of bond areas around a single chip area ( 130 ) for connection to a respective one of a plurality of bond pads of a single chip to be mounted in the single chip area, a first set ( 110a ) of the bond areas is positioned along a first line segment (L1) for connection to a first plurality of adjacent bond pads of the single chip to be attached, and a second set ( 120a ) of the bonding regions is positioned along a second line segment (L2) for connection to a second plurality of adjacent bond pads of the single chip to be attached, and a plurality of external leads each connected to a corresponding one of the plurality of bond regions; Bond angle between each one of the corresponding first plurality of adjacent bond pads and the first set of bond regions is incremental and - wherein a change in the bond angle between each one of the corresponding second plurality of adjacent bond pads and the second set of bonding regions is incremental, characterized in that a change in the bond angle between a last of the corresponding first plurality of adjacent bond pads and the first set of bond regions and a first of the corresponding second plurality of adjacent bond pads and d a second set of bonding areas is discontinuous relative to the incremental change by having its direction of change opposite to the direction of change of the incremental change in bond angle between penultimate and last of the first plurality of adjacent bond pads and the associated one of the first set of bond areas and opposite to the direction of change of the incremental change in bond angle between the first and second ones of the second plurality of adjacent bond pads and the associated one of the second set of bond regions. Connection system according to claim 1 or 2, characterized characterized in that the bond areas bond peaks of a lead frame include and further include conductive lines, that between each bond area and a corresponding one of the plurality from external connections are looped. Connection system according to claim 3, characterized in that that at least one of the conductive Leads coupled to the second set of bond areas are, includes a first bend point of the line in Direction of the first set of bond areas redirects. A connection system for a semiconductor device package comprising - a plurality of bond areas around a single chip area ( 130 ), - a plurality of external terminals, each connected to a corresponding one of the plurality of bonding areas, and - a plurality of conductive lines ( 110 . 120 ), the coupling respective bond areas and external terminals, the bond areas each including bond tips of the conductive lines for connection to a respective one of a plurality of bond pads of a single chip to be mounted in the single die area, a first set ( 110a ) of the bond areas is positioned along a first line segment (L1) for connection to a first plurality of adjacent bond pads of the single chip to be attached, and a second set ( 120a ) of the bond regions is positioned along a second line segment (L2) for connection to a second plurality of adjacent bond pads of the single die to be attached, characterized in that - at least one of the conductive leads coupled to the second set of bond regions has a first bend point ( P1) which redirects the line towards the first set of bond areas. Connection system according to claim 5, characterized in that that the connection system includes a lead frame. Connection system according to claim 5 or 6, characterized characterized in that the conductive Lines lie on one level. Connection system according to one of claims 3 to 7, characterized in that the conductive lines inwardly over the Bond tips extend out into the single chip area to act as a carrier for one to serve in the single chip area mounted single chip. Connection system according to one of claims 1 and 3 to 8, characterized in that A change in bond angle between each one of the corresponding first plurality of adjacent ones Incremental bond pads and the first set of bond areas is - a change the bonding angle between each one of the corresponding second Plurality of adjacent bond pads and the second set of bond areas is incremental and A change in bond angle between a last of the corresponding first plurality of adjacent ones Bond pads and the first set of bond areas and a first of the corresponding second plurality of adjacent bond pads and the second set of bonding areas relative to the incremental change is discontinuous by opposing their direction of change to the direction of change the incremental change the bond angle between the last and a penultimate of the first Plurality of adjacent bond pads and the associated one of the first set of bonding areas and opposite to the direction of change the incremental change the bonding angle between the first and a second of the second Plurality of adjacent bond pads and the associated one of the second set of bond areas. Connection system according to one of claims 2 to 9, characterized in that the first and the second line segment are discontinuous. Connection system according to one of claims 1 to 10, characterized in that the bonding areas include bonding fingers. Connection system according to claim 11, characterized in that that the bonding fingers on an outer surface of a multi-layer substrate or a multi-layer printed circuit board are formed and further a plurality of conductive Through contacts include each of the plurality of bond fingers with one each the majority of external connections connect. Connection system according to one of claims 4 to 12, characterized in that the at least one of the conductive lines, which are coupled to the second set of bond areas, one second bend point (P2), which is closer to the single chip area lies as the first bend point and the line deflects so that it is oriented in a direction towards the bond pad, the bonding area of the conductive Line is assigned. Connection system according to one of claims 1 to 13, characterized in that the first and the second line segment at least one line segment, a curve segment, a sinusoidal curve segment, a spline function curve, an arc segment, a parabolic arc segment, a elliptical arc segment or a circular arc segment include. Connection system according to one of claims 1 to 14, characterized in that the bonding angles of each corresponding first plurality of adjacent bond pads and the first one Set of bond areas and the bond angles of each corresponding second Plurality of adjacent bond pads and the second set of bonding areas not larger than is a maximum acceptable bond angle. Connection system according to one of claims 2 to 15, characterized in that the first and the second line segment at different intervals are positioned from the single chip area. A connection system according to claim 16, since characterized in that the second line segment is closer to the single chip area than the first line segment. Connection system according to one of claims 1 to 17, characterized in that the bond areas are elongated are and have longitudinal axes, oriented in one direction to the associated bond pad are. Connection system according to one of claims 1 to 18, characterized in that the first set of bond areas, which is positioned along the first line segment, and the second set of bond areas, along the second line segment is positioned so in the connection system that they are one Octanes of the single chip area are assigned. Connection system according to claim 19, characterized that each octand has an associated one first set of bonding areas, along the first line segment is positioned, and a corresponding second set of bond areas which is positioned along the second line segment. Connection system according to one of claims 1 to 20, characterized in that the semiconductor device package a ball grid array (BGA), a quad-flat pack (QFP) or includes a quad flat non-lead package (QFN). Semiconductor device package comprising - a semiconductor device die ( 140 ) in a central single chip area of the package, wherein the single chip includes a first plurality of bond pads in a central area of an edge of the single chip and a second plurality of bond pads in a corner area of the single chip, 100 ) including a plurality of bonding areas around the single-chip area, and - a plurality of bonding wires ( 170a . 170b ), wherein each bonding wire connects corresponding bond areas of the connection system and bonding pads of the single chip, characterized in that - the connection system ( 100 ) is one according to one of claims 1 to 21. The semiconductor device package of claim 22, further characterized by a single chip pad, which is the single chip in the single chip area. Semiconductor component package according to claim 23, characterized characterized in that the single chip pad of square, rectangular, circular, oval, elliptical or polygonal shape. Semiconductor component package according to one of claims 22 to 24, characterized in that the bonding wires include: - one first set of bonding wires, the corresponding first set of bond areas and the majority from adjacent bond pads in the central region of the Couple individual chips, - one second set of bonding wires, the corresponding second set of bond areas and the majority from adjacent bond pads in the corner area of the single chip couple, - in which at least one of the bonding wires of the first set and at least one of the bonding wires of the second Set overlap. Semiconductor component package according to claim 25, characterized in that the at least one of the bonding wires of the first set a greater loop height than that at least one of the bonding wires of the second sentence. A method of wire bonding a semiconductor device package, comprising: - mounting a semiconductor device die ( 140 ) in a central single chip area of the package, wherein the single chip includes a first plurality of bond pads in a central area of an edge of the single chip and a second plurality of bond pads in a corner area of the single chip, characterized by providing a connection system ( 100 ) according to one of claims 1 to 21 and - wire bonding a plurality of bonding wires ( 170a . 170b ) to connect respective bonding areas of the connection system and bond pads of the single chip. Method according to Claim 27, characterized that attaching the single chip attaching the single chip on a single chip pad that includes the single chip in the single chip area.