DE102005010308B4 - Process for the production of chips with solderable connections on the rear side - Google Patents
Process for the production of chips with solderable connections on the rear side Download PDFInfo
- Publication number
- DE102005010308B4 DE102005010308B4 DE102005010308.1A DE102005010308A DE102005010308B4 DE 102005010308 B4 DE102005010308 B4 DE 102005010308B4 DE 102005010308 A DE102005010308 A DE 102005010308A DE 102005010308 B4 DE102005010308 B4 DE 102005010308B4
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- H01L2924/14—Integrated circuits
Abstract
Verfahren zur Herstellung von Halbleiterchips mit lötfähigen Anschlüssen auf der Rückseite der Chips, wobei die Chips als Oberflächenmontagebauelemente für die Direktmontage ihrer Rückseite auf Substraten ausgebildet sind und eine Chipoberseite mit den funktionellen Oberflächenstrukturen des Halbleiterbauelements und eine Chiprückseite mit den nach unten zeigenden Rückseitenanschlüssen zur elektrischen Kontaktierung auf Substraten aufweisen, bei dem folgende Schritte ausgeführt werden: – photolithographisches Strukturieren einer Ätzmaske auf der Chipoberseite der noch im Waferverbund befindlichen Halbleiterchips (2, 3) derart, dass in der Ätzmaske Fenster zwischen im Randbereich jeweils benachbarter Chips (2, 3) angeordneten Kontaktpads (5, 6) geöffnet werden, wobei diese Fenster breiter sind als eine beim späteren Vereinzeln der Chips (2, 3) durch Sägen entstehende Sägespur (4) und diese Sägespur (4) überdecken, – anisotropes Ätzen des Halbleitermaterials der Chipoberseite mit den geöffneten Fenstern als Ätzmaske so, dass zwischen den Kontaktpads (5, 6) der jeweils benachbarten Chips (2, 3) Vertiefungen (9) im Halbleitermaterial der Chipoberseite erzeugt werden, – Herstellen einer Isolation auf der Chipoberseite unter Aussparung der Kontaktpads (5, 6), wobei die Isolation in den Vertiefungen (9) eine Seitenwandpassivierung (18) bildet, – Herstellen einer Metallisierung (12), die die Kontaktpads (5, 6) der jeweils benachbarten Chips (2, 3) durch die Vertiefung (9) miteinander verbindet, – Oxidieren der Waferrückseite, – photolithographisches Strukturieren einer Ätzmaske auf der Waferrückseite und Ätzen von Fenstern in dem Oxid der Waferrückseite, – Herstellen von Vias (10) mit ovalem oder elliptischem Querschnitt durch anisotropes Trockenätzen der Chips (2, 3) des Waferverbundes von der Waferrückseite her mit der zuvor hergestellten Ätzmaske, wobei die Vias (10) bis zu den Vertiefungen (9) in der Chipoberseite reichen, – Passivierender Seitenwände der Vias (10) mit einer Seitenwandpassivierung (13) zur elektrischen Isolation der Seitenwände und komplettes Auffüllen der Vias (10) mit Metall (11), – Herstellen von Rückseitenkontakten der Chips (2, 3) durch – Abscheiden einer ersten photo-dielektrischen Schicht (19) auf der Waferrückseite, ...A method of manufacturing semiconductor chips having solderable terminals on the back side of the chips, wherein the chips are formed as surface mount devices for direct mounting of their back side on substrates, and a chip top having the functional surface structures of the semiconductor device and a chip back side having the downwardly facing backside terminals for electrical contacting Comprising substrates in which the following steps are carried out: photolithographic patterning of an etching mask on the chip top side of the semiconductor chips (2, 3) still in the wafer assembly such that in the etching mask windows between contact pads (2, 3) arranged in the edge region 5, 6) are opened, these windows being wider than a sawing track (4) produced by sawing during subsequent separation of the chips (2, 3) and overlapping this sawing track (4), - anisotropic etching of the semiconductor material Chip top side with the open windows as an etching mask so that between the contact pads (5, 6) of the respective adjacent chips (2, 3) recesses (9) are generated in the semiconductor material of the chip top side, - Making an insulation on the chip top side with recess of the contact pads ( 5, 6), wherein the insulation in the recesses (9) forms a sidewall passivation (18), - producing a metallization (12), the contact pads (5, 6) of the respective adjacent chips (2, 3) through the recess ( 9), - oxidizing the wafer backside, - photolithographically patterning an etch mask on the wafer back and etching windows in the wafer backside oxide, - producing vias (10) with oval or elliptical cross section by anisotropic dry etching of the chips (2, 3) the wafer assembly from the wafer backside with the previously prepared etch mask, wherein the vias (10) to the wells (9) in the top of the chip, Passivating sidewalls of the vias (10) with a sidewall passivation (13) for electrical insulation of the sidewalls and complete filling of the vias (10) with metal (11), - making back contacts of the chips (2, 3) by - depositing a first photo dielectric layer (19) on the back of the wafer, ...
Description
Die Erfindung betrifft ein Verfahren zur Herstellung von Chips mit lötfähigen Anschlüssen auf der Rückseite von Halbleiteranordnungen, derart, dass die Halbleiteranordnung als Oberflächenmontagebauelement (SMD-Bauelement) für die Direktmontage mit der Chipoberseite, welche die funktionellen Oberflächenstrukturen enthält, nach oben (Face up) geeignet ist.The invention relates to a method for the production of chips with solderable terminals on the back of semiconductor devices, such that the semiconductor device as a surface mounting device (SMD component) for direct mounting with the chip top side containing the functional surface structures upwards (face up) suitable is.
Derartige Halbleiteranordnungen mit beliebigen Oberflächenstrukturen und gegebenenfalls elektronischen und mechanischen Komponenten, wie Mikrospiegel oder sonstigen mechanischen Strukturen, die optisch oder chemisch bzw. auf sonstige Reize sensitiv sind, können Platz sparend ohne jede weitere Chip and Wire Technik, also ohne zusätzliche Drahtbondtechnologie verarbeitet, d. h. auf beliebigen Substraten montiert werden.Such semiconductor arrangements with arbitrary surface structures and optionally electronic and mechanical components, such as micromirrors or other mechanical structures, which are optically or chemically or sensitive to other stimuli, can be space-saving processed without any further chip and wire technology, ie without additional wire bonding technology, d. H. be mounted on any substrates.
Um das zu erreichen, ist es erforderlich, die auf der aktiven Seite der jeweiligen Halbleiteranordnung befindlichen Kontaktpads, die normalerweise für die elektrische Verbindung mit einem Substrat (PCB) mittels Drahtbrücken oder auch Redistribution Layers (Umverdrahtungen) und Löthügel oder Lotbumps (Solder Bumps) o. dgl. verwendet werden, auf die Rückseite derselben zu verlegen.In order to achieve this, it is necessary to use the contact pads located on the active side of the respective semiconductor arrangement, which are normally used for electrical connection to a substrate (PCB) by means of wire bridges or redistribution layers and solder bumps or solder bumps The like can be used to lay on the back of the same.
Dazu ist es bekannt geworden, die Halbleiteranordnungen zunächst in Waferverbund vollständig zu prozessieren. Anschließend daran werden dann metallische Leitbahnen von den Kontaktpads auf der aktiven Seite der Halbleiteranordnung bis auf die Außenkanten derselben und eine elektrische Verbindung der Leitbahnen auf den Außenkanten mit Kontakten auf der Rückseite der Halbleiteranordnung hergestellt. Danach erfolgt dann die Vereinzelung in individuelle Halbleiteranordnungen.For this purpose, it has become known to process the semiconductor devices initially completely in wafer composite. Subsequently, metallic interconnects are then produced from the contact pads on the active side of the semiconductor device to the outer edges thereof and an electrical connection of the interconnects on the outer edges with contacts on the back side of the semiconductor device. This is followed by separation into individual semiconductor arrangements.
So zeigt die
Es versteht sich, dass ein derartiges Verfahren wegen der notwendigen und komplizierten 3-D-Lithographie äußerst aufwändig ist. Außerdem erfordert die gegenüber normalen Sägespuren wesentlich breitere v-förmige Nut wegen des größeren Flächenbedarfs eine Berücksichtigung bereits im Entwurf des Schaltungs-Layouts. Die Folge ist eine geringere Chipanzahl pro Wafer. Nachteilig ist zudem die unproduktive Herstellung der v-förmigen Nuten, was durch sequentielles Schleifen oder Ansägen bei geringem Vorschub erfolgt. Die hergestellten Kontakte (sog. „T-contact”) zwischen Kontaktpad und der auf den Flanken der v-förmigen Nuten angebrachten Leitbahnen sind extrem empfindlich gegenüber den Herstellungsbedingungen und leiden an Zuverlässigkeitsproblemen, die durch Unterbrechungen hervorgerufen werden.It is understood that such a method is extremely complicated because of the necessary and complicated 3-D lithography. In addition, the substantially wider compared to normal saw marks V-shaped groove due to the larger area requirement requires consideration already in the design of the circuit layout. The result is a smaller number of chips per wafer. Another disadvantage is the unproductive production of the V-shaped grooves, which is done by sequential grinding or sawing with low feed. The fabricated contacts (so-called "T-contact") between the contact pad and the interconnects mounted on the flanks of the V-shaped grooves are extremely sensitive to manufacturing conditions and suffer from reliability problems caused by interruptions.
Ein anderes Verfahren zur Herstellung von dreidimensional aufgebauten integrierten Schaltungen mit Rückseitenkontaktierung geht aus der
Um das zu erreichen wird ein Kontakt von der einen Seite des Chips zu dessen anderen Seite hergestellt, indem ein leitender Kanal in das Chip eingebracht wird. Auf der anderen Seite des Chips wird eine Kontaktfläche hergestellt, die mit dem leitenden Kanal elektrisch verbunden ist. Dieser leitende Kanal kann durch Einfügen eines Lochs erzeugt werden, das anschließend mit einem leitenden Material oder einen leitenden Epoxyd verfüllt wird.To accomplish this, contact is made from one side of the chip to its other side by inserting a conductive channel into the chip. On the other side of the chip, a contact surface is produced, which is electrically connected to the conductive channel. This conductive channel can be created by inserting a hole, which is then filled with a conductive material or a conductive epoxy.
Für den Fall, dass das Loch dem Chip nicht durchdringt, wird das Chip nach dem Verfüllen mit dem leitenden Material abgedünnt, so dass zumindest im Bereich des Lochs die Dicke des Chips geringer ist, als die Tiefe des Lochs. Die Löcher werden dabei mittels Ätzen hergestellt und stellen somit Ätzgruben im Substrat dar, die sich innerhalb der Chipfläche befinden. Damit ist die Anwendung auf Substrate bzw. prozessierte Wafer beschränkt, die eine ausreichende Fläche für die Herstellung der Ätzgruben aufweisen, oder der größere Flächenbedarf findet bereits eine Berücksichtigung während des Entwurfs des Schaltungs-Layouts.In the event that the hole does not penetrate the chip, the chip is thinned after filling with the conductive material, so that at least in the region of the hole, the thickness of the chip is less than the depth of the hole. The holes are made by etching and thus represent etching pits in the substrate, which are located within the chip surface. Thus, the application is limited to substrates or processed wafers, which have a sufficient area for the production of etch pits, or the larger area requirement already takes into account during the design of the circuit layout.
Weiterhin wird in der
Diese Anwendung setzt voraus, dass sich unter der oberen zu kontaktierenden Metallisierungsebene keine weiteren dielektrischen Schichten, dotierte oder undotierte Bereiche sowie Metallisierungen befinden, die jeweils in Ebenen angeordnet sind. Somit ist dieses Verfahren für Chips, die durch etablierte CMOS-Technologien hergestellt werden und dabei überwiegend solche Strukturen besitzen, nicht praktikabel. In Abhängigkeit von der Substrat- bzw. Waferdicke ist die Packungsdichte der elektrischen Verbindungen geometrisch begrenzt durch die inhärente Neigung der Seitenwände (Kristallebenen) bei der Verwendung des anisotropen nasschemischen Ätzens. Dieses Verfahren kann nur bei einer vergleichsweise geringen Anzahl von Durchkontaktierungen, die zudem einen großen Pitch besitzen, eingesetzt werden.This application presupposes that there are no further dielectric layers, doped or undoped regions and metallizations, which are each arranged in planes, below the upper metallization level to be contacted. Thus, this method is impractical for chips made by established CMOS technologies that predominantly have such structures. Depending on the substrate or wafer thickness, the packing density of the electrical connections is geometrically limited by the inherent tilt of the sidewalls (crystal planes) when using the anisotropic wet-chemical etching. This method can be used only with a comparatively small number of vias, which also have a large pitch.
In der
Die in der Sägespur immer vorhandenen Teststrukturen werden dabei nicht berücksichtigt, so dass die Gefahr von Kurzschlüssen oder zumindest Fehlfunktionen besteht.The test structures that are always present in the saw track are not taken into account, so there is a risk of short circuits or at least malfunctions.
Die
Aus der
In Appl. Phys. Lett. 58 (11), 18 March 1001, pp. 1178–1180 wird ein Verfahren zur Laservorbehandlung von Oberflächen und zur nachfolgenden Füllung von Vias mit einem Metall mittels LP-CVD beschrieben. Mit der Laservorbehandlung wird eine Keimschicht abgeschieden, welche die nachfolgende Füllung mit einem Metall ermöglicht.In Appl. Phys. Lett. 58 (11), 18 March 1001, pp. 1178-1180 describes a process for laser pretreatment of surfaces and subsequent filling of vias with a metal by means of LP-CVD. With the laser pretreatment, a seed layer is deposited, which allows the subsequent filling with a metal.
Auch aus der
Schließlich beschreibt die
Der Erfindung liegt die Aufgabe zugrunde, ein Verfahren zur Herstellung von Chips mit lötfähigen Anschlüssen auf der Rückseite von Halbleiteranordnungen bereits im Waferverbund, d. h. auf Wafer-Level-Ebene zu schaffen, das unabhängig vom Bauelement und ohne Änderung des Schaltungs-Layouts einfach und kostengünstig realisiert werden kann.The invention is based on the object, a method for the production of chips with solderable terminals on the back of semiconductor devices already in the wafer composite, d. H. at the wafer level level, which can be realized easily and inexpensively regardless of the device and without changing the circuit layout.
Die der Erfindung zugrunde liegende Aufgabe wird gelöst durch die Merkmale des Hauptanspruchs.The object underlying the invention is achieved by the features of the main claim.
Das erfindungsgemäße Verfahren ermöglicht eine effektivere Herstellung von Rückseitenkontakten, ohne dass das Layout der Halbleiteranordnungen (Chips) geändert werden muss.The inventive method enables a more effective production of backside contacts without having to change the layout of the semiconductor devices (chips).
Die Herstellung der Vias einschließlich deren Seitenwandpassivierung und Metallisierung nach der photolithographischen Strukturierung einer Ätzmaske kann einfach von der Rückseite des Wafers aus erfolgen.The fabrication of the vias including their sidewall passivation and metallization after the photolithographic patterning of an etch mask can be done easily from the backside of the wafer.
Die Öffnung der Ätzfenster für die Herstellung der Vias kann durch Oxidätzen mit SF6/CHF3 vorgenommen werden. Eine andere Möglichkeit besteht darin, die Öffnung der Ätzfenster durch nasschemisches Ätzen vorzunehmen.The opening of the etch window for the production of the vias can be made by oxide etching with SF 6 / CHF 3 . Another possibility is to undertake the opening of the etching windows by wet-chemical etching.
Die Vias selbst können durch anisotropes Trockenätzen (DRIE, ICP) mit hoher Ätzrate mit SF6/CH4/C4F8 hergestellt werden. Dabei liegt der erreichte Böschungswinkel im Bereich von 70°...88°. The vias themselves can be made by anisotropic dry etching (DRIE, ICP) with high etching rate with SF 6 / CH 4 / C 4 F 8 . The reached slope angle is in the range of 70 ° ... 88 °.
Die Seitenwandpasivierung der Vias kann einfach durch plasmaunterstützte Oxydation mit SiH4/N2O oder durch plasmaunterstützte Siliziumnitriderzeugung (mit SiH4/NH3) erfolgen.The sidewall pasivation of the vias can be done easily by plasma assisted oxidation with SiH 4 / N 2 O or by plasma assisted silicon nitride generation (with SiH 4 / NH 3 ).
In einer weiteren Ausführungsform besteht die Seitenwandpassivierung aus einer Kombination von nacheinander abgeschiedenen Siliziumoxid- und Siliziumnitridlagen, die mit plasmaangeregter Gasphasenabscheidung (PECVD) erzeugt wird.In another embodiment, sidewall passivation consists of a combination of sequentially deposited silicon oxide and silicon nitride layers produced by plasma enhanced vapor deposition (PECVD).
In Fortführung der Erfindung werden die Vias mit TiN oder TaN als Barriereschicht belegt und anschließend durch Wolfram-CVD mittels WF6 oder Cu-CVD beschichtet. Dies ist die Startschicht für anschließende stromlose bzw. galvanische Cu-Abscheidung zum Verfüllen der Vias.In continuation of the invention, the vias are coated with TiN or TaN as a barrier layer and then coated by tungsten CVD using WF 6 or Cu-CVD. This is the starting layer for subsequent electroless or galvanic Cu deposition for filling the vias.
Es ist auch möglich, die Vias durch Al-Laser-CVD oder Cu-Laser-CVD mit Al oder Cu zu füllen.It is also possible to fill the vias with Al or Cu by Al laser CVD or Cu laser CVD.
Zur Erleichterung der Herstellung der Vias von der Rückseite aus und der nachfolgenden Beschichtung kann der prozessierte Wafer unter Zuhilfenahme bekannter Abdünnverfahren gedünnt werden, wie z. B. chemisch-mechanisches Polieren (CMP).To facilitate the production of the vias from the back and the subsequent coating of the processed wafer can be thinned using known thinning, such. B. chemical mechanical polishing (CMP).
Eine besondere Ausgestaltung der Erfindung besteht darin, dass die mit Metall gefüllten Vias nicht zentriert in der Sägespur zwischen den benachbarten Chips angeordnet sind. Durch eine entsprechende Wahl der geometrischen Dimensionen können die Vias so ausgeführt sein, dass diese beim Vereinzeln der Chips nicht mit getrennt werden.A particular embodiment of the invention consists in that the metal-filled vias are not centered in the saw track between the adjacent chips. By an appropriate choice of geometric dimensions, the vias can be designed so that they are not separated when separating the chips.
Die Erfindung ist dadurch gekennzeichnet, dass für die Herstellung des Rückseitenkontaktes zunächst eine erste photo-dielektrische Schicht (BCB) auf der Rückseite des Wafers abgeschieden und ein Lithographieschritt zur Ausbildung einer Öffnung über den metallisierten Vias mit anschließender chemischer Aktivierung ausgeführt wird, dass auf der gesamten Rückseite des Wafers eine Metallisierung abgeschieden und nach einem Lithographieschritt die Metallschicht zur Ausbildung der Umverdrahtung strukturiert wird, dass eine zweite photodielektrische Schicht aufgetragen und lithographiert wird und dass anschließend eine UBM (Under Bump Metallization/Metallurgy) zur Aufnahme von Lotdepots hergestellt wird.The invention is characterized in that, for the production of the backside contact, first a first photo-dielectric layer (BCB) is deposited on the back of the wafer and a lithography step is carried out to form an opening over the metallized vias with subsequent chemical activation, that on the whole A metallization is deposited on the rear side of the wafer and, after a lithography step, the metal layer is patterned to form the rewiring, a second photodielectric layer is applied and lithographed, and subsequently an underbump metallization / metallurgy (UBM) is produced to receive solder deposits.
Die erste Photo-dielektrische Schicht kann vorteilhaft mit einem Palladium-Aktivator aktiviert werden.The first photo-dielectric layer may be advantageously activated with a palladium activator.
Schließlich ist vorgesehen, dass die metallische Leiterbahn, z. B. Cu, für Leitbahnen der Umverdrahtung durch stromloses Beschichten hergestellt wird.Finally, it is provided that the metallic conductor track, z. B. Cu, for interconnects of the rewiring by electroless plating is made.
In einer weiteren Ausgestaltung der Erfindung besteht die UBM aus einer Nickel/Gold-Schicht, wobei die Nickelschicht durch stromloses Abscheiden und die Goldschicht durch einen Au-Immersionsprozess abgeschieden wird. Diese derart hergestellten Kontaktflächen bzw. Lands können bereits für eine Oberflächenmontage genutzt oder mit Lötbumps ergänzt werden.In a further embodiment of the invention, the UBM consists of a nickel / gold layer, wherein the nickel layer is deposited by electroless deposition and the gold layer by an Au immersion process. These contact surfaces or lands produced in this way can already be used for surface mounting or supplemented with solder bumps.
Die Herstellung der Lötbumps geschieht vorteilhaft mittels Aufbringen der Lotdepots durch Schablonendruck. Mit einem Reflow-Prozess erfolgt das Ausformen der Lothügel bzw. der Lotbumps.The production of Lötbumps is done advantageously by applying the solder deposits by stencil printing. A reflow process is used to shape the solder bumps or solder bumps.
Die Erfindung soll nachfolgend an einem Ausführungsbeispiel näher erläutert werden. In den zugehörigen Zeichnungen zeigen:The invention will be explained in more detail below using an exemplary embodiment. In the accompanying drawings show:
In
Weiterhin sind zentrisch zur Sägespur
Auf der Waferrückseite befinden sich weiterhin Rückseitenkontakte, bestehend aus einer Cu-Metallisierung
Bei dem Wafer
Für die Herstellung von lötfähigen Anschlüssen auf der Rückseite von Chips
Das Ätzen von Vertiefungen
Anschließend wird dann eine Metallisierung
Im nächsten Schritt werden dann Vias
Die notwendige Seitenwandpasivierung der Vias
Im Anschluss an die Herstellung der Vias
zum Schluss werden dann die Rückseitenkontakte der Chips
Für die Herstellung der Rückseitenkontakte wird zunächst eine erste photo-dielektrische Schicht
Danach wird auf der gesamten Rückseite des Wafers eine Cu-Metallisierung
Die Herstellung der Lotdepots wird vorteilhaft mit einem Schablonendruck realisiert. Mit einem Reflow-Prozess erfolgt danach das Ausformen der Lothügel bzw. Lotbumps
BezugszeichenlisteLIST OF REFERENCE NUMBERS
- ll
- Waferwafer
- 22
- Chipchip
- 33
- Chipchip
- 44
- Sägespur (Schnittbreite)Saw track (cutting width)
- 55
- Kontaktpadcontact pad
- 66
- Kontaktpadcontact pad
- 77
- aktives Gebietactive area
- 88th
- aktives Gebietactive area
- 99
- Vertiefungdeepening
- 1010
- ViaVia
- 1111
- Metallfüllung des ViaMetal filling of the Via
- 1212
- Metallisierungmetallization
- 1313
- Isolationisolation
- 1414
- Cu-MetallisierungCu metallization
- 1515
- UBMUBM
- 1616
- UBMUBM
- 1717
- Lotbumpsolder bump
- 1818
- Seitenwandpassivierungsidewall
- 1919
- Photodielektrische SchichtPhotodielectric layer
- 2020
- Foto-dielektrische SchichtPhoto-dielectric layer
- 2121
- SägegrabenSägegraben
Claims (15)
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Citations (5)
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---|---|---|---|---|
DE2054571A1 (en) * | 1969-11-07 | 1971-05-19 | Ibm | Integrated semiconductor structure and method for producing this semiconductor structure |
US20020139577A1 (en) * | 2001-03-27 | 2002-10-03 | Miller Charles A. | In-street integrated circuit wafer via |
US20040017012A1 (en) * | 2000-10-23 | 2004-01-29 | Yuichiro Yamada | Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device |
EP1429377A2 (en) * | 2002-12-13 | 2004-06-16 | Sanyo Electric Co., Ltd. | Method of reflowing conductive terminals |
DE10320877A1 (en) * | 2003-05-09 | 2004-12-09 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Semiconductor component and method for producing a semiconductor component |
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2005
- 2005-03-03 DE DE102005010308.1A patent/DE102005010308B4/en not_active Expired - Fee Related
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DE2054571A1 (en) * | 1969-11-07 | 1971-05-19 | Ibm | Integrated semiconductor structure and method for producing this semiconductor structure |
US20040017012A1 (en) * | 2000-10-23 | 2004-01-29 | Yuichiro Yamada | Semiconductor chip, wiring board and manufacturing process thereof as well as semiconductor device |
US20020139577A1 (en) * | 2001-03-27 | 2002-10-03 | Miller Charles A. | In-street integrated circuit wafer via |
EP1429377A2 (en) * | 2002-12-13 | 2004-06-16 | Sanyo Electric Co., Ltd. | Method of reflowing conductive terminals |
DE10320877A1 (en) * | 2003-05-09 | 2004-12-09 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | Semiconductor component and method for producing a semiconductor component |
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