DE102005010308B4 - Process for the production of chips with solderable connections on the rear side - Google Patents

Abstract

A method of manufacturing semiconductor chips having solderable terminals on the back side of the chips, wherein the chips are formed as surface mount devices for direct mounting of their back side on substrates, and a chip top having the functional surface structures of the semiconductor device and a chip back side having the downwardly facing backside terminals for electrical contacting Comprising substrates in which the following steps are carried out: photolithographic patterning of an etching mask on the chip top side of the semiconductor chips (2, 3) still in the wafer assembly such that in the etching mask windows between contact pads (2, 3) arranged in the edge region 5, 6) are opened, these windows being wider than a sawing track (4) produced by sawing during subsequent separation of the chips (2, 3) and overlapping this sawing track (4), - anisotropic etching of the semiconductor material Chip top side with the open windows as an etching mask so that between the contact pads (5, 6) of the respective adjacent chips (2, 3) recesses (9) are generated in the semiconductor material of the chip top side, - Making an insulation on the chip top side with recess of the contact pads ( 5, 6), wherein the insulation in the recesses (9) forms a sidewall passivation (18), - producing a metallization (12), the contact pads (5, 6) of the respective adjacent chips (2, 3) through the recess ( 9), - oxidizing the wafer backside, - photolithographically patterning an etch mask on the wafer back and etching windows in the wafer backside oxide, - producing vias (10) with oval or elliptical cross section by anisotropic dry etching of the chips (2, 3) the wafer assembly from the wafer backside with the previously prepared etch mask, wherein the vias (10) to the wells (9) in the top of the chip, Passivating sidewalls of the vias (10) with a sidewall passivation (13) for electrical insulation of the sidewalls and complete filling of the vias (10) with metal (11), - making back contacts of the chips (2, 3) by - depositing a first photo dielectric layer (19) on the back of the wafer, ...

Description

The invention relates to a method for the production of chips with solderable terminals on the back of semiconductor devices, such that the semiconductor device as a surface mounting device (SMD component) for direct mounting with the chip top side containing the functional surface structures upwards (face up) suitable is.

Such semiconductor arrangements with arbitrary surface structures and optionally electronic and mechanical components, such as micromirrors or other mechanical structures, which are optically or chemically or sensitive to other stimuli, can be space-saving processed without any further chip and wire technology, ie without additional wire bonding technology, d. H. be mounted on any substrates.

In order to achieve this, it is necessary to use the contact pads located on the active side of the respective semiconductor arrangement, which are normally used for electrical connection to a substrate (PCB) by means of wire bridges or redistribution layers and solder bumps or solder bumps The like can be used to lay on the back of the same.

For this purpose, it has become known to process the semiconductor devices initially completely in wafer composite. Subsequently, metallic interconnects are then produced from the contact pads on the active side of the semiconductor device to the outer edges thereof and an electrical connection of the interconnects on the outer edges with contacts on the back side of the semiconductor device. This is followed by separation into individual semiconductor arrangements.

That's how it shows US Pat. No. 6,040,235 a method and an apparatus for the production of an integrated circuit are produced in the first in the wafer assembly along the future joints mechanically introduced v-shaped grooves. In these grooves metal contacts or metal tracks are then prepared by means of 3-D lithography, mask patterning and metal deposition, which are connected to the contact pads in a metallization of the integrated circuit. Finally, then the division into individual integrated circuits by separating saws o. The like. A similar process is also from the US Pat. No. 6,646,289 B1 out.

It is understood that such a method is extremely complicated because of the necessary and complicated 3-D lithography. In addition, the substantially wider compared to normal saw marks V-shaped groove due to the larger area requirement requires consideration already in the design of the circuit layout. The result is a smaller number of chips per wafer. Another disadvantage is the unproductive production of the V-shaped grooves, which is done by sequential grinding or sawing with low feed. The fabricated contacts (so-called "T-contact") between the contact pad and the interconnects mounted on the flanks of the V-shaped grooves are extremely sensitive to manufacturing conditions and suffer from reliability problems caused by interruptions.

Another method for manufacturing three-dimensional integrated circuits with back contact is from the DE 101 41 475 A1 out. Here, a method is described in which chips can be interconnected so that the active sides of the chips comprising the electronically active elements need not face each other.

To accomplish this, contact is made from one side of the chip to its other side by inserting a conductive channel into the chip. On the other side of the chip, a contact surface is produced, which is electrically connected to the conductive channel. This conductive channel can be created by inserting a hole, which is then filled with a conductive material or a conductive epoxy.

In the event that the hole does not penetrate the chip, the chip is thinned after filling with the conductive material, so that at least in the region of the hole, the thickness of the chip is less than the depth of the hole. The holes are made by etching and thus represent etching pits in the substrate, which are located within the chip surface. Thus, the application is limited to substrates or processed wafers, which have a sufficient area for the production of etch pits, or the larger area requirement already takes into account during the design of the circuit layout.

Furthermore, in the DE 198 46 232 A1 a method for producing a semiconductor device with back-contacting described. For this purpose, an etching pit is formed in a main surface, ie, from the rear side of the component substrate, which extends as far as a highly doped connection region or up to the metallization plane (contact pad) of the component structure. Following this, an insulation layer is produced on at least regions of the main surface, which comprises the etching pit, such that at least a portion of the heavily doped connection region or the metallization plane remains free. Subsequently, a metallization layer on the Insulation layer generated so that the metallization layer conductively connects the vacant portion of the heavily doped terminal region or the metallization with the contact region on the other main surface of the semiconductor substrate.

This application presupposes that there are no further dielectric layers, doped or undoped regions and metallizations, which are each arranged in planes, below the upper metallization level to be contacted. Thus, this method is impractical for chips made by established CMOS technologies that predominantly have such structures. Depending on the substrate or wafer thickness, the packing density of the electrical connections is geometrically limited by the inherent tilt of the sidewalls (crystal planes) when using the anisotropic wet-chemical etching. This method can be used only with a comparatively small number of vias, which also have a large pitch.

In the US 2002/0139577 A1 a wafer with holes in the saw line is described. The vias are formed by etching steps from the active side of the wafer, each followed by a passivation step. After each etching step, however, a protective layer is first applied to the bottom of the hole (blind hole) in order to prevent the subsequent passivation that the bottom of the hole is passivated with. After completion of the holes, the wafer is metallized and the holes filled with metal and made by photolithographic steps a connection between the metallization in the via and the corresponding contact pads on the wafer top and bottom.

The test structures that are always present in the saw track are not taken into account, so there is a risk of short circuits or at least malfunctions.

The DE 20 54 571 refers to the connection of optical components on top of a chip with circuit parts on the bottom, also to realize stacking arrangements. For this purpose, windows are first photolithographically produced by etching through the passivation (oxide layer), which is used as a hard mask. Thereafter, etching is carried out along the crystal structures from both sides until pyramidal or conical structures with an opening are formed, which are then metallized.

From the US 2004/0017012 A1 shows a method for producing a semiconductor chip, in which both sides of the saw blade vias are produced in the form of blind holes. These blind holes are filled with metal after passivation, whereupon the silicon substrate is turned over and glued onto a support. Subsequently, from the back of a V-shaped recess by grinding or anisotropic etching is incorporated until the blind holes are opened. This is followed by backside metallization and passivation. Finally, the wells are filled with a plastic prior to sawing the silicon substrate into chips.

In Appl. Phys. Lett. 58 (11), 18 March 1001, pp. 1178-1180 describes a process for laser pretreatment of surfaces and subsequent filling of vias with a metal by means of LP-CVD. With the laser pretreatment, a seed layer is deposited, which allows the subsequent filling with a metal.

Also from the DE 103 20 877 A1 shows that a mask surface is first germinated with a metal on which copper can then chemically deposit.

Finally, that describes EP 1 429 377 A2 a stencil printing method on UBM layers with subsequent formation of Lörbumps by reflow soldering.

The invention is based on the object, a method for the production of chips with solderable terminals on the back of semiconductor devices already in the wafer composite, d. H. at the wafer level level, which can be realized easily and inexpensively regardless of the device and without changing the circuit layout.

The object underlying the invention is achieved by the features of the main claim.

The inventive method enables a more effective production of backside contacts without having to change the layout of the semiconductor devices (chips).

The fabrication of the vias including their sidewall passivation and metallization after the photolithographic patterning of an etch mask can be done easily from the backside of the wafer.

The opening of the etch window for the production of the vias can be made by oxide etching with SF ₆ / CHF ₃ . Another possibility is to undertake the opening of the etching windows by wet-chemical etching.

The vias themselves can be made by anisotropic dry etching (DRIE, ICP) with high etching rate with SF ₆ / CH ₄ / C ₄ F ₈ . The reached slope angle is in the range of 70 ° ... 88 °.

The sidewall pasivation of the vias can be done easily by plasma assisted oxidation with SiH ₄ / N ₂ O or by plasma assisted silicon nitride generation (with SiH ₄ / NH ₃ ).

In another embodiment, sidewall passivation consists of a combination of sequentially deposited silicon oxide and silicon nitride layers produced by plasma enhanced vapor deposition (PECVD).

In continuation of the invention, the vias are coated with TiN or TaN as a barrier layer and then coated by tungsten CVD using WF ₆ or Cu-CVD. This is the starting layer for subsequent electroless or galvanic Cu deposition for filling the vias.

It is also possible to fill the vias with Al or Cu by Al laser CVD or Cu laser CVD.

To facilitate the production of the vias from the back and the subsequent coating of the processed wafer can be thinned using known thinning, such. B. chemical mechanical polishing (CMP).

A particular embodiment of the invention consists in that the metal-filled vias are not centered in the saw track between the adjacent chips. By an appropriate choice of geometric dimensions, the vias can be designed so that they are not separated when separating the chips.

The invention is characterized in that, for the production of the backside contact, first a first photo-dielectric layer (BCB) is deposited on the back of the wafer and a lithography step is carried out to form an opening over the metallized vias with subsequent chemical activation, that on the whole A metallization is deposited on the rear side of the wafer and, after a lithography step, the metal layer is patterned to form the rewiring, a second photodielectric layer is applied and lithographed, and subsequently an underbump metallization / metallurgy (UBM) is produced to receive solder deposits.

The first photo-dielectric layer may be advantageously activated with a palladium activator.

Finally, it is provided that the metallic conductor track, z. B. Cu, for interconnects of the rewiring by electroless plating is made.

In a further embodiment of the invention, the UBM consists of a nickel / gold layer, wherein the nickel layer is deposited by electroless deposition and the gold layer by an Au immersion process. These contact surfaces or lands produced in this way can already be used for surface mounting or supplemented with solder bumps.

The production of Lötbumps is done advantageously by applying the solder deposits by stencil printing. A reflow process is used to shape the solder bumps or solder bumps.

The invention will be explained in more detail below using an exemplary embodiment. In the accompanying drawings show:

1 FIG. 4 is a schematic sectional view of a plan view of the area between two integrated circuits with contact pads and a metallic connection between two adjacent contact pads through an anisotropically etched recess; FIG.

2 : a sectional view along the line AB in 1 backside contacts electrically connected via the cavity and a metal-filled via to contact pads on the active side of the integrated circuit; and

3 FIG. 4 is a schematic sectional view of a top view of the area between two integrated circuits with contact pads and variously shaped metallic interconnections up to the anisotropically etched recess and various via arrangements. FIG.

In 1 is a section of a wafer 1 with two adjacent chips 2 . 3 in the area of the saw track 4 shown as a plan view. Continue to be on the chips 2 . 3 each in the edge area next to the saw track 3 arranged in rubbing contact pads 5 . 6 , each with an active area 7 . 8th (n ⁺ area) are contacted ( 2 ).

Furthermore, they are centric to the saw track 4 wells 9 into the surface of the wafer 1 etched. The depression 9 sits down through the wafer 1 in the form of a vias 10 away, that with a metal 11 is filled. In conjunction with metallization 12 that is between the Kontatpads 5 . 6 through the depression 9 extends, thus becomes an electrical connection from the contact pads 5 . 6 through the wafer 1 extends to the back. It is understood that himself under the metallization 12 an isolation 18 which isolates the metallization from the adjacent semiconductor material. Likewise is an isolation 13 around the metal filling 11 arranged around which the metal filling of the vias 10 isolated from the adjacent semiconductor material.

On the backside of the wafer are still backside contacts, consisting of a copper metallization 14 as well as one UBM each 15 . 16 for a soldering bump 17 ,

At the wafer 1 it may also be a back-ground wafer, which has been post-treated by a flash-etch after the grinding and polishing operation.

For making solderable connections on the back of chips 2 . 3 First, a photolithographic structuring of an etching mask on the active side of the still in the wafer composite chips 2 . 3 , The structuring of the mask is carried out in such a way that windows next to contact pads 5 . 6 , the area of the saw track 4 between individual chips 2 . 3 overlapping and with greater width than the saw track 4 , be formed. Thereafter, by anisotropic etching of pits 9 in the wafer 1 etched through the windows and then as a side wall passivation insulation 18 ,, z. As SiO ₂ or Si ₃ H ₄ , with the recess of the contact pads 5 . 6 or the UBM (Ni / Au) located thereon.

The etching of pits 9 in the wafer 1 can the in the sawing 4 or in the sawmill 21 eliminate test structures that are necessary for process control.

Subsequently, a metallization 12 by a conventional mask patterning and coating technology from a contact pad 5 a chip 2 through the depression 9 to another contact pad 6 of the neighboring chip 3 produced.

3 alternatively shows a metallization 12 that from a contact pad 5 a chip 2 only into the depression 9 zoom ranges. Likewise, the possibility is shown here, the wells 9 not centric to the saw blade in the surface of the wafer 1 to etch.

The next step will be vias 10 with oval or elliptical cross section through the depressions 9 to the back of the wafer 1 produced by the wafer back is first oxidized, then for the vias 10 to open corresponding mask windows with conventional lithography and mask technology. This can be done by wet chemical etching or by dry etching. The vias themselves are made by anisotropic dry etching (DRIE, ICP) at a high etch rate from the wafer backside.

The necessary sidewall pasivation of the vias 10 is done by suitable process steps. The sidewall passivation 13 may advantageously in addition to the dielectric insulation in the form of SiO ₂ also contain a barrier in the form of TiN or TaN as a layer sequence.

Following the preparation of the vias 10 These will be with a metal 11 filled, which can be done by tungsten CVD with tungsten or alternatively by electroless or galvanic deposition with Cu. It is also possible to fill the vias with Al or Cu by a Cu CVD method, Al laser CVD or Cu laser CVD.

Finally, the backside contacts of the chips 2 . 3 made and filled with metal vias 10 connected. This is done such that a backside contact of a chip 2 over the corresponding Via 10 with a backside contact of the adjacent chip 3 is electrically connected. Finally, then the wafer 1 into individual chips 2 . 3 zersagt.

For the production of the backside contacts, first a first photo-dielectric layer 19 on the back of the wafer 1 followed by a lithography step followed by chemical activation with a palladium activator.

Thereafter, a Cu metallization occurs on the entire backside of the wafer 14 deposited by electroless plating and after a lithography step the copper metallization 14 structured: Subsequently, a second photodielectric layer is applied and lithographed and then a UBM 15 . 16 from a nickel / gold layer to accommodate solder bumps 17 produced. The nickel layer can be easily prepared by electroless plating. For the deposition of the gold layer, an Au immersion process is particularly suitable.

The production of the solder deposits is advantageously realized with a stencil printing. With a reflow process then takes the shaping of the solder bumps or solder bumps 17 ,

LIST OF REFERENCE NUMBERS

l

wafer

2

chip

3

chip

4

Saw track (cutting width)

5

contact pad

6

contact pad

7

active area

8th

active area

9

deepening

10

Via

11

Metal filling of the Via

12

metallization

13

isolation

14

Cu metallization

15

UBM

16

UBM

17

solder bump

18

sidewall

19

Photodielectric layer

20

Photo-dielectric layer

21

Sägegraben

Claims (15)

A method of manufacturing semiconductor chips having solderable terminals on the back side of the chips, wherein the chips are formed as surface mount devices for direct mounting of their back side on substrates and a chip top having the functional surface structures of the semiconductor device and a chip back side having the downwardly facing backside terminals for electrical contacting Have substrates in which the following steps are carried out: photolithographic patterning of an etching mask on the chip top side of the semiconductor chips still in the wafer assembly ( 2 . 3 ) such that in the etching mask windows between in the edge region respectively adjacent chips ( 2 . 3 ) arranged contact pads ( 5 . 6 ) are opened, these windows are wider than one in the later separation of the chips ( 2 . 3 ) saw blade caused by sawing ( 4 ) and this saw track ( 4 ) cover, - anisotropic etching of the semiconductor material of the chip top side with the opened windows as an etching mask such that between the contact pads ( 5 . 6 ) of the respective adjacent chips ( 2 . 3 ) Wells ( 9 ) are produced in the semiconductor material of the chip top side, - production of an insulation on the chip top side with the recess of the contact pads ( 5 . 6 ), with the isolation in the wells ( 9 ) a sidewall passivation ( 18 ), - producing a metallization ( 12 ), the contact pads ( 5 . 6 ) of the respective adjacent chips ( 2 . 3 ) through the depression ( 9 ), - oxidizing the wafer backside, - photolithographically patterning an etching mask on the wafer back side and etching windows in the wafer backside oxide, - producing vias ( 10 ) with an oval or elliptical cross section through anisotropic dry etching of the chips ( 2 . 3 ) of the wafer composite from the wafer backside with the previously prepared etch mask, wherein the vias ( 10 ) to the wells ( 9 ) in the chip top, - Passivating sidewalls of the vias ( 10 ) with a sidewall passivation ( 13 ) for the electrical insulation of the side walls and complete filling of the vias ( 10 ) with metal ( 11 ), - making backside contacts of the chips ( 2 . 3 by depositing a first photodielectric layer ( 19 ) on the wafer backside, - forming an opening in this layer over the vias ( 10 ), - metallizing the wafer backside and structuring the metallization ( 14 ) for forming a rewiring, which with the metal filling ( 11 ) of the vias ( 10 ), - applying a second photodielectric layer ( 20 ) and performing a lithography process on that backside contact making layer, and - forming a metal layer (UBM 15 . 16 ) on the backside contacts and creating solder bumps ( 17 on this layer, dicing the chips by sawing the wafer along the aforementioned saw tracks such that metal remaining after sawing on the sidewalls of the vias and on the sidewalls of the recesses in the chip top makes an electrical connection between the back side contacts with the solder bumps and the solder bumps Creating contact pads on the chip front. A method according to claim 1, characterized in that the opening of the etching window for the production of vias ( 10 ) is carried out by dry etching. A method according to claim 1, characterized in that the opening of the etching mask for the production of vias ( 10 ) is carried out by wet chemical etching. Method according to claim 1, characterized in that the production of the vias ( 10 ) is performed by anisotropic dry etching at a high etching rate. Method according to one of the preceding claims, characterized in that the Seitenwandpasivierung ( 18 ) of the vias ( 10 ) by plasma assisted oxidation or plasma assisted silicon nitride generation. Method according to claim 5, characterized in that the sidewall passivation ( 18 ) is produced from a combination of sequentially deposited silicon oxide and silicon nitride layers with plasma-enhanced vapor deposition. Method according to one of claims 1 to 6, characterized in that the vias ( 10 ) are first coated with TiN or TaN as a barrier layer and then coated by tungsten CVD and then filled with Cu by electroless or electrodeposition. Method according to one of claims 1 to 6, characterized in that the inner walls of the vias ( 10 ) are germinated by a Cu-CVD method and filled with Cu by electroless or electrodeposition. Method according to one of claims 1 to 6, characterized in that the vias are filled with an Al laser method or Cu laser CVD method with Al or Cu. A method according to claim 1, characterized in that the first photo-dielectric layer is activated for the preparation of the subsequent metal deposition. A method according to claim 1, characterized in that the metal layer is prepared by electroless plating. Method according to claim 1, characterized in that the UBM ( 15 . 16 ) consists of a nickel / Glold layer. A method according to claim 12, characterized in that the nickel layer is produced by electroless plating. A method according to claim 12 and 13, characterized in that the gold layer is deposited by an Au immersion process. Method according to one of claims 1 to 14, characterized in that for the production of Lötbumps ( 17 stencil printing first Lotdepots on the UBM ( 15 . 16 ) are applied, which are formed in a subsequent reflow process to solder bumps or solder bumps.

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