DE102005002023B4 - Semiconductor structure with vertical JFET - Google Patents

Abstract

Semiconductor structure (10) having an integrated vertical junction field effect transistor (JFET) in which the current flow direction of the drain current (I _D ) is vertical from a surface to a depth of a semiconductor body (11),
- with the semiconductor body (11), which contains at least one inner zone (16) of a first conductivity type, within the at least one source zone (22) of the first conductivity type and at least one gate electrode zone (23) of a second conductivity type, which on a first surface ( 15) of the semiconductor body (11) are embedded in the inner zone (16), are arranged,
- With a first dielectric layer (13), which is arranged for electrical insulation of the semiconductor body (11) in the vertical direction (X) on a second surface (14) of the semiconductor body (11) at least in the region outside the inner zone (16)
- With a carrier wafer (12), which is connected to the semiconductor body (11) via the first dielectric layer (13), wherein the carrier wafer (12) has at least one through-recess (19, 27) in the region of the inner zone (16), about which the inner zone ...

Description

The The invention relates to a semiconductor structure with integrated vertical JFET (JFET).

Junction field effect transistors (JFET), which due to their function in the literature often as Junction field effect transistors are called are in one Variety of different embodiments and variants widely known. Junction field effect transistors, hereinafter short as JFET transistors or JFETs are field-effect controllable transistors. Different from other field effect controllable transistors (e.g., MOSFETs) in a JFET transistor, the current in the transistor channel does not through the height controlled by an energy barrier, but by a change the current flow geometry. In a JFET transistor, therefore, the cross-sectional area, through which a current can flow varied by the application of a control voltage.

JFET transistors are also characterized by the controllable space charge zone very low capacities, especially very low Miller capacities. Because of that and due to the fact the JFET transistors operated with majority carriers are suitable, JFET transistors and semiconductor circuits having JFET transistors everything for the operation at relatively high frequencies.

at a JFET transistor is generally a self-conducting, so-called normally-on semiconductor switch, which is thus at a Gate control potential of 0 volts is in the on state. Therefore, JFET transistors typically have a low on-resistance RDSon on. Only by applying a negative voltage between Drain and gate, the JFET transistor depends on the amount of applied Voltage as well as dependent increasingly switched off by the potential applied to the source terminal. This is called a constricting effect through the space charge zone. Due to the low on-resistance, JFET transistors are suitable especially for Such applications, in which one as possible when switched on low voltage over the current leading Channel should fall, so as to minimize the power loss to obtain.

For the production conventional JFET transistors is a relatively high-doped and therefore relatively basic substrate low-resistance semiconductor substrate used. On the high-doped semiconductor substrate For example, epitaxy then becomes a thin semiconductor layer thereof Applied line type, which then for the current-carrying Channel is provided. Due to the very high doping of the semiconductor substrate Although its influence on the on-resistance is relatively low, However, it is becoming more and more prevalent, especially at high voltages. Especially for for However, high-voltage JFET transistors always exist the need to keep the on-state resistance as low as possible, because here already a low on-resistance to a sometimes unacceptably high power loss can lead.

JFET transistors can be designed as lateral or vertical JFET transistors. The present invention relates to vertical JFET transistors. vertical JFET transistors face lateral JFET transistors the advantage that they are much more space-saving to produce. For vertical JFET transistors, the current flow direction of the Drain current in the ideal case vertically, so from a surface in the Depth of the semiconductor body. Indeed flows typically always one too - albeit also lower - electricity in lateral direction.

It thus always comes to a parasitic leakage in lateral Direction and thus to a voltage drop, especially at very high frequencies and / or at high leakage currents to a significant Energy loss leads. This more so when the vertical JFET transistor in lateral Direction of a semiconductor material of the opposite conductivity type and thus of a parasitic pn junction is surrounded. For vertical JFET transistors, therefore, there is always also the need for one as possible good, in particular lateral isolation of the corresponding JFET structures.

at usual Semiconductor devices where multiple vertical JFET transistors in one Semiconductor body are arranged parallel to each other, due to the common, highly doped semiconductor substrate, the individual JFET transistors only via a large-area backside contact be contacted. A direct contact (back contact or drain contact) one or more individual JFET transistors is conventional vertical JFET transistor arrangements without further action not or technologically only extremely complicated realizable.

From the US 4,205,344 For example, a vertical junction field effect transistor is known. Laterally, the junction field effect transistor is isolated by deep trenches of silicon dioxide. The junction field effect transistor further comprises a buried n ⁺ doped layer. Against the p-doped semiconductor substrate, the junction field effect transistor is poled by a reverse-biased Isolated PN junction. Also from the US 6,084,284 A For example, a junction field effect transistor is known.

From the DE 38 50 855 T2 For example, a MOSFET is known that has a backside contact for the drain. To enable backside contact, a deep n ^{+ region of} the drain is provided within a p-substrate. From WO 2004/053993 A1 a vertical DMOSFET is known, which has a back side contact for the drain connection. Furthermore, the DMOSFET has a P-type substrate. From the US 4,845,051 For example, a JFET transistor is known as a device whose drain extends vertically through a semiconductor wafer. The JFET transistor has a plurality of individual transistors with a common drain.

Of the present invention is based on the object, the influence parasitic To reduce elements in a JFET transistor as possible.

According to the invention this Task by a semiconductor structure with the features of the claim 1 solved.

It is accordingly a semiconductor structure with an integrated vertical junction field effect transistor (JFET), in which the current flow direction of the drain current vertically from a surface into a depth of a semiconductor body is.

The Semiconductor structure comprises a semiconductor body having at least one Contains inner zone of a first conductivity type, within the at least one Source zone of the first conductivity type and at least one gate electrode zone a second conductivity type, which at a first surface of the semiconductor body in the inner zone are embedded, are arranged.

The Semiconductor structure has a first dielectric layer, that for the electrical insulation of the semiconductor body in the vertical direction on a second surface of the semiconductor body at least outside the inner zone is arranged.

The Semiconductor structure has a carrier wafer which is connected to the semiconductor body via the first dielectric layer is connected, wherein the carrier beetle at least has a continuous recess in the region of the inner zone, via which the inner zone from the side of the second surface by means of a drain contact electrode directly contacted.

The Semiconductor structure has a second dielectric layer, which completely encloses the inner zone in the lateral direction. there has the vertical junction field effect transistor (JFET) no parasitic Substrate drain diode on.

A Through recess in the region of the inner zone, which is the active Forming areas of the JFET semiconductor structure means that at one exposed, back surface the inner zone over this the continuous recesses from the back of the semiconductor structure are contactable, i. that the recesses in vertical Direction just below the exposed surface of the Inner zone are arranged.

Compared to conventional field-effect-controlled semiconductor switches, such as a DMOS transistor, the JFET transistor according to the invention now has no parasitic substrate-drain diode in the vertical direction, since the drain electrode directly to the active layer, ie directly to the inner zone is applied. This brings with it considerable advantages:
Due to the complete absence of a semiconductor substrate (bulk material), the drain contact electrode can be applied directly to the active region and thus directly to those regions of the semiconductor body that are provided for the formation of the current-carrying channel. Although the semiconductor substrate (bulk) is doped much higher and thus formed with lower impedance than the inner zone, but this semiconductor substrate is typically formed much thicker than the inner zone.

The Semiconductor substrate carries therefore even with conventional JFET transistor structures, which use a highly doped semiconductor substrate (bulk), a significant contribution to the on-resistance (RDSon) at and affected negative the high frequency characteristics of the JFET transistor. By the full Absence of this semiconductor substrate (bulk) depends on its doping a significant reduction of the on-resistance RDSon, typically by a factor of 3 to 10 or more.

Due to this much lower on-resistance and the concomitant significant reduction of switching-related losses, small leakage currents, which may possibly result from a parasitic pn diode between the inner zone and the gate contact electrode, are tolerated. It is essential in this connection that, in particular for high-power applications, the lowest possible turn-on resistance is absolutely necessary in order to ensure that as low a voltage as possible falls above the current-carrying channel when the circuit breaker is switched on so that the power switch has the lowest possible power loss. A possible advantage of the present invention is that due to a clotting gen Einschaltwiderstandes this semiconductor device low power loss is ensured in the switched-on operation.

Thereby, that the drain metallization directly on the active layer, ie is applied directly to the inner zone, can be so individual, several single or all JFET transistors directly over the back Contact the semiconductor structure. That is, the backside metallization (drain contact electrode) can be over the entire surface be applied or structured. A structured Back side metallization allows one or more individual vertical JFET transistors individually to contact and integrate in a smart power technology.

By enclosing the inner zone through at least the second dielectric layer becomes the JFET semiconductor structure in the lateral direction completely against the surrounding material of the semiconductor body and the carrier wafer isolated. Under lateral isolation is here and in the whole Each patent application to understand such an insulation, the the respective inner zone at their, with respect to the first surface lateral Completely enclosing pages and thus lateral completely electrically isolated. So there is no parasitic pn junction in the lateral direction to an adjacent to the inner zone, in which the JFET structure is arranged Semiconductor region.

beneficial Refinements and developments of the invention are the dependent claims and the description with reference to the drawings.

In In a very advantageous further development, several, over each other second dielectric layers laterally insulated inner zones provided. In each of these inner zones, each one sort of defines a single transistor cell of the JFET semiconductor structure, For example, each a single JFET transistor, any another semiconductor device (e.g., a MOSFET, an IGBT, a bipolar transistor, etc.) or any integrated circuit.

In a typical embodiment form the semiconductor body, the first dielectric layer and the carrier wafer together an SOI structure. This is typically on the back of the semiconductor body applied or grown dielectric (first dielectric Layer), for example, by wafer bonding with the specially provided carrier wafer mechanically fixed, i. undetachably connected under operating conditions.

typically, the source zone has a much higher doping concentration as the corresponding inner zone in which it is embedded, for example an at least a factor of 100 higher doping concentration.

In a very advantageous development in the case of several arranged in the semiconductor body Inner zones these from the side of the second surface (back) over here contacted a single continuous drain contact electrode over a large area. This large-area contacting covers so that the entire back surface the semiconductor structure, so both the exposed surfaces of the respective inner zones, as well as the carrier wafer, and thus allows simultaneous contacting of all at this drain contact electrode Connected inner zones or semiconductor areas.

In an alternative, also very advantageous development in the case of a plurality of inner zones arranged in the semiconductor body a structured drain contact electrode provided. This structured Drain contact electrode has a plurality of contact areas, by means of each of which one or more inner zones can be contacted independently are. In this way, each one can be very beneficial Inner zone decided by a just for this inner zone Discharge contact electrode to be contacted.

Of the possible The advantage of this is that this creates vertical structures in the same Integrate semiconductor body but they are more or less independent of each other can be operated. In particular, you can in this way, the individual semiconductor devices within a Inner zone, in particular the respective JFET transistors, with a different drain potential are applied, which, for example in a large-area drain contact, at the all drain contacts have the same drain potential would not be possible.

In an advantageous embodiment is the drain contact electrode as a metallization, for example of an electrically conductive metallic material or metal alloy, or as a highly doped, electrically conductive polysilicon layer educated.

In an advantageous embodiment, the within a respective Inner zone disposed source zones and gate electrode zones from each other spaced, in particular laterally offset and spaced. Preferably are the source zones and gate electrode zones arranged within an inner zone Also arranged offset vertically to each other, wherein the gate electrode zones each closer to second surface (Back) and the source zones closer together to the first surface (front side) are arranged.

Especially advantageous in this context, when the gate electrode zones as Buried layers are arranged within the source zones. That way the current is leading Channel particularly effectively and elegantly constricting this implementation for reasons alone the optimal controllability of the vertical JFET transistor especially good. Preferably, between a gate metallization and the gate electrode zones at least partially a third dielectric Layer arranged, the passivation of the gate electrode zones to the first surface serves.

In In a very advantageous embodiment, the drain contact electrodes are over at least a fourth dielectric layer against the carrier wafer completely electrically isolated. In this way it is prevented that between the Drain contact electrode and the carrier wafer a parasitic pn junction, the thus undesirable leakage currents in the carrier wafer can result, trains.

In an advantageous embodiment is at least one of the dielectric Layers as STI structure (STI = shallow trench isolation) and / or as Deep trench structure formed. It can be in very advantageous Way the often anyway for the Producing the JFET transistors or another, located on the semiconductor body integrated circuit required deep trench technology or Use STI technology.

In a technologically very premature embodiment contains at least one of the dielectric layers at least partially a material made of silica, spin on glass, spin on diamond, low k, high k and / or silicon nitride, but of course would be here as well other dielectric materials conceivable.

In a preferred embodiment is in at least one inner zone integrated at least one JFET transistor. Typically, the JFET transistor is self-conducting Transistor (normally-on) formed. In the JFET transistor is the Current leading Channel open if there is no control potential at the gate connection. It would also be possible a self-locking transistor (normally-off). This one can be by a suitable choice of conditions the doping concentrations of the channel region and the source zones and drain zones, over the the space charge zone is determined in the stress-free case, and on the Realize channel width.

In A particularly advantageous application of the invention is the JFET transistor component a smart power JFET transistor. At least one is in the semiconductor body a first semiconductor region and at least one second semiconductor region are provided, wherein in the first semiconductor region as the circuit breaker formed JFET transistor and in the second semiconductor region the logic part of the smart power JFET transistor is arranged. typically, the logic part has an integrated drive circuit for driving of the or designed as a power switch JFET transistors. additionally or alternatively it can also be provided that the logic part at least a protection circuit to protect the smart power JFET transistor against overvoltages, overcurrents, Temperature and the like or any differently designed integrated Circuit, preferably, but not necessarily, with the JFET transistor is coupled.

Smart power semiconductor devices, smart FETs, smart power transistors and the like are each designations for power switches in which power electronics are combined with "intelligence." Smart power devices combine power semiconductors in a modular fashion and the necessary drive for them Such smart-power semiconductor devices are widely known by different designs of the power switch, such as MOSFET, IGBT, JFET, etc., and the corresponding drive logic, protection circuitry, temperature protection, and the like In such smart power devices, there is a particular need to integrate the JFET molded circuit breaker together with the corresponding drive logic on a single semiconductor chip, the power part being from the logic part for driving the circuit breaker isolated as well as possible and thus separated. The background of this requirement is that the power section must be operated at relatively high voltages of, for example, 50-500 volts and more (and high currents in the range of 1-100 A), whereas the components of the logic section which serves to drive the circuit breaker are very low voltages of 3.3 volts, 2.5 volts, 1.8 volts and less (and low currents in the range of a few milliamps). With such low supply voltages and currents of the logic part, there is always the danger that, due to interference coupled externally into the logic part, its functionality may under certain circumstances be adversely affected. Since designed as JFET transistors circuit breaker are especially suitable for very high switching speeds, there is also the particular danger that caused by the high-frequency switching noise undesirably be coupled into the logic part. These disturbances may limit the function of the logic part, causing the JFET to malfunction can be controlled. In extreme cases, this can lead to a failure of the JFET, especially at high switching speeds. To prevent this, the JFET would therefore have to be operated at much lower switching speeds, which would however lose the advantage of high-frequency switching of the JFET. The particular advantage of the present invention is that here in the vertical direction as well as in the lateral direction, ie in the direction of the drive logic, a very good insulation is realized and thus the problems mentioned can not arise. Above all, smart-power JFET circuit breakers designed for high switching speeds can be provided here.

The smart power JFET transistors according to the invention can preferably be used in all applications in which a so-called power management for switching circuit breakers and batteries is required, for example, full bridges, half bridges, high-side switches, low-side switches and the same. The invention is particularly advantageous when used in the motherboard of a computer (PC, laptop, etc.). However, the invention is also suitable in the same way for industrial Applications (industrial application) and in the field of automotive electronics (automotive application).

In another, also advantageous application of the invention are a plurality of electrically coupled first semiconductor regions intended. Furthermore, at least one second semiconductor region is in the semiconductor body provided, wherein in each of the first semiconductor regions at least a JFET transistor is provided, which together to form a full bridge or a half bridge are interconnected. In the second semiconductor region, it is then preferable to but not necessarily, the drive circuit for driving the full bridge or half bridge arranged. In this way, several, over their controlled paths parallel to each other JFET transistors switch and operate individually.

Though This invention is very advantageous in the above Bridge circuits, however would it be also conceivable, a variety of within a single transistor cell arranged JFET transistors based on their controlled routes in parallel, thereby obtaining a higher load current. By the individual JFET transistor cells according to the invention individually are controllable leaves so by selecting all or only certain JFET transistors the load current resulting from the parallel connection is optimal adapt to the respective requirements or needs.

Especially can in those applications where a high load current is required, very many or all parallel JFET transistor cells for the Realization of the desired high load current can be used. In contrast, in the case of a lower Load current only a correspondingly predetermined number of JFET transistor cells, just for This load current is sufficient to be used. The remaining, So the unused JFET transistor cells are then in controlled the off state. That way you can a smart, extraordinary flexible power management via a big Provide service area.

In a very advantageous embodiment of the invention, the Recesses a funnel-shaped Cross-section on. This is especially true for the manufacturing process, So for the generation of the contacts of the side walls of the recesses with the Drain metallization of particular advantage, since the drain metallization in a technologically simple way both on the exposed surfaces of the Inner zone and the back surface of the carrier wafer as well as on the side walls the recesses can be deposited. Conceivable but would be Also, that the recesses have more or less vertical side walls or even rounded side walls can have. In these cases could for example, for contacting the entire recess through the drain metallization filled become.

The Invention will be described below with reference to the schematic figures The drawings specified embodiments explained in more detail. Show it attended:

1 a partial section of a first embodiment of a vertical JFET transistor according to the invention;

2 a partial section of a second embodiment of a vertical smart power JFET transistor arrangement according to the invention, which has a plurality of arranged in the semiconductor body transistor cells each having a JFET transistor;

3 a partial section of a third, particularly preferred embodiment of a vertical smart power JFET transistor arrangement according to the invention, which has a plurality of arranged in the semiconductor body transistor cells each having a JFET transistor.

In all figures of the drawing, identical and functionally identical elements and features - unless otherwise stated - have been provided with the same reference numerals. It goes without saying by itself, that the semiconductor structures of the 1 to 3 not to scale and in particular not represented according to the actual size ratios. In all 1 to 3 the vertical direction is indicated by the arrow X and the lateral direction by the arrow Y.

1 shows a partial section of a first embodiment of a JFET transistor according to the invention. In 1 is with reference numerals 10 a semiconductor device including a JFET semiconductor structure. The semiconductor device 10 has a semiconductor body 11 and a carrier wafer 12 on. The semiconductor body 11 For example, a silicon wafer, a thinned silicon wafer or a part thereof has a back surface 14 and a front surface 15 on. The semiconductor body 11 is with its back surface 14 over a carrier wafer 12 arranged, wherein semiconductor body 11 and carrier wafers 12 by means of a dielectric layer 13 isolated from each other.

The dielectric layer 13 is formed in the present embodiment as an SOI layer (SOI = silicon on insulator) and contains, for example, silicon dioxide. The dielectric layer 13 serves the vertical electrical insulation of the semiconductor body 11 or the structures contained therein against the carrier wafer 12 , The dielectric layer has a thickness of, for example, 100 nm to 2 μm

The carrier wafer 12 itself also serves among other things, the mechanical stability of the semiconductor body 11 , in particular during the processing of the semiconductor body 11 , This is necessary because of the necessity of a very low on-resistance, since the typically very thin, eg 1-5 micron thick semiconductor body 11 in such applications without Trä gerwafer 12 difficult or impossible to process and handle.

In the in 1 shown semiconductor body 11 a single JFET transistor is integrated. Hereinafter, the semiconductor structures of this JFET transistor will be described.

The semiconductor body 11 has a weak n-doped inner zone 16 on. This inner zone 16 contains in the example shown, the structures of a single, designed as a JFET transistor circuit breaker, which is formed in the present embodiment as a self-conducting, so-called "normally on" transistor.

In the present embodiment are around the inner zone 16 deep trenches around 18 intended. These trenches 18 define dielectric areas 18 , which are made for example in a well-known "deep trench" technology. These trenches 18 range from the front surface 15 to the SOI layer 13 between semiconductor body 11 and carrier wafers 12 and there are completely to the SOI layer 13 connected. The trenches 18 are filled with a dielectric, which is typically formed as a spin-on-glass (SOG), spin-on-diamond (SOD) or the like. The dielectric areas 18 enclose the inner zone 16 in the lateral direction Y complete and isolate this inner zone 16 thus in the lateral direction Y completely from the inner zone 16 surrounding areas of the semiconductor body 11 ,

From the side of the surface 15 is an n-doped source region 22 in the inner zone 16 embedded. The source area 22 has a strong n-doping such that its doping concentration is at least significantly higher than that of the surrounding n-doped inner zone 16 , From the side of the surface 15 are also heavily p-doped gate regions 23 in the inner zone 16 embedded. While the source area 22 directly to the surface 15 adjacent, are the gate areas 23 as in the inner zone 16 formed buried layers. In the present embodiment, the gate areas are 23 from the surface 15 about more dielectric areas 30 spaced. The gate areas 23 are further from the source region 22 laterally offset as well as vertically offset and arranged at a distance.

The source area 22 is on the front surface 15 via a source metallization 24 , which is connected to a source terminal S, the gate regions 23 are via a gate metallization 25 , which is connected to a gate terminal G, electrically contacted. In doing so, the gate areas 23 for example via specially provided contact holes 31 in the dielectric areas 30 that in the example in 1 are merely indicated, electrically with the gate metallization 25 be connected.

The carrier wafer 12 has one through the entire carrier wafer 12 through recess 19 on. This recess 19 ranges from a back surface 20 of the carrier wafer 12 to the front surface 21 , In addition, the SOI layer also points 13 a continuous recess 27 in the area above the recess 19 of the carrier wafer 12 on. These two recesses 19 . 27 are in the area of the inner zone 16 arranged so that the inner zone 16 about the recesses 19 . 27 from the back of the semiconductor device 10 can be contacted.

Further, a drain metallization 32 provided on the exposed surfaces 14 ' in the area of the inner zone 16 on this inner zone 16 is applied and thus the inner zone 16 electrically contacted. The drain metallization 32 is large on the back surface 14 ' the inner zone 16 and moreover to the adjacent areas of the SOI layer 13 and the carrier wafer 12 applied. For better contacting is the drain metallization 32 also slightly above the back surface 20 of the carrier wafer 12 above. The drain metallization 32 is connected to a drain terminal D. In the electrical contacting of the inner zone 16 through the drain metallization 32 Care must be taken to ensure that the contact is as ohmic as possible, which in the present case due to the large area on the inner zone 16 applied drain metallization 32 also the case is.

Between the carrier wafer 12 and the drain metallization 32 is a thin dielectric layer 28 intended. This dielectric layer 28 serves the purpose of a parasitic Schottky diode between carrier wafer 12 and drain metallization 32 to prevent.

Source regions 22 , Gate areas 23 , Inner zone 16 and drain metallization 32 thus form the elements of the JFET transistor. The corresponding structures effectively form a vertical transistor cell whose lateral dimensions in 1 with reference number 29 is merely indicated. This transistor cell 29 is in the lateral direction Y over the trenches 18 and the dielectric contained therein 18 electrically isolated and thus against this transistor cell 29 possibly surrounding semiconductor areas, semiconductor devices, integrated circuits and the like isolated.

The shape of the transistor cell 29 is essentially due to the geometry of the current-carrying channel 26 determined, consisting essentially of the areas of the inner zone 16 that are directly between Sourcezone 22 and drain metallization 32 are arranged results. The transistor cell 29 can be round, oval, square, rectangular, strip-shaped, hexagonal, octagonal, meander-shaped, etc. be formed. While the geometry of the transistor cell 29 essentially of the desired geometry of the current-carrying channel 26 , ie in particular of the geometry of the inner zone 16 , the source zone 22 and the gate zones 25 , is determined, the geometry of the drain metallization 32 more or less arbitrary.

While in the embodiment in 1 only a single JFET transistor is shown, refer to the other embodiments in the 2 and 3 to the embodiment of a vertical semiconductor device having a plurality of parallel-connected transistor cells 29 each having a JFET transistor. In the 2 and 3 are exemplary only three transistor cells 29 shown. The structure of these individual transistor cells 29 corresponds essentially to the structure of the individual transistor cell 29 in 1 ,

In 2 are the individual transistor cells 29 arranged parallel to each other, ie, their drain-source load paths are connected in parallel. This means that the respective source terminals S one in a respective transistor cell 29 arranged JFET transistor are short-circuited. In the same way, the respective drain terminals D of these individual JFET transistors are short-circuited with each other. For this purpose, the semiconductor structure 10 a large-scale drain metallization 32 on, the adjacent transistor cells 29 interconnects and thus a single large-scale drain metallization 32 for all transistor cells 29 provides the semiconductor structure.

In contrast to the embodiment in 2 are in 3 the individual JFET transistors within the respective transistor cell 29 not connected in parallel via their drain-source load paths, ie their source terminals S and drain terminals D1-D3 are not short-circuited with each other. In the case of the drain connection D1-D3, this can be realized in a very simple manner according to the invention in that a single transistor cell 29 one each of this transistor cell 29 associated drain metallization 32 does not contain the corresponding drain metallizations 32 the adjacent transistor cells 29 connected is. The same can apply to the corresponding source connections S. However, it would also be conceivable that these individual transistor cells 29 , For example, by a suitable drive circuit, are kurzschließbar via their drain-source load paths. The individual JFET transistors within the respective transistor cell 29 could thus be controlled independently of the adjacent JFET transistors. This can be achieved, for example, in that these individual JFET transistors are each driven separately via a control signal, which is coupled into the gate terminal G.

In contrast to the general embodiment in the 1 is in the semiconductor body 11 in the 2 and 3 integrated a smart power JFET semiconductor device. For this purpose, the semiconductor body 11 first semiconductor regions 17 ' and second semiconductor regions 17 '' on. The first semiconductor areas 17 ' and the second semiconductor regions 17 '' are lateral to each other through the dielectric regions 18 electrically completely isolated from each other. In the first semiconductor areas 17 ' are the transistor cells 29 arranged with the circuit breakers designed as a JFET transistor. In the second semiconductor regions 17 '' is each an integrated circuit 33 provided, for example, contains a drive circuit for driving the JFET transistor or may have any other integrated circuit. The embodiment of this in the second semiconductor region 17 '' arranged integrated circuit 33 is in the 2 and 3 not shown. The embodiment of the integrated circuit 33 can also vary depending on the requirements of the smart power JFET transistors. In particular, this integrated circuit 33 For example, in addition to the known control (driver circuit) and protective circuits for protecting the integrated circuit against overcurrents and overvoltages and a temperature sensor for detecting an overtemperature and a corresponding temperature protection circuit have.

Hereinafter, the operation of a normally-on JFET transistor according to the invention according to the 1 to 3 briefly explained: In the linear region of the transistor characteristic, ie in the event that between gate terminal G and source terminal S no voltage is applied, the transistor channel is open. When a voltage is applied between the source terminal S and the drain terminal D, the maximum drain current ID flows. This drain current ID then depends only on the magnitude of the voltage difference between the source terminal S and the drain terminal D. If a negative potential with respect to the source terminal S is applied to the gate terminal G, then a space charge zone is formed around the p-doped gate electrode, which channel carries the current 26 increasingly constricting with increasing potential of the gate terminal G. This is referred to as a so-called "pinch off" (constriction) of the current-carrying channel 26 , At a sufficiently high drain-gate voltage, this space charge region (barrier layer) at the drain-side electrode fills the entire current-carrying channel 26 out. The potential in the current-carrying channel 26 thus no longer depends on the drain potential. A further increase in the drain potential then no longer leads to a higher drain current ID. With sufficient negative gate potential, the space charge zone is in the entire current carrying channel 26 so spread that no power-leading channel at all 26 can train. Thus, no drain current ID flows regardless of the level of the drain potential.

The doping concentration in the n-doped inner zone 16 and in particular in the region of the current-carrying channel 26 defines the current carrying capacity of the JFET transistor.

Although the present invention above based on a preferred embodiment It is not limited to this, but in many ways and modifiable.

Thus, the present invention is not limited to the specific, on the basis of 1 to 3 limited embodiments shown. Rather, by exchanging the conductivity types n (first conductivity type) with p (second conductivity type) and vice versa and / or by varying the doping concentrations, a multiplicity of different circuit variants and semiconductor topographies can be provided there.

So Also, the present invention is not limited to the above materials for the dielectric layers, semiconductor layers and layer sequences limited, which have been given only for the sake of clarity. Rather, you can here also more, additional Layers can be used or it can, if it makes sense optionally also on individual dielectric layers and semiconductor structures be waived.

In the present embodiments have been for lateral and vertical isolation STI structures, deep trench structures and an SOI layer were used. It goes without saying that to the lateral or vertical insulation and any other dielectric layers and structures could be used, although the use the STI technology and deep trench technology is particularly advantageous.

Further was in the embodiments the JFET semiconductor structure formed symmetrically, but without the To limit the invention. It goes without saying that, in addition, the drain regions and source regions and / or Source areas and gate areas can be interchanged without that of the fundamental Function of the JFET transistor would be deviated.

The Metallizations for contacting the gate region, the source region and the drainage area included in the present embodiment one for the semiconductor technology suitable metal (for example, aluminum, Copper, gold, tungsten, etc.) or a corresponding metal alloy. These contacts could but of course also be designed as highly doped polysilicon contacts, what especially in technological terms due to the process technology easy manufacturability of poly silicon and its electrical and physical properties is beneficial.

10

Semiconductor devices (with smart power JFET)

11

Semiconductor body, silicon wafer

12

carrier wafer

13

dielectric Layer, SOI layer

14

rear surface

14 '

Surface in the area the recess of the carrier wafer

15

front surface

16

inner zone

17 '

first Semiconductor regions

17 ''

second Semiconductor regions

18

dielectric Area, deep trench with dielectric

19

recess (in the carrier wafer)

20

rear surface

21

front surface

22

Source regions, source zone

23

Gate regions, Gate electrode zone

24

source metallization

25

gate metallization

26

electricity leading channel

27

recess (in the SOI layer)

28

dielectric layer

29

transistor cell

30

dielectric areas

31

vias

32

drain metallization, Drain contact electrode

33

integrated circuit

ID

drain current

G

gate terminal

D

drain

D1-D3

drains

S

source terminal

X

vertical direction

 Y

lateral direction

Claims (19)

Semiconductor structure ( 10 comprising an integrated vertical junction field-effect transistor (JFET) in which the current flow direction of the drain current (I _D ) vertically from a surface to a depth of a semiconductor body ( 11 ), - with the semiconductor body ( 11 ), the at least one inner zone ( 16 ) of a first conductivity type within which at least one source zone ( 22 ) of the first conductivity type and at least one gate electrode zone ( 23 ) of a second conductivity type, which at a first surface ( 15 ) of the semiconductor body ( 11 ) into the inner zone ( 16 ) are arranged, with a first dielectric layer ( 13 ), for the electrical insulation of the semiconductor body ( 11 ) in the vertical direction (X) on a second surface ( 14 ) of the semiconductor body ( 11 ) at least in the region outside the inner zone ( 16 ), - with a carrier wafer ( 12 ) connected to the semiconductor body ( 11 ) over the first dielectric layer ( 13 ), wherein the carrier wafer ( 12 ) at least one continuous recess ( 19 . 27 ) in the region of the inner zone ( 16 ), over which the inner zone ( 16 ) from the side of the second surface ( 14 ) by means of a drain contact electrode ( 32 ) is directly contacted, - with a second dielectric layer ( 18 ), which is the inner zone ( 16 ) in the lateral direction (Y) completely, wherein the vertical junction field effect transistor (JFET) has no parasitic substrate-drain diode. Semiconductor structure according to Claim 1, in which in the semiconductor body ( 11 ) a plurality of one another via second dielectric layers ( 18 ) laterally isolated inner zones ( 16 ) are provided. Semiconductor structure according to one of the preceding claims, in which the semiconductor body ( 11 ), the first dielectric layer ( 13 ) and the carrier wafer ( 12 ) together form an SOI structure. Semiconductor structure according to one of the preceding claims, in which the source zone ( 22 ) a much higher doping concentration than the corresponding inner zone ( 16 ), in which it is arranged. Semiconductor structure according to one of the preceding claims, in which in the semiconductor body ( 11 ) several inner zones ( 16 ) are arranged and in which these inner zones ( 16 ) from the side of the second surface ( 14 ) via a single continuous drain contact electrode ( 32 ) are contacted over a large area. Semiconductor structure according to one of Claims 1 to 4, in which in the semiconductor body ( 11 ) several inner zones ( 16 ) and in which a structured drain contact electrode ( 32 ), which has several contact areas ( 32 ), by means of which in each case one or more of the inner zones ( 16 ) independent of one or more other inner zones ( 16 ) are contacted over a large area. A semiconductor structure according to any one of claims 5 or 6, wherein the drain contact electrode ( 32 ) is formed as a metallization or as a highly doped polysilicon layer. Semiconductor structure according to one of the preceding claims, in which the inside of a respective inner zone ( 16 ) arranged source zones ( 22 ) and gate electrode zones ( 23 ) spaced apart, in particular laterally offset and spaced, are arranged. A semiconductor structure according to any one of the preceding claims, wherein the inside of an inner zone ( 16 ) arranged source zones ( 22 ) and gate electrode zones ( 23 ) are arranged vertically offset from each other, wherein the gate electrode zones ( 23 ) closer to the second surface ( 14 ) and the source zones ( 22 ) closer to the first surface ( 15 ) are arranged. A semiconductor structure according to any one of the preceding claims, wherein between a gate metallization ( 25 ) and the gate electrode zone ( 23 ) at least partially a third dielectric layer ( 30 ) is arranged. A semiconductor structure according to any one of claims 4 to 10, wherein the drain contact electrode ( 32 ) via a fourth dielectric layer ( 28 ) completely electrically against the carrier wafer ( 12 ) is isolated. Semiconductor structure according to one of the preceding claims, in which at least one of the dielectric layers ( 13 . 18 . 28 . 30 ) is designed as an STI structure and / or as a deep trench structure. Semiconductor structure according to one of the preceding claims, in which at least one of the dielectric layers ( 13 . 18 . 28 . 30 ) Contains silicon dioxide, spin on glass, spin on diamond, low K, high K and / or silicon nitride. Semiconductor structure according to one of the preceding Claims, in which the junction field effect transistor is a self-conducting (normally-on) transistor is formed. Semiconductor structure according to one of the preceding Claims, in which the junction field effect transistor is a smart power junction field effect transistor is trained. A semiconductor structure according to claim 15, wherein in the semiconductor body ( 11 ) at least one first semiconductor region ( 17 ' ) and at least one second semiconductor region ( 17 '' ) is provided, wherein in the first semiconductor region ( 17 ' ) the barrier layer field effect transistor designed as a power switch and in the second semiconductor region ( 17 '' ) the logic part ( 33 ) of the smart power junction field effect transistor is arranged. A semiconductor structure according to claim 16, wherein the logic part comprises an integrated drive circuit ( 33 ) for controlling the barrier layer field effect transistor designed as a power switch and / or at least one protective circuit ( 33 ) to protect the smart power junction field effect transistor against overvoltages, overcurrents or temperature. Semiconductor structure according to one of the preceding claims, in which a plurality of first semiconductor conductor regions ( 17 ' ) and in which at least one second semiconductor region ( 17 '' ) is provided in the semiconductor body, wherein in each of the first semiconductor regions ( 17 ' ) at least one junction field effect transistor (JFET) is arranged, which are connected together to form a full bridge or half bridge, and wherein in the second semiconductor region (FIG. 17 '' ) a drive circuit ( 33 ) is arranged to control the full bridge or the half bridge. Semiconductor structure according to one of the preceding claims, in which at least one recess ( 19 . 27 ) has a funnel-shaped cross-section.