DE102004059884A1 - Microchip, e.g. heterojunction bipolar transistor, flip-chip mounting method, involves coating surfaces of microchips, with gold-tin-solder, where chips are soldered by heating of arrangement along with substrate - Google Patents
Microchip, e.g. heterojunction bipolar transistor, flip-chip mounting method, involves coating surfaces of microchips, with gold-tin-solder, where chips are soldered by heating of arrangement along with substrate Download PDFInfo
- Publication number
- DE102004059884A1 DE102004059884A1 DE102004059884A DE102004059884A DE102004059884A1 DE 102004059884 A1 DE102004059884 A1 DE 102004059884A1 DE 102004059884 A DE102004059884 A DE 102004059884A DE 102004059884 A DE102004059884 A DE 102004059884A DE 102004059884 A1 DE102004059884 A1 DE 102004059884A1
- Authority
- DE
- Germany
- Prior art keywords
- carrier
- chip
- solder
- flip
- heat dissipation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Abstract
Description
Die Erfindung betrifft ein Verfahren zur Flip-Chip-Montage von Mikrochips, beispielsweise Leistungs-Bipolartransistoren, auf einen Träger aus thermisch gut leitfähigem Material sowie eine mit dem Verfahren hergestellte elektronische Baugruppe.The The invention relates to a method for flip-chip mounting of microchips, for example, power bipolar transistors, on a carrier of thermal good conductive Material and an electronic produced by the method Assembly.
Bei der konventionellen Montage von Flip-Chip-Halbleiterbauelementen werden diese mit ihren Anschlusskontakten auf die Leiterbahnstruktur eines Trägers (submount) aufgelötet. Dabei setzen die Anschlusskontakte der Halbleiterbauelemente auf entsprechende Leiterbahn-Endbereiche (Kontaktpads) auf. Die Lötverbindungen zwischen den Anschlusskontakten des Halbleiterbauelements und den Kontaktpads auf dem Träger werden durch sogenannte Bumps realisiert, das heißt kleine Lotflächen oder Kügelchen (Lötmetallhöcker), die zuvor auf das Bauelement und/oder den Träger aufgebracht worden sind. Die Bumps sind etwa 80–100 μm hoch. Das Löten erfolgt mittels eines Wärme-Druck-Verfahrens (Wärmedruckbonden) bei etwa 200–300°C. Die Kontaktverbindung hat den Vorteil, dass die Elektroden des Bauelements direkt, also ohne zusätzliche Drahtverbindung, mit dem Träger kontaktiert werden.at the conventional assembly of flip-chip semiconductor devices These are with their connection contacts on the trace structure of a carrier (submount) soldered. In this case, the connection contacts of the semiconductor components set corresponding conductor end areas (contact pads) on. The solder joints between the terminal contacts of the semiconductor device and the Contact pads on the carrier are realized by so-called bumps, that is small Solder surfaces or globule (Solder bumps), the previously applied to the device and / or the carrier. The bumps are about 80-100 μm high. The soldering takes place by means of a heat-pressure-process (heat pressure bonding) at about 200-300 ° C. The contact connection has the advantage that the electrodes of the device directly, so without additional Wire connection, with the carrier be contacted.
Die Lötverbindungen mittels der Bumps haben zwar eine hohe Abscherfestigkeit, aber nur eine ungenügende thermische Leitfähigkeit, so dass weitere Maßnahmen zur Abführung der beim Betrieb des Bauelements entstehenden Wärme getroffen werden müssen. Leistungs-Bipolartransistoren werden deshalb „abgedünnt", das heißt, dass der Träger nach dem Aufbringen der elektrisch aktiven Schichten in seiner Dicke reduziert wird.The solder connections Although using the bumps have a high shearing resistance, but only an insufficient one thermal conductivity, so that further action to the exhaustion the heat generated during operation of the device must be taken. Performance bipolar transistors are therefore "thinned", that is, that the carrier after the application of the electrically active layers in its thickness is reduced.
Es ist auch bekannt, den aufgrund der Bumps zwischen Bauelement und Träger verbleibenden Zwischenraum zur Erhöhung der mechanischen Stabilität und in geringerem Maße auch zur Erhöhung der thermischen Leitfähigkeit mit einem Füllmaterial aufzufüllen. Beispielsweise zeigt US 2004/0185603 A1 eine Flip-Chip-Anordnung mit einem solchen Füllmaterial. Dieses Füllmaterial ist jedoch nicht zu einer deutlich effizienten Verbesserung der Wärmeabführung geeignet und außerdem bei Mikrowellentransistoren wegen der damit verbundenen erhöhten kapazitiven Belastung problematisch.It is also known due to the bumps between component and carrier remaining gap to increase the mechanical stability and in lesser degree also to increase the thermal conductivity to fill with a filling material. For example shows a flip-chip arrangement with such a US 2004/0185603 A1 Filling material. This filling material However, this does not lead to a significant improvement in the efficiency Heat dissipation suitable and also in microwave transistors because of the associated increased capacitive Burden problematic.
Die möglichst effiziente Abführung der beim Betrieb entstehenden Verlustwärme ist eine wesentliche Voraussetzung, um die volle Leistungsfähigkeit von Leistungs-Bipolartransistoren und anderen Mikrowellen-Leistungsbauelementen zu erreichen.The preferably efficient exhaustion the loss of heat generated during operation is an essential prerequisite to the full capacity of Power bipolar transistors and other microwave power devices to reach.
Der Erfindung liegt deshalb die Aufgabe zugrunde, ein Verfahren für eine kostengünstige und thermisch effiziente Montage von Mikrochips wie Leistungstransistoren auf einen Träger (submount) sowie eine mit dem Verfahren hergestellte elektronische Baugruppe anzugeben.Of the The invention is therefore based on the object, a method for a cost and thermally efficient assembly of microchips such as power transistors on a carrier (submount) and an electronic produced by the method Specify module.
Erfindungsgemäß wird die Aufgabe gelöst durch die Merkmale der Ansprüche 1 und 8. Zweckmäßige Ausgestaltungen sind Gegenstand der Unteransprüche.According to the invention Task solved by the features of the claims 1 and 8. Expedient refinements are the subject of the dependent claims.
Danach wird
- – der Chip an seinen Anschlusskontakten, den Oberflächen seiner Aktivschichten einschließlich der z.B. von Verbindungsleitern gebildeten Wärmeableitungsflächen an seiner Oberfläche koplanar mit einer 10–20μm dicken Goldschicht versehen
- – der Träger an Lotflächen, die den Kontaktflächen, den Oberflächen der Aktivschichten und den Wärmeleitungsflächen an der Oberfläche des Mikrochips gegenüberliegen und deren Flächen im wesentlichen jeweils der gesamten Fläche dieser Kontaktflächen und den Oberflächen der Aktivschichten einschließlich der übrigen Wärmeableitungsflächen entsprechen, in einer Dicke mit AuSn-Lot beschichtet, die größer ist als die Rauhigkeitsunterschiede und die Planaritätsunterschiede der Goldschicht des Chips
- – der Chip in Flip-Chip-Lage auf den Träger aufgesetzt
- – der Chip durch Erhitzen der Anordnung mit dem Träger verlötet.
- - The chip at its terminal contacts, the surfaces of its active layers including the heat dissipation surfaces formed for example by connecting conductors on its surface coplanar with a 10-20μm thick gold layer provided
- - The support at solder surfaces, which are opposite to the contact surfaces, the surfaces of the active layers and the heat conduction surfaces on the surface of the microchip and their surfaces substantially corresponding to the total area of these contact surfaces and the surfaces of the active layers including the other heat dissipation surfaces, in a thickness with AuSn Solder, which is larger than the roughness differences and the planarity differences of the gold layer of the chip
- - The chip placed in a flip-chip layer on the support
- - Soldered the chip by heating the assembly with the carrier.
Eine mit dem Verfahren hergestellte elektronische Baugruppe ist so ausgebildet, dass der Chip an seinen Anschlusskontakten und den Oberflächen seiner Aktivschichten einschließlich der Wärmeableitungsflächen an seiner Oberfläche koplanar mit einer 10–20μm dicken Goldschicht versehen und auf Lotflächen eines Trägers gelötet ist, die den Kontaktflächen, Oberflächen der Aktivschichten und den Wärmeableitungsflächen an der Oberfläche des Mikrochips gegenüberliegen und deren Flächen jeweils der gesamten Fläche dieser Kontaktflächen und den Oberflächen der Aktivschichten einschließlich seiner übrigen Wärmeableitungsflächen entsprechen.A electronic assembly made by the method is designed to that the chip is connected to its terminals and the surfaces of its Active layers including the heat dissipation surfaces its surface coplanar with a 10-20μm thick Gold layer provided and soldered to solder surfaces of a carrier, the contact surfaces, surfaces the active layers and the heat dissipation surfaces the surface opposite to the microchip and their surfaces each of the entire area these contact surfaces and the surfaces including the active layers his remaining Heat dissipation surfaces correspond.
Die wesentlichen Unterschiede zu dem allgemein üblichen Flip-Chip-Bonden wie z.B. mittels Thermokompression sind:
- – die Lotverbindung ist im Gegensatz zu bisher bekannten Verfahren nicht auf kleine Lotflächen (Bumps) beschränkt, da das Verfahren die simultane Verlötung von groß- und kleinflächigen Kontaktstrukturen ermöglicht
- – die verlöteten Flächen bewirken nicht nur eine elektrische Kontaktierung, sondern es werden gleichzeitig thermisch aktive Verbindungen erzeugt
- – es werden keine Lotflächen auf den Mikrochip aufgebracht wie z.B. die Bumps, sondern es wird eine funktionelle Goldschicht großflächig und mit einer bestimmten Mindestdicke koplanar auf Kontaktflächen an der Chipoberfläche, darunter auch dort, wo eine leitende Verbindung für die intrinsische Funktionsfähigkeit des Transistors notwendig ist (beispielsweise eine Luftbrücke), für die Verbindung zum Träger benutzt.
- - The solder joint is not limited to small solder surfaces (bumps) in contrast to previously known methods, since the method allows the simultaneous soldering of large and small contact structures
- - the soldered surfaces do not just cause one electrical contact, but it is simultaneously generated thermally active compounds
- No solder surfaces are applied to the microchip such as the bumps, but a functional gold layer is coplanar over a large area and with a certain minimum thickness on contact surfaces on the chip surface, including where a conductive connection is necessary for the intrinsic functionality of the transistor ( for example, an air bridge), used for the connection to the carrier.
Die im Chip entstehende Wärme wird durch die erfindungsgemäße Bauweise nunmehr zum größten Teil an den Träger weitergegeben und kann von dort großflächig abgeführt werden. Ein Abdünnen von Bauelementen ist nicht mehr nötig. Außerdem entfällt die Rückseitenmetallisierung des Bauelements.The Heat generated in the chip is due to the construction of the invention now for the most part to the carrier passed on and can be removed from there large area. A thinning of Components is no longer necessary. Furthermore deleted the backside metallization of the component.
Dank der besseren Wärmeabführung kann ein Transistor mit einer deutlich erhöhten (etwa Faktor 2) Verlustleistung betrieben werden (je nach Größe der Emitterfläche bis zu 400 kW/cm2).Thanks to the better heat dissipation, a transistor can be operated with a significantly increased (about factor 2) power loss (depending on the size of the emitter surface up to 400 kW / cm 2 ).
Das Verfahren eröffnet die Möglichkeit, den Lötprozess über eine elektrothermische Messung des thermischen Widerstandes der Transistor-Träger-Anordnung zu qualifizieren. Die hierfür benutzte Methode beruht auf der temperaturabhängigen Änderung der Transistorkennlinien. Die Messung kann gleichzeitig mit der Funktionsprüfung des Bauelements durchgeführt werden. Auf diese Weise ist eine kostengünstige und effiziente Beurteilung der Lötung und der Funktionsfähigkeit des Bauelements möglich.The Procedure opened the possibility, the soldering process over one electrothermal measurement of the thermal resistance of the transistor-carrier arrangement to qualify. The one for this The method used is based on the temperature-dependent change of the transistor characteristics. The measurement can be done simultaneously with the functional test of the Component performed become. In this way is a cost effective and efficient assessment the soldering and the functionality of the component possible.
Die Erfindung soll nachstehend anhand von Ausführungsbeispielen näher erläutert werden. In den zugehörigen Zeichnungen zeigen The Invention will be explained below with reference to exemplary embodiments. In the associated Drawings show
Da
der Träger
Mit
einem Träger
- 11
- Trägercarrier
- 22
- Lotflächensolder surfaces
- 33
- Kontaktflächencontact surfaces
- 44
- Transistortransistor
- 55
- Goldschichtgold layer
- 66
- Luftbrückeairlift
- 77
- BasisBase
- 88th
- Emitteremitter
- 99
- Kollektorcollector
- 1010
- Flächensurfaces
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004059884A DE102004059884A1 (en) | 2004-12-10 | 2004-12-10 | Microchip, e.g. heterojunction bipolar transistor, flip-chip mounting method, involves coating surfaces of microchips, with gold-tin-solder, where chips are soldered by heating of arrangement along with substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004059884A DE102004059884A1 (en) | 2004-12-10 | 2004-12-10 | Microchip, e.g. heterojunction bipolar transistor, flip-chip mounting method, involves coating surfaces of microchips, with gold-tin-solder, where chips are soldered by heating of arrangement along with substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102004059884A1 true DE102004059884A1 (en) | 2006-06-29 |
Family
ID=36580089
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102004059884A Ceased DE102004059884A1 (en) | 2004-12-10 | 2004-12-10 | Microchip, e.g. heterojunction bipolar transistor, flip-chip mounting method, involves coating surfaces of microchips, with gold-tin-solder, where chips are soldered by heating of arrangement along with substrate |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE102004059884A1 (en) |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5373185A (en) * | 1992-09-18 | 1994-12-13 | Sharp Kabushiki Kaisha | Multilayer vertical transistor having an overlay electrode connected to the top layer of the transistor and to the transistor substrate |
EP0663693A1 (en) * | 1993-11-30 | 1995-07-19 | Texas Instruments Incorporated | Low thermal impedance integrated circuit |
US5532512A (en) * | 1994-10-03 | 1996-07-02 | General Electric Company | Direct stacked and flip chip power semiconductor device structures |
DE19507547C2 (en) * | 1995-03-03 | 1997-12-11 | Siemens Ag | Method of assembling chips |
US5717231A (en) * | 1994-08-31 | 1998-02-10 | Texas Instruments Incorporated | Antenna having elements with improved thermal impedance |
US5939739A (en) * | 1996-05-31 | 1999-08-17 | The Whitaker Corporation | Separation of thermal and electrical paths in flip chip ballasted power heterojunction bipolar transistors |
DE19956903A1 (en) * | 1999-11-26 | 2001-05-31 | Daimler Chrysler Ag | Process for the integration of PIN diodes comprises depositing a diode structure on a substrate, structuring a mesa structure, producing a metal bump, bonding a heat sink to the bump |
DE10201781A1 (en) * | 2002-01-17 | 2003-08-07 | Infineon Technologies Ag | High-frequency power component and high-frequency power module and method for producing the same |
US20040130037A1 (en) * | 2003-01-02 | 2004-07-08 | Cree Lighting Company | Group III nitride based flip-chip intergrated circuit and method for fabricating |
-
2004
- 2004-12-10 DE DE102004059884A patent/DE102004059884A1/en not_active Ceased
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5373185A (en) * | 1992-09-18 | 1994-12-13 | Sharp Kabushiki Kaisha | Multilayer vertical transistor having an overlay electrode connected to the top layer of the transistor and to the transistor substrate |
EP0663693A1 (en) * | 1993-11-30 | 1995-07-19 | Texas Instruments Incorporated | Low thermal impedance integrated circuit |
US5717231A (en) * | 1994-08-31 | 1998-02-10 | Texas Instruments Incorporated | Antenna having elements with improved thermal impedance |
US5532512A (en) * | 1994-10-03 | 1996-07-02 | General Electric Company | Direct stacked and flip chip power semiconductor device structures |
DE19507547C2 (en) * | 1995-03-03 | 1997-12-11 | Siemens Ag | Method of assembling chips |
US5939739A (en) * | 1996-05-31 | 1999-08-17 | The Whitaker Corporation | Separation of thermal and electrical paths in flip chip ballasted power heterojunction bipolar transistors |
DE19956903A1 (en) * | 1999-11-26 | 2001-05-31 | Daimler Chrysler Ag | Process for the integration of PIN diodes comprises depositing a diode structure on a substrate, structuring a mesa structure, producing a metal bump, bonding a heat sink to the bump |
DE10201781A1 (en) * | 2002-01-17 | 2003-08-07 | Infineon Technologies Ag | High-frequency power component and high-frequency power module and method for producing the same |
US20040130037A1 (en) * | 2003-01-02 | 2004-07-08 | Cree Lighting Company | Group III nitride based flip-chip intergrated circuit and method for fabricating |
Non-Patent Citations (1)
Title |
---|
Guptd, D.: A novel active aera bumped flip tech- nology for convergent heat transfer from gallium arsenide power devices. In: IEEE Transactions on Components, Packaging, and Manufacturing Techno- logy, Part A, ISSN 1070-9886, 1995, Vol. 18, No. 1, Seite 82-86. * |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE102006037118B3 (en) | Semiconductor switching module for vehicle electrical systems with a plurality of semiconductor chips, use of such a semiconductor switching module and method for producing the same | |
DE10201781B4 (en) | High frequency power device and high frequency power module and method of making the same | |
DE69737375T2 (en) | Method for mounting an electronic component on a printed circuit board and system for carrying out the method | |
DE102008059130B4 (en) | Device with a shunt resistor and method of manufacturing a device with a shunt resistor | |
DE19743767B4 (en) | A method of manufacturing a semiconductor die package having a surface mount semiconductor die and a semiconductor die package having a semiconductor die fabricated therefrom | |
DE10306643B4 (en) | Arrangement in pressure contact with a power semiconductor module | |
DE102011115886B4 (en) | Method for creating a connection of a power semiconductor chip with top potential surfaces to form thick wires | |
DE102006060484B4 (en) | Semiconductor device with a semiconductor chip and method for producing the same | |
DE10003671A1 (en) | Semiconductor component, especially a surface mountable semiconductor package, has front and back face electrodes connected to metal parts by precious metal-containing bodies or layers | |
EP3401950B1 (en) | Method of manufacturing a power semiconductor module | |
DE102017118913A1 (en) | Power semiconductor with a shunt resistor | |
DE102007007142A1 (en) | Benefits, semiconductor device and method for their production | |
DE102010000407A1 (en) | Semiconductor package with a band consisting of metal layers | |
DE112016007562B4 (en) | semiconductor device | |
DE202012004434U1 (en) | Metal shaped body for creating a connection of a power semiconductor chip with upper potential surfaces to thick wires | |
DE102007032775B4 (en) | power amplifier | |
DE10223738B4 (en) | Method for connecting integrated circuits | |
DE102007036841B4 (en) | Semiconductor device with semiconductor chip and method for its production | |
DE4446471C2 (en) | Method for mounting a chip on a flexible circuit carrier | |
DE102009027416B4 (en) | Semiconductor module with a pluggable connection and method of manufacturing a semiconductor module with a pluggable connection | |
DE10047213A1 (en) | Electric or electronic component e.g. for microelectronics, has electrically-conducting connection element between contact surface of component and section of contact path | |
DE102006012007A1 (en) | Power semiconductor module, has insulation layer covering upper and edge sides of chip, and inner housing section under release of source and gate contact surfaces of chip and contact terminal surfaces on source and gate outer contacts | |
DE102006024147B3 (en) | An electronic module including a semiconductor device package and a semiconductor chip and method of making the same | |
DE102004059884A1 (en) | Microchip, e.g. heterojunction bipolar transistor, flip-chip mounting method, involves coating surfaces of microchips, with gold-tin-solder, where chips are soldered by heating of arrangement along with substrate | |
DE102007044046B4 (en) | Method for internal contacting of a power semiconductor module |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8131 | Rejection |