DE102004055511B3 - Production process for a power semiconductor module forms solder layer between two partner layers then three hard fixing bridges and melts solder to give exact thickness - Google Patents

Production process for a power semiconductor module forms solder layer between two partner layers then three hard fixing bridges and melts solder to give exact thickness Download PDF

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Publication number
DE102004055511B3
DE102004055511B3 DE102004055511A DE102004055511A DE102004055511B3 DE 102004055511 B3 DE102004055511 B3 DE 102004055511B3 DE 102004055511 A DE102004055511 A DE 102004055511A DE 102004055511 A DE102004055511 A DE 102004055511A DE 102004055511 B3 DE102004055511 B3 DE 102004055511B3
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solder
bridges
power semiconductor
semiconductor module
solder layer
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Expired - Fee Related
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DE102004055511A
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German (de)
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Mathias Kock
Lars Paulsen
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Danfoss Silicon Power GmbH
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Danfoss Silicon Power GmbH
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09909—Special local insulating pattern, e.g. as dam around component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10992—Using different connection materials, e.g. different solders, for the same connection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/0415—Small preforms other than balls, e.g. discs, cylinders or pillars
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

A production process for a power semiconductor module comprises applying a solder layer of defined thickness onto a connection partner followed by a second partner, forming and hardening at least three stiffenable fixing bridges between the partners and melting the solder, leaving the bridges, to give solder of exact thickness.

Description

Die Erfindung betrifft ein Verfahren zum Herstellen eines Leistungshalbleitermoduls.The The invention relates to a method for producing a power semiconductor module.

Bei der Lötung von Leistungshalbleitermodulen ergibt sich das Problem, dass durch Temperaturwechsel Lötstellen verspröden und reißen.at the soldering of power semiconductor modules, the problem arises that through Temperature change solder joints go brittle and tear.

Bisher wird versucht, dem Problem durch eine Erhöhung der Lötschichtdicke entgegenzuwirken; je höher Lötschichtdicke ist, um so größer ist der Bereich, in dem das im we sentlichen elastische Lot Ausdehnungsunterschiede ausgleichen kann, die durch unterschiedliche Temperaturausdehnungskoeffizienten der Verbindungspartner begründet sind.So far an attempt is made to counteract the problem by increasing the solder layer thickness; The higher Solder layer thickness is, the bigger it is the area in which the essen- we elastic elastic solder expansion differences can compensate, by different coefficients of thermal expansion the connection partner justified are.

EP 10 39 536 A2 zeigt Aufbringungsstellen von jeweils vier Klebepunkten aus Epoxyd an /Montagestellen für drei integrierte Leistungsbauelemente. Ein einzelnes IPD wird dabei mit vier Klebepunkten montiert. Dies erfolgt durch auflegen einer Lot-Preform, Dispensen der Klebepunkte, Platzieren des IPD, Ausheilen des Epoxyds und Heizen des Reflow des Lotes. EP 07 12 153 A2 zeigt ein Leitungshalbleiterbauelement mit ringförmigem Klebstoffkranz um ein Lot auf einem Substrat. Die US 59 23 956 montiert einen Chip durch Aufschmelzen von Lot und nachfolgender Anordnung von Klebeppunkten an den Rand des Chips, wobei der Chip während des Aufschmelzens des Lotes gehalten werden muss und der Klebstoff erst in nachfolgenden Hochtemperaturschritten dieses Halten übernimmt. Die EP 07 89 397 A2 stellt ein Substrat für ein Leistungshalbleitermodul durch Verbinden eines Substrates mit Leiterschichten her, wobei ein Verbindungselement wie Silberlot verwendet wird und wobei an den Randstellen der Verbindung ein Harz aufgebracht wird, um das Substrat bruchunempfindlicher zu machen. Die JP 07-254781 nutzt aushärtbaren Kleber, um einen Chip mittels Lotplättchen auf die Landstücke der Leiterplatte zu montieren. Die US 63 33 209 B1 montiert ebenfalls einen BGA Chip und lehrt das simultane Ausheilen von Kapselung, Unterfüllung und Reflow, wozu moderner und schnell aushärtender Klebstoff dienen soll. Die US 63 83 843 B1 verwendet wieder entfernbare Spacer, um einen Chip auf einem Leiterrahmen mittels Epoxy zu haltern, wobei durch die wieder entfernbaren Spacer entstehenden Freiräume Eingriffsteilen für die nachfolgend aufgebrachte Kapselung entstehen. Die US 62 14 650 B1 verwendet eine als „Tubing" bezeichnete Dichtung, die zwischen Chip und Board eingebracht wird, um bei einem BGA Chip das Eindringen von Kapselmaterial zu verhindern. EP 10 39 536 A2 shows application points of four adhesive dots of epoxy at / assembly points for three integrated power components. A single IPD is mounted with four adhesive dots. This is done by placing a solder preform, dispensing the adhesive dots, placing the IPD, annealing the epoxy and heating the reflow of the solder. EP 07 12 153 A2 shows a lead semiconductor device with annular glue ring around a solder on a substrate. The US 59 23 956 mounted a chip by melting solder and subsequent arrangement of Klebeppunkten to the edge of the chip, wherein the chip must be held during the melting of the solder and the adhesive takes over in subsequent high temperature steps of this holding. The EP 07 89 397 A2 provides a substrate for a power semiconductor module by bonding a substrate to conductor layers using a connector such as silver solder and applying a resin at the edge locations of the compound to make the substrate less susceptible to breakage. JP 07-254781 uses thermosetting adhesive to mount a chip by means of solder plates on the land pieces of the circuit board. The US 63 33 209 B1 also assembles a BGA chip and teaches the simultaneous annealing of encapsulation, underfill and reflow, using modern and fast curing adhesive. The US 63 83 843 B1 again uses removable spacers to hold a chip on a lead frame by means of epoxy, resulting from the removable spacers resulting spaces engagement parts for subsequently applied encapsulation. The US 62 14 650 B1 uses a gasket called a "tubing", which is inserted between the chip and the board to prevent capsule material from entering a BGA chip.

Der Erfindung liegt die Aufgabe zugrunde, die hochbelasteten Stellen eines Lötschichtverbindungsaufbaus, die Ecken und Kanten einer Lötverbindung genauer in der Dicke zu definieren, die Verbindung in der Lebensdauer daher zu verbessern und gegen vorzeitigen Ausfall sicherer zu gestalten.Of the Invention is based on the object, the highly stressed bodies a solder layer connection structure, the corners and edges of a solder joint to define more accurately in thickness, the connection in life Therefore, to improve and to make against premature failure safer.

Erfindungsgemäß wird dies durch die Merkmale des Hauptanspruches gelöst. Durch Aufdrücken eines DCB auf die Preform und Fixieren dieses „zweiten Verbindungspartners" auf dem „ersten Verbindungspartner", einer Bodenplatte oder dergleichen wird sichergestellt, daß die definierte Anfangsstellung eingehalten bleibt.According to the invention this is solved by the features of the main claim. By pressing a DCB on the preform and fix this "second connection partner" on the "first Connection Partner " a bottom plate or the like ensures that the defined Initial position is maintained.

Weiter können Verformungen, beispielsweise der Bodenplatte antizipiert werden und entsprechend durch höhere Lötschichtdicken und entsprechend vor Auftrag weiterer abstandhaltender Schichten ausgeglichen werden. Auf diese Weise lassen sich neben zukünftigen Substratverformungen auch bereits bestehende Substratverformungen, beispielsweise durch gebogene Substrate oder nicht glatte Strukturen an der Oberseite ausgleichen.Further can Deformations, such as the bottom plate are anticipated and accordingly higher Solder layer thicknesses and accordingly before ordering further distance-retaining layers be compensated. In this way can be next to future Substrate deformations also existing substrate deformations, for example, by curved substrates or non-smooth structures balance at the top.

Weitere Merkmale und Vorteile der Erfindung ergeben sich aus nachfolgender Beschreibung eines bevorzugten Ausführungsbeispiels.Further Features and advantages of the invention will become apparent from the following Description of a preferred embodiment.

Das erfindungsgemäße Verfahren zum Herstellen eines Leistungshalbleitermoduls beruht auf den Schritten Auflegen eines zweiten Verbindungspartners auf den ersten Verbindungspartner unter Zwischenlegen bevorzugt eines Lotpreforms (bei bestimmten Geometrien unter zusätzlichem Anpressdruck), wodurch die Dicke des Lotpreforms die gewünschte Dicke der Lötverbindung definiert, Anordnung von drei oder mehr Fixierungsbrücken aus erstarrendem Material zwischen erstem und zweiten Verbindungspartner, Aushärten der Fixierungsbrücken, Aufschmelzen des Preforms unter Belassung der Geometrie der Fixierungsbrücken zur Erstellung einer Lötverbindung exakt definierter Dicke.The inventive method for manufacturing a power semiconductor module is based on the steps Placing a second connection partner on the first connection partner with the interposition of a preferred Lotpreforms (at certain Geometries under additional Contact pressure), whereby the thickness of the Lotpreforms the desired thickness the solder joint defines, arranging three or more fixation bridges solidifying material between first and second connection partners, Harden the fixation bridges, Melting of the preform while leaving the geometry of the fixation bridges to Creation of a solder joint exactly defined thickness.

Statt eines Preforms, einer flachen Lotmassescheibe vorbestimmter Geometrie kann die Lotmasse auch anders zwischen die Verbindungspartner gelagert werden. So ist es beispielsweise möglich, durch Kaltgasspritzen oder sogar durch einen rein mechanischen Auftrag einer Lotpaste geeignete Mengen Lotmasse aufzuschichten.Instead of a preform, a flat Lotmassescheibe predetermined geometry the solder mass can also be stored differently between the connection partners become. So it is possible, for example, by cold gas spraying or even by a purely mechanical application of a solder paste to apply appropriate quantities of solder paste.

Auf die Lotmasse wird dann definiert, bevorzugt mit vorbestimmten Anpressdruck der zweite Verbindungspartner aufgesetzt und dessen Position durch Fixierungsbrücken auch für den Fall festgelegt, das die Lotmaß ihn nicht mehr trägt, da sie aufgeschmolzen ist. Sofern keine anderen fixierenden Einrichtungen vorhanden sind, sind drei Fixierungsbrücken vorzusehen.On the solder mass is then defined, preferably with a predetermined contact pressure of the second connection partners placed and fixed its position by fixing bridges for the case, that the Lotmaß him no longer carries, since it is melted. Unless there are other fixing devices, three fixation bridges shall be provided.

Dabei kann schnellhärtendem nichtleitender Klebstoff zum Einsatz kommen, der kurzzeitig der Schmelztemperatur des z.B. im Preform vorhandenen Lots widerstehen kann oder es kann hochschmelzendem Lot verwendet werden, wobei darauf zu achten ist, während der Anordnung der Fixierungsbrücken das Preform nicht aufgeschmolzen wird.there can be fast-curing non-conductive adhesive are used, the short-term melting temperature of e.g. in the preform can withstand existing lots or it can refractory solder, taking care to while the arrangement of fixation bridges the preform is not melted.

Ein erfindungsgemäßes Leistungshalbleitermoduls mit einer Lötverbindung aus geschmolzenem Lot, besitzt dann im fertigen Zustand drei oder mehr Fixierungsbrücken aus erstarrendem Material, die zwischen erstem und zweiten Verbindungspartner verlaufen, und der Lotmasse ist noch anzusehen, daß sie nach dem Aushärten der Fixierungsbrücken zwischen den Verbindungspartnern aufgeschmolzen wurde.One Inventive power semiconductor module with a solder joint from molten solder, then has three or in the finished state more fixation bridges of solidifying material passing between first and second connection partners, and the solder mass is still to be seen that they after curing the Fixation bridges between was melted down to the liaison partners.

Claims (5)

Verfahren zum Herstellen eines Leistungshalbleitermoduls, gekennzeichnet durch die Reihenfolge der folgenden Schritte: – Auflegen eines zweiten Verbindungspartners auf einen ersten Verbindungspartner nach Zwischenlegen einer Lotschicht definierter Dicke, wobei die Dicke der Lotschicht der gewünschten Dicke der Lötverbindung entspricht, – Anordnen von drei oder mehr Fixierungsbrücken aus erstarrendem Material zwischen dem erstem und dem zweiten Verbindungspartner, – Aushärten der Fixierungsbrücken, – Aufschmelzen des Lotschicht unter Belassen der Geometrie der Fixierungsbrücken zur Erstellung einer Lötverbindung exakt definierter Dicke.Method for producing a power semiconductor module, characterized by the order of the following steps: - Hang up a second connection partner to a first connection partner after interposing a layer of solder of defined thickness, wherein the Thickness of the solder layer of the desired Thickness of the solder joint corresponds, - Arrange of three or more fixation bridges solidifying material between the first and the second connection partner, - curing the Fixing bridges, - melting the solder layer while leaving the geometry of the fixation bridges to Creation of a solder joint exactly defined thickness. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Lotschicht in Form eines Preforms aufgelegt wird.Method according to claim 1, characterized in that that the solder layer is applied in the form of a preform. Verfahren nach Anspruch 1, dadurch gekennzeichnet, daß die Fixierungsbrücken aus schnell härtendem nicht leitendem Klebstoff bestehen.Method according to claim 1, characterized in that that the fixing bridges from fast curing non-conductive adhesive. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass die Fixierungsbrücken aus hoch schmelzendem Lot bestehen, und während des Anordnens der Fixierungsbrücken das Preform nicht aufgeschmolzen wird.Method according to claim 1, characterized in that that the fixation bridges made of high-melting solder, and during the placement of the fixation bridges the Preform is not melted. Verfahren nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, dass beim Auflegen des zweiten Verbindungspartners und Anordnen der Fixierungsbrücken der zweite Verbindungspartner einem Anpressdruck ausgesetzt wird.Method according to one of the preceding claims, characterized characterized in that when the second connection partner and arranging the fixation bridges the second connection partner is exposed to a contact pressure.
DE102004055511A 2004-11-17 2004-11-17 Production process for a power semiconductor module forms solder layer between two partner layers then three hard fixing bridges and melts solder to give exact thickness Expired - Fee Related DE102004055511B3 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102012105297A1 (en) * 2012-06-19 2013-12-19 Endress + Hauser Gmbh + Co. Kg Method for connecting a component to a carrier via a soldering and component for connecting to a carrier
DE102015113421A1 (en) * 2015-08-14 2017-02-16 Danfoss Silicon Power Gmbh Method for producing semiconductor chips
DE102019206260A1 (en) * 2019-05-02 2020-11-05 Abb Schweiz Ag Method for manufacturing a semiconductor module

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EP0712153A2 (en) * 1994-11-10 1996-05-15 Vlt Corporation Packaging electrical circuits
EP0789397A2 (en) * 1996-02-07 1997-08-13 Hitachi, Ltd. Circuit board and semiconductor device using the circuit board
US5923956A (en) * 1996-01-30 1999-07-13 Nec Corporation Method of securing a semiconductor chip on a base plate and structure thereof
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US6214650B1 (en) * 2000-02-01 2001-04-10 Lockheed Martin Corporation Method and apparatus for sealing a ball grid array package and circuit card interconnection
US6333209B1 (en) * 1999-04-29 2001-12-25 International Business Machines Corporation One step method for curing and joining BGA solder balls
US6383843B1 (en) * 2000-04-17 2002-05-07 Advanced Micro Devices, Inc. Using removable spacers to ensure adequate bondline thickness

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07254781A (en) * 1994-03-16 1995-10-03 Matsushita Electric Ind Co Ltd Mounting of electronic component
EP0712153A2 (en) * 1994-11-10 1996-05-15 Vlt Corporation Packaging electrical circuits
US5923956A (en) * 1996-01-30 1999-07-13 Nec Corporation Method of securing a semiconductor chip on a base plate and structure thereof
EP0789397A2 (en) * 1996-02-07 1997-08-13 Hitachi, Ltd. Circuit board and semiconductor device using the circuit board
EP1039526A2 (en) * 1999-03-24 2000-09-27 Ford Motor Company Method and article for attaching high-operating-temperature electronic component
US6333209B1 (en) * 1999-04-29 2001-12-25 International Business Machines Corporation One step method for curing and joining BGA solder balls
US6214650B1 (en) * 2000-02-01 2001-04-10 Lockheed Martin Corporation Method and apparatus for sealing a ball grid array package and circuit card interconnection
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102012105297A1 (en) * 2012-06-19 2013-12-19 Endress + Hauser Gmbh + Co. Kg Method for connecting a component to a carrier via a soldering and component for connecting to a carrier
DE102012105297A8 (en) * 2012-06-19 2014-03-20 Endress + Hauser Gmbh + Co. Kg Method for connecting a component to a carrier via a soldering and component for connecting to a carrier
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DE102015113421B4 (en) * 2015-08-14 2019-02-21 Danfoss Silicon Power Gmbh Method for producing semiconductor chips
DE102019206260A1 (en) * 2019-05-02 2020-11-05 Abb Schweiz Ag Method for manufacturing a semiconductor module
EP3741562A3 (en) * 2019-05-02 2021-04-07 Audi AG Method for producing a semiconductor module
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