DE102004031447A1 - Data-weighting device for a sigma-delta ADC, has scrambler rotating digital output of converter as function of computed current pointer determined using pipeline mechanisms from preceding pointer and output data - Google Patents

Abstract

Scrambling devices (15) rotate the digital output signal of the sigma delta encoder (1) as a function of a computed current pointer. Pointer computation pipeline mechanisms (16) calculate the value of the current pointer P(n+1) as a function of a preceding pointer P(n) and preceding output data D(n). The preceding pointer and the preceding output data are delayed by at least one clock cycle. Preferably the current pointer is computed from the sum of the preceding pointer and preceding output data. Independent claims are included for : (1) a sigma-delta analog-digital converter for converting an applied analog input signal into digital output data; and (2) a method for calculating a current value pointer for a data-weighting device forming an average value within a sigma-delta analog-digital converter.

Description

The The invention relates to a mean value data weighting unit (DWA) for a sigma-delta analog-to-digital converter or converter in particular for continuous-time low-pass sigma-delta converter.

Sigma-Delta converter make an attractive solution for the effective implementation of an analog input or input signal in a digital output signal. Sampling the sigma-delta converter the analog signal at a much higher rate than the Nyquist rate, which is also referred to as oversampling. Oversampling relaxed the requirements of anti-alias filters and allows swapping of time resolution in amplitude resolution. In this way, high speed is exploited, too many Belongs to technologies such as VLSI technology. The noise-shaping property of sigma-delta modulators allows such converters high resolutions even using simple components such as 1-bit quantizers to reach. Due to the robustness of the components of the sigma-delta modulator and the efficient application of high speed are the sigma-delta analog-to-digital converters well suited for use in many applications.

1 shows a sigma-delta analog-to-digital converter according to the prior art. The in 1 The illustrated sigma-delta analog-to-digital converter includes a subtractor which subtracts an analog feedback signal from an applied analog input signal to produce an analog difference signal. The applied analog signal is the signal to be converted by the sigma-delta analog-to-digital converter into a digital signal. A loop filter is provided for filtering the output difference signal from the subtracter.

One quantizer connected to the output of the loop filter or analog-to-digital converter is clocked by a Tatksignal and quantized the filtered output difference signal from the loop filter to generate the digital output signal of the sigma-delta analog-to-digital converter. The quantizer is formed by an analog-to-digital converter (ADC). In many applications, the quantizer is designed as a very coarse quantizer, which only one resolution outputs from a bit.

Of the Sigma-delta analog-to-digital converter also has a digital-to-analog converter (DAC), which is also clocked by the clock signal and the converted by the quantizer output digital signal, around the analogue feedback signal to be generated, which is supplied to the subtractor. In this embodiment has the feedback loop the effect on, the accumulating difference of the loop filter output to force to zero.

Sigma-delta modulators have a noise-shaping property. Noise shaping does not reduce the magnitude of the glitch, but does change that Spectral density of the quantization error in that it is its Energy to higher Shifts frequencies. If oversampling has been used, can the higher ones Frequency components of the modulator output by using a digital low-pass filter be filtered out. In this way, disturbances within the signal band can be significant be reduced.

In The last couple of years have been receiving ever-increasing attention on the time-continuous approach steered for sigma-delta modulators, because they have either very low energy consumption properties or a higher one Have signal bandwidth. Due to the low energy consumption characteristics For example, the time-continuous sigma-delta modulators are attractive to all wireless receivers. A higher one Signal bandwidth is beneficial for all xDSL AFE transmitters or transceiver.

In a continuous-time sigma-delta modulator is the loop filter an analog loop filter and could be at least one integrator exhibit. A common problem with continuous-time sigma-delta modulators is the linearity of the feedback DAC for multi-bit implementations, because he's the linearity limited to the entire system. The distortion introduced by the DAC becomes main determined by the mismatch between its unitary components.

To remedy this disadvantage, a sigma-delta analog-to-digital converter as in 2 shown proposed. This sigma-delta ADC has an averaging data weighting unit (DWA) in the feedback branch. This averaging data weighting unit is formed by a barrel shifter. A barrel shifter is a hardware component that shifts or rotates a data word by any number of bits in a command cycle.

The feedback digital word is continuously rotated by the DWA unit, with the switching order of the DAC components occurring randomly within the digital-to-analog converter. The DAC components are either capacitors or switched current sources. In this way, the with the Mismatch of the DAC components transforms distorted energy into out-of-band shaped perturbation energy, and the performance of the sigma-delta modulator is enhanced.

3 Figure 4 shows a 4-bit implementation of a digital-to-analog converter (DAC) and the feedback signal path with 15 components such as capacitors or current sources.

3A shows the status when the DWA unit is switched off. The example represents a sequence of output data: 4134245631. The thermometer-coded output data of the quantizer is applied to the DAC and activates the DAC components. How out 3A can be seen, the first DAC component is always activated, thus increasing the mismatch.

The barrel shifter or DWA unit randomizes or generates a random switching sequence by computing a pointer that selects, in each clock cycle, the starting component to be used, based on the thermometer-coded data, as follows: P [n + 1] = P [n] + D [n] (1)

As can be seen from equation (1), the pointer P of the next clock cycle is simply calculated as the sum of the previous pointer and the previous data. As in the example below 3B 2, the second applied data portion (one) activates the fifth component of the DAC as the first component. In the same way, the next data part (three) activates the next three parts within the DAC (that is, part six to eight).

4 shows the implementation of the prior art averaging data weighting unit (DWA) as described in the sigma-delta ADC in FIG 2 is implemented. The DWA unit has a scrambling unit and a pointer calculation logic. The pointer calculation logic performs the calculation expressed in Equation (1) and selects the exact amount of component rotation that the scrambling unit has to perform.

5 shows a simulation of the implementation of a sigma-delta analog-to-digital converter according to the prior art after 2 if the like in 4 shown DWA unit is turned off. The mismatch of components within the DAC is not corrected by the DWA unit. The pointer always points to the first component, ie P = 0 5 The given example shown is the data sequence of the data D 44655445544454464 as in 5B shown.

5A represents the energy in spectral density PSD for the given example. When a CMOS oscillation input signal is applied, the sigma-delta ADC has a PSD with a peak amplitude at the respective frequency. How out 5A As can be seen, more peaks are produced in the higher frequency band which degrade the performance of the sigma-delta ADC.

6 shows the same sigma-delta ADC with the DWA unit turned on.

The pointer P (n + 1) of the next stage is always calculated from the sum of the previous data D (n) and the previous pointer P (n), as shown 6B is apparent. As 6A shows that the distortion frequency peaks above the main peak are greatly attenuated, thereby increasing the signal-to-noise ratio SNR of the sigma-delta ADC.

The conventional sigma-delta analog-to-digital converter with a DWA unit as in 2 The main disadvantage is that the digital operation performed within the DWA unit by the pointer calculation logic must be performed within less than half of a clock cycle of the applied clock signal CLK. The reason for this is that the comparators in the quantizer do not decide immediately but need at least half a clock cycle for their decision. The data D (n) for calculating the pointer is therefore available only at the end of this half clock cycle, but the next pointer P (n + 1) must be calculated and available half a clock cycle later when the next decision phase begins. Otherwise, the setting of the scrambling unit changes during the decision phase, and this can lead to incompatible data of the feedback input of the DAC.

Very According to high clock rates, the pointer calculation logic on a Implemented high-speed logic, which is not easy to build is and which does not allow low energy supply.

Accordingly, it is the object of the present invention to provide an averaging data weighting unit (DWA) for a sigma-delta analog-to-digital converter which enables very high clock frequencies while allowing the use of relatively low-speed logic which is easy to set up is and does not require a high supply voltage.

These Task is by a mean-forming data weighting unit solved with the features of claim 1.

• (a) Scrambling- bzw. Verwürfelungseinrichtungen zur Rotation des digitalen Ausgabesignals des Sigma-Delta-Analog- Digital-Umsetzers in Abhängigkeit von einem berechneten aktuellen Zeiger; und
• (b) Zeigerberechnungs-Pipelineeinrichtungen zur Berechnung des aktuellen Zeigers P(n+1) in Abhängigkeit von einem vorhergehenden Zeiger P(n) und vorhergehenden Ausgabedaten D(n); wobei der vorhergehende Zeiger P(n) und die vorhergehenden Ausgabedaten D(n) durch mindestens einen (α) Taktzyklus des Taktsignals verzögert sind.

The invention provides an averaged data weighting unit for a clock signal clocked which converts an applied analog input signal to a digital output signal, comprising:

• (a) scrambling means for rotating the digital output signal of the sigma-delta analog-to-digital converter in response to a calculated current pointer; and
• (b) pointer calculation pipeline means for calculating the current pointer P (n + 1) in response to a previous pointer P (n) and previous output data D (n); wherein the previous pointer P (n) and the previous output data D (n) are delayed by at least one (α) clock cycle of the clock signal.

In a preferred embodiment averaging data weighting unit according to the present invention Invention becomes the current pointer as a sum of the preceding one Pointer and the previous output data.

In a preferred embodiment the digital output data is thermometer-coded data.

In a preferred embodiment of the averaging data weighting unit of the sigma-delta analog-to-digital converter, it comprises:
a subtractor that subtracts the analog feedback signal from the analog input signal to form an analog difference signal,
a loop filter for filtering the difference signal output from the subtractor,
a quantizer clocked by the clock signal that quantizes the filtered difference signal output from the loop filter to produce the digital output signal of the sigma-delta analog-to-digital converter;
an analog-to-digital converter clocked by the clock signal that converts the digital output signal output from the quantizer and fed back to the analog-to-digital converter to produce the analog feedback signal for the subtractor.

In a preferred embodiment averaging data weighting unit according to the present invention Invention, the sigma-delta analog-to-digital converter is a time-continuous sigma-delta analog-to-digital converter.

In a preferred embodiment averaging data weighting unit according to the present invention Invention, the sigma-delta analog-to-digital converter is a discrete-time sigma-delta analog-to-digital converter.

In a preferred embodiment have the pointer calculation pipeline facilities at least two calculation stages for calculating the current pointer on.

In a preferred embodiment For example, each calculation stage has a pointer calculation logic and a delay unit which are connected in series.

In a preferred embodiment is every delay unit by at least one for Clock edges sensitive memory component formed.

In a preferred embodiment the clock frequency of the clock signal is higher than 200 MHz.

In a preferred embodiment the scrambling devices have sliding blocks.

• (a) Subtrahiereinrichtungen zur Subtraktion des analogen Rückkopplungssignals von dem analogen Eingangssignal zur Bildung eines analogen Differenzsignals;
• (b) ein Schleifenfilter zur Filterung des von den Subtrahiereinrichtungen ausgegebenen Differenzsignals;
• (c) einen von einem Taktsignal getakteten Quantisierer zur Quantisierung des von dem Schleifenfilter ausgegebenen gefilterten Differenzsignals zur Erzeugung der digitalen Ausgabedaten des Sigma-Delta-Analog-Digital-Umsetzers;
• (d) einen von dem Taktsignal getakteten Digital-Analogwandler, der das von dem Quantisierer ausgegebene und an den Digital-Analogwandler rückgekoppelte digitale Ausgabesignal zur Erzeugung des analogen Rückkopplungssignals für die Subtrahiereinrichtungen umwandelt;
• (e) eine Mittelwert bildende Datengewichtungseinheit, welche Folgendes aufweist:
• (e1) Scramblingeinheiten zur Rotation des an den Digital-Analogwandler rückgekoppelten digitalen Ausgabesignals in Abhängigkeit von einem berechneten Zeiger zur Randomisierung bzw. zufälligen Erzeugen der Schaltfolge von Umsetzbauteilen innerhalb des Digital-Analogwandlers;
• s(e2) Zeigerberechnungs-Pipelineeinrichtungen zur Berechnung des aktuellen Zeigers P(n+1) in Abhängigkeit von dem vorhergehenden Zeiger und den vorhergehenden Ausgabedaten, wobei der vorhergehende Zeiger und die vorhergehenden Ausgabedaten durch mindestens einen Taktzyklus des Taktsignals verzögert sind.

The invention further provides a sigma-delta analog-to-digital converter for converting an applied analog input signal to digital output data, comprising:

• (a) subtracting means for subtracting the analog feedback signal from the analog input signal to form an analog differential signal;
• (b) a loop filter for filtering the difference signal output from the subtracting means;
• (c) a quantizer clocked by a clock signal for quantizing the filtered difference signal output by the loop filter to produce the digital output data of the sigma-delta analog-to-digital converter;
• (d) a digital-to-analog converter clocked by the clock signal that converts the digital output signal output from the quantizer and fed back to the digital-to-analog converter to produce the analog feedback signal for the subtracting means;
• (e) a mean value data weighting unit comprising:
• (e1) scrambling units for rotating the digital output signal fed back to the digital-to-analog converter in response to a calculated pointer for randomizing the switching sequence of conversion components within the digital-to-analog converter;
• s (e2) pointer calculation pipeline means for calculating the current pointer P (n + 1) in response to the previous pointer and the previous output data, the previous pointer and the previous output data being delayed by at least one clock cycle of the clock signal.

In a preferred embodiment is the sigma-delta analog-to-digital converter a low-pass analog-to-digital converter.

In a preferred embodiment the loop filter has at least one integrator.

The The invention further provides a method for calculating a current one Pointer of an averaging data weighting unit within a Sigma-delta analog-to-digital converter, which is clocked by a clock signal and an applied converts analog signal into output data, wherein the current pointer dependent on from a previous calculated pointer and previous output data the sigma-delta analog-to-digital converter is calculated and where the previous pointer and the previous output data delayed at least one clock cycle of the clock signal.

In a preferred embodiment the method according to the invention The output data of the sigma-delta analog-to-digital converter are continuously in dependence from the calculated current pointer rotates to a random switching sequence of Convert components of a digital-to-analog converter (DAC), in a feedback path the sigma-delta analog-to-digital converter is arranged.

in the The following are preferred embodiments averaging data weighting unit for a Sigma-delta analog-to-digital converter according to the present Invention with reference to the accompanying drawings.

1 shows a sigma-delta analog-to-digital converter according to the prior art;

2 shows a further sigma-delta analog-to-digital converter according to the prior art with a DWA unit;

3 shows a diagram for illustrating the functionality of a sigma-delta analog-to-digital converter according to the prior art after 2 ;

4 shows a DWA unit according to the prior art as used in a conventional sigma-delta analog-to-digital converter;

5 shows a diagram illustrating the functionality of a sigma-delta analog-to-digital converter with disabled DWA unit;

6 shows the functionality of a conventional sigma-delta analog-to-digital converter with DWA unit switched on;

7 represents a preferred embodiment of the sigma-delta analog-to-digital converter according to the invention with a DWA unit according to the invention;

8th shows an implementation of a scrambling unit according to the present invention;

9 shows a preferred embodiment of the pointer calculation pipeline unit according to the present invention;

10 shows a diagram illustrating the functionality of the sigma-delta analog-to-digital converter according to the present invention;

11 shows another diagram illustrating the functionality of the sigma-delta analog-to-digital converter according to the present invention;

12 illustrates the mismatch noise shaping transfer function for a conventional DWA unit and different embodiments of the DWA unit according to the present invention.

How out 7 As can be seen, has the implementation of an applied analog signal in the digital output signal sigma-delta analog-to-digital converter 1 According to the present invention, an analog signal input 2 and a data output 3 on. The applied analog signal is transmitted via an internal signal line 4 subtracters 5 which subtract an analog feedback signal from the analog input signal to produce an analog difference signal. The analog differential signal is sent via an internal line 6 a loop filter 7 for filtering the subtracting means 5 passed difference signal passed. The output of the loop filter 7 is over a line 8th to a quantizer 9 connected, that of the loop filter 7 outputted filter signal to the digital output signal of the sigma-delta analog-to-digital converter 1 to create. The quantizer output is via an internal line 10 to the digital output 3 of the sig ma-Delta analog-to-digital converter connected. At a branching node 11 The digital output signal is sent via an internal line 12 to an entrance 13 a mean value data weighting unit according to the invention 14 fed back.

The quantizer 9 is formed by an analog-to-digital converter which is clocked by a clock signal CLK. In a preferred embodiment, the output data of the quantizer 9 Thermometer-coded data.

The mean value data weighting unit 14 has a scrambling unit 15 and a pointer calculation pipeline unit 16 on. The inputs of the scrambling unit 15 and the pointer calculation pipeline unit 16 are over lines 17 . 18 to the entrance 13 the DWA unit 14 connected. The output of the scrambling unit 15 is via an internal line 19 with a data output 20 the DWA unit 14 connected. The pointer calculation pipeline unit 16 is provided for calculating a current pointer in response to a previous pointer and previous output data, the preceding pointer and the previous output data being delayed by at least one clock cycle of the clock signal CLK.

How out 7 can be seen, the pointer calculation pipeline unit 16 different calculation levels 21-1 . 21-2 , ..., 21-N on. Each calculation level 21-i has a pointer calculation logic 22-i and a delay unit 23-i which are connected in series. In a preferred embodiment, the delay unit becomes 23-i formed by a clock edge sensitive memory device such as a flip-flop. The output of each pointer calculation stage is at the input of the next pointer calculation stage 21-i connected. The output of the delay component 23-N the last pointer calculation stage 21-N is via control lines 24 to the control input of the scrambling unit 15 connected. The pointer calculation of the current pointer P is performed by the pointer calculation pipeline unit 16 in a pipeline computation process that allows the implementation of higher clock rates with computation logic that requires only a low supply power, such as CMOS logic.

The data output 20 the DWA unit 14 is via an internal line 25 to the digital-to-analog converter 26 connected, which converts the scrambled or scrambled data into an analog feedback signal. The analogue feedback signal is sent via an internal line 27 at the subtraction node 5 directed.

The scrambling unit 15 the DWR unit 14 is to the rotation of the entrance 13 the DWA unit 14 applied digital output signal in response to the calculated current pointer designed so that the switching sequence of the Umsetzbauteile within the digital-to-analog converter 26 happens at random.

The pointer calculation pipeline unit 16 calculates the current pointer P as follows: P [n + 1] = P [n-α] + D [n-α] (2) where α is at least 1: α ≥1 (3)

The current pointer is calculated in response to the previous pointer and previous output data D. The previous pointer and the previous output data are delayed by at least one (α) clock cycle of the clock signal CLK. The digital process involving the pointer within the pointer calculation pipeline unit 16 can be pipelined in (α + 1) subprocesses so that the latency seen at the system level is only due to the latency of the last stage 21-N the pipeline is given. In pipelining the digital process, it is possible to significantly increase the clock rate of the clock signal CLK, which is the sigma-delta analog-to-digital converter 1 is supplied. Accordingly, it is with the pointer calculation pipeline unit 16 possible to use clock signals with a frequency greater than 200 MHz. This is without increasing the necessary computation speed of the computation logic units 22-i possible, so that calculation logic requires only low supply power.

8th shows an implementation of the scrambling unit 15 which a 4-bit binary coded pointer P via control lines 24 and generates a random data word having a data word width of n. In a preferred embodiment, n is 15. The scrambling unit 15 is a cascade of 4 binary coded sliding blocks 15-1 . 15-2 . 15-3 . 15-4 as in 8th shown executed. In this way, a significant amount of area on the chip can be saved when compared to a full matrix design.

9 shows a preferred embodiment of the pointer calculation pipeline unit 16 according to the present invention. The process is divided into 3 sub-operations, that is, thermometer-to-binary encoding, a modulo-16 binary summation, and forming the sum of the previous result with the carry bit to total that for the 15-row array of scrambling Ness 15 required modulo-15-sum.

In order to perform these three necessary computations in only half a clock cycle of the clock signal, the process in the illustrated embodiment has become two pipeline computation stages 21-i the pointer calculation pipeline unit 16 wherein the previous pointer and the previous output data are delayed by one clock cycle of the clock signal CLK (α = 1).

The first calculation stage 21-1 converts 15-bit thermometer-coded output data into a 4-bit binary coded data word. A 4-bit binary coded data word can be used more easily to calculate a sum. The binary full adder within the first calculation stage 21-1 adds the stored previous pointer to the current data. In the second calculation stage 21-2 the remaining summation is realized with the previous carry bit. The calculation stages 21-i are separated by edge sensitive memory devices, such as flip-flops, which operate with the system clock derived appropriate clock signal CLK.

10 shows a simulation result for a sigma-delta analog-to-digital converter according to the invention 1 with two calculation stages, ie with a delay of one (α = 1). When comparing 10 With 6 It will be seen that the SNR signal to interference ratio is slightly increased when a pointer calculation unit 16 with pipeline is used.

11 shows a similar relationship result for a pointer calculation pipeline unit with three calculation stages 21-i that is, with a delay of two clock cycles (α = 2). It can be seen that the ratio SNR signal to perturbation is almost as good as that of the conventional sigma-delta analog-to-digital converter without delay (α = 0), as in FIG 6 shown. Consequently, the sigma-delta analog-to-digital converter results 1 according to the present invention, a data weighting unit 14 with pipeline pointer calculation unit 16 Similar results, but has the advantage that much higher clock rates of the clock signal CLK can be used.

12 represents the mismatch noise shaping transfer function MTF for different delays (α). In the important frequency range, that is between zero and the bandwidth BW, the slope of the MTF slightly increases as the delay (α) increases.

The mismatch noise shaping transfer function MTF is given by: MTF (z) = 1 - z - (Α + 1) (4)

For α> 0 it can be seen that MTF becomes a bandpass design. Besides, it is off 12 It can be seen that the in-band perturbation increases slightly as α is increased. However, the advantage of a higher clock rate is decisive. In any case, the in-band perturbation is still acceptable for α = 1 and α = 2, as in 10 . 11 is shown.

1

Sigma-delta analog-to-digital converter

2

analog input

3

Digital output

4

internal management

5

subtractor

6

internal management

7

loop filter

8th

management

9

quantizer

10

management

11

branch nodes

12

management

13

entrance

14

Average forming data weighting unit

15

Scramblingeinheit

16

Pointer calculation pipeline unit

17

management

18

management

19

management

20

output

21

calculation stage

22

calculation logic

23

delay unit

24

control lines

25

management

26

additional analog converter

27

cables

Claims (16)

Averaging Data Weighting Unit (DWA) for a sigma-delta analog-to-digital converter clocked by a clock signal (CLK) ( 1 ) which converts an applied analog input signal to a digital output signal, comprising: (a) scrambling means (Fig. 15 ) for rotating the digital output signal of the sigma-delta analog-to-digital converter ( 1 ) in response to a calculated current pointer; and (b) pointer calculation pipeline facilities ( 16 ) for calculating the current pointer P (n + 1) in response to a previous pointer P (n) and previous output data D (n); wherein the previous pointer P (n) and the previous output data D (n) are delayed by at least one (α) clock cycle of the clock signal (CLK). Averaging data weighting unit Claim 1, wherein the current pointer P (n + 1) is a sum of the previous pointer P (n) and the previous output data D (n) is calculated. Averaging data weighting unit Claim 1, wherein the digital output data thermometer-coded Data is. The average data weighting unit of claim 1, wherein the sigma-delta analog-to-digital converter comprises: a subtractor ( 5 ) which subtracts the analog feedback signal from the analog input signal to form an analog differential signal; a loop filter ( 7 ) for filtering by the subtractor ( 5 ) output difference signal; a clocked by the clock signal (CLK) quantizer ( 9 ), that of the loop filter ( 7 ) outputted filtered differential signal for generating the digital output signal of the sigma-delta analog-to-digital converter ( 1 ) quantizes; a clocked by the clock signal (CLK) analog-to-digital converter ( 26 ), that of the quantizer ( 9 ) and to the analog-digital converter ( 26 ) feedback digital output signal for generating the analog feedback signal for the subtractor ( 5 ) converts. Averaging data weighting unit according to claim 1, wherein the sigma-delta analog-to-digital converter ( 1 ) is a time-continuous sigma-delta analog-to-digital converter. Averaging data weighting unit according to claim 1, wherein the sigma-delta analog-to-digital converter ( 1 ) is a discrete-time sigma-delta analog-to-digital converter. Averaging data weighting unit according to claim 1, wherein said pointer calculation pipeline means ( 16 ) have at least two calculation stages (21-i) for calculating the current pointer. Averaging data weighting unit according to claim 7, wherein each calculation stage ( 21-i ) a pointer calculation logic ( 22-i ) and a delay unit ( 23-i ), which are connected in series. Averaging data weighting unit according to claim 8, wherein each delay unit ( 23-i ) is formed by at least one memory component sensitive memory component. Averaging data weighting unit Claim 1, wherein the clock frequency of the clock signal (CLK) is higher than 200 MHz is formed. Averaging data weighting unit according to claim 1, wherein said scrambling means ( 15 ) Have sliding blocks. A sigma-delta analog-to-digital converter for converting an applied analog input signal into digital output data comprising: (a) a subtracting device ( 5 ) for subtracting the feedback signal from the input signal to form a difference signal; (b) a loop filter ( 7 ) for filtering the difference signal output from the subtracting means; (c) a quantizer clocked by a clock signal (CLK) ( 9 ) for quantizing the of the loop filter ( 7 ) outputted filtered differential signal for generating the output data of the sigma-delta analog-to-digital converter ( 1 ); (d) a digital-to-analog converter clocked by the clock signal (CLK) ( 26 ), that of the quantizer ( 9 ) and to the digital-to-analog converter ( 26 ) feedback output data for generating the feedback signal for the subtracting device ( 5 ) converts; (e) an averaging data weighting unit ( 14 ), comprising: (e1) scrambling devices ( 15 ) for rotation to the digital-to-analog converter ( 26 ) feedback digital output data in response to a calculated pointer for randomizing or generating the switching sequence of Umsetzbauteilen randomly within the digital-to-analog converter ( 26 ); (e2) pointer calculation pipeline devices ( 16 ) for calculating the current pointer in response to the previous pointer and the previous output data, the preceding pointer and the previous output data being delayed by at least one (α) clock cycle (T) of the clock signal (CLK). A sigma-delta analog-to-digital converter according to claim 12, wherein said sigma-delta analog-to-digital converter ( 1 ) a low-pass analog-to-digital converter. A sigma-delta analog-to-digital converter according to claim 12, wherein the loop filter ( 7 ) has at least one integrator. Method for calculating a current pointer of an averaging data weighting unit ( 14 ) within a sigma-delta analog-to-digital converter ( 1 ), which is clocked by a clock signal (CLK) and converts an applied input signal into output data, wherein the current pointer in response to a previous calculated pointer and previous output data of the sigma-delta analog-to-digital converter ( 1 ), and wherein the previous pointer and the previous output th delayed by at least one (α) clock cycle of the clock signal (CLK). The method of claim 15, wherein the output data of the sigma-delta analog-to-digital converter ( 1 ) is continuously rotated in response to the calculated current pointer to produce a random switching sequence of conversion components of a digital to analogue converter ( 26 ) in a feedback path of the sigma-delta analog-to-digital converter ( 1 ) is arranged.