DE102004027277A1 - Excess film emending method for e.g. dynamic RAM, involves providing simulation model with regulation algorithm, determining offset values for samples, and determining parameter of algorithm for illumination device on basis of offset values - Google Patents

Abstract

The method involves exposing two samples with gauge marks to exposure fields. A simulation model with a regulation algorithm is provided in an illumination device for correction of inter field errors arising out during exposure of the samples. A set of offset values is determined for the two samples, and a parameter of the regulation algorithm is determined for the illumination device on basis of the offset values.

Description

The The present invention relates to a method for correcting the overlap several layers in photolithographic structuring using different projection devices.

to Integrated circuit fabrication is commonly done on semiconductor wafers provided with different electrical properties layers applied and each lithographically structured. A lithographic Structuring step may consist of a photosensitive Apply Resist, this with a desired structure for the relevant Layer to illuminate and develop, and then the thus resulting resist mask in the underlying layer in an etching step transferred to.

With the ever increasing integration densities of integrated circuits increase also the requirements for the positional accuracy of a Semiconductor substrate to be projected structure. In particular, then if already pre-levels in underlying layers, eg. In one have been transferred lithographic projection step, always stricter tolerance limits regarding the mutual orientation of the currently projected onto the substrate Structure taken into account relative to the structures of said pre-levels be to functional to ensure the circuit.

density Line-column patterns, such as those in the field of manufacture of dynamic random access memories (DRAM) are formed, have, for example, in the first to be formed on the semiconductor wafer Layers structures with line widths of 70, 90 or 110 nm. The first layers to be patterned are in this example the deep trench formation pattern (DT level) and the definition active areas (AA level). The formed above these layers Structures usually have a coarser one structural resolution so that more relaxed overall requirements for the resolution of the Projection apparatus result.

For the lithographic Projection step of such a pattern is usually for the first Critical layers used a wafer scanner, in comparison to a wafer stepper a higher one Resolving power. Subsequent non-critical layers could also be scanned with a wafer scanner be exposed. Often, however, is for uncritical layers Wafer stepper used, in particular, to increase production costs reduce. This mixture of different exposure devices is typical for a high volume Manufacturing process.

at A wafer stepper is subjected to a large-area exposure of a layer with a pattern in an exposure field on top of the semiconductor wafer. By doing so leaves a much higher one Achieve throughput in the production of integrated circuits. Because of the big one However, the image quality to be imaged (projection image field) is the image quality across from a wafer scanner a little worse.

In a wafer scanner, the exposure of the photosensitive takes place Resists along an exposure slot. The semiconductor wafer is generally deposited on a substrate holder and for exposure in moved a corresponding position. Then that's on a mask arranged patterns successively in individual exposure fields transferred to the photosensitive resist. It will be during the exposure of an exposure field of the substrate holder and the the aperture defining slot against each other. Usually is the size of a Exposure field about 26 mm × 35 mm. The exposure slot passes over the exposure field due to the uniform movement of the substrate holder and the aperture. It comes from a source of light Light the exposure slot and will be in the subsequent projection optics imaged on the semiconductor wafer.

One The advantage of the wafer scanner is that the projection image field on the size of the exposure slot is limited. this makes possible a substantial improvement of the imaging properties of the projection device. by virtue of the shift (scanning) of the projection image field over the pattern to be imaged results in an overall picture, the Image fidelity achieved by an appropriate control of the exposure device must become.

The Exposure of the individual exposure fields is usually carried out in such a way that the top of the semiconductor wafer in a multiple array of Exposure fields in the form of a matrix or a grid (engl. grid), which with the wafer scanner or the wafer stepper be successively exposed and structured.

at Modern technologies of DRAM manufacturing will be the one to target accuracy required between structures of different layers, which is also referred to as an overlay budget, due to the smaller expectant structure resolutions continue to sink. So is for example, the tolerable inaccuracy in the coverage at the 110nm process line only still about 20 nm. Current and future process lines are thus sensitive to sources of very subtle overlay errors.

The Determination of coverage or positional accuracy of two superimposed lying layers takes place during the production of integrated circuits usually with so-called Overlay targets. These are two substructures that each separately mapped to each of the layers. The first Substructure can consist of a rectangular structural element, that of a frame-shaped second Substructure is surrounded. Overlay targets usually become arranged together with other alignment marks in the saw frame area. The structure described above is a box-in-box or box-in-frame brand known. Usually is the offset of the individual substructures to each other with a Overlay measurement device for example, an optical microscope, measured.

to Determination of Distortions in the Lithographic Projection A single layer often uses measuring marks whose Form is very similar to the overlay targets described above. Again, these are two substructures, with the first substructure, e.g. the rectangular structural element, at the projection of the first exposure field is displayed. The second in this example frame-shaped part structure is at the projection of the second exposure field shown. The two Substructures together form the overlay target. One speaks in in this context also of a so-called nested target or interlocking target. The difference to the ones described above Overlay Targets is thus that the two partial structures are formed on the same layer of semiconductor wafer.

at the exposure of a semiconductor wafer with a wafer scanner or a Wafer steppers are known to have multiple effects that cause overlay errors to lead can. This overlay error can generally be assigned to two categories of error sources. For one thing Errors occur during exposure within an exposure field arise. These sources of error are usually called intra-field errors or Field error called. Second, sources of error are known by dividing the semiconductor wafer into individual exposure fields be caused and for each exposure field can be different. These sources of error usually become as an inter-field error or grid error designated.

at The following entries are of importance, among other things, for the intra-field errors. For example, the exposure in an exposure field can change twisted a fixed angle or a constant factor in the magnification to be wrong. In the first case one speaks of a rotation error, the second case usually becomes as a magnification error designated. Rotation errors, for example, by a misalignment caused by the reticle.

Inter field error be in the exposure, for example, by the control of the Caused substrate holder. A source of error is a twist the position of the exposure field around one of the position of the Exposure field on the semiconductor wafer dependent angle given (so-called Grid rotation error). Another source of error is the same scaling error dependent on the position of the exposure field on the semiconductor wafer (Grid magnification error). About that In addition, the exposure with a wafer scanner still plays the so-called translation errors a role, the different scan directions and different speeds in different scanning directions of the wafer scanner. The translation error is usually smaller in amount than the other above mentioned mistakes.

The Intrafield and interfield errors can each be separated for a component in a first direction (eg the x-direction) and for a component indicate perpendicular to this (y-direction). Leave for the wafer scanner Thus, the overlay errors in a simulation model with ten Summarize parameters.

at the exposure or structuring of the first layer on the semiconductor wafer Correct the correction of intra-field and inter-field errors important contribution to the overall overlay budget, as these errors may at later No longer correct exposures. In particular, a Wafer stepper in subsequent exposure steps no correction different exposure field sizes or asymmetric intra-field errors To run.

Under asymmetric errors are generally understood as errors in x direction and y direction are different. That's the way it is, for example possible, with a wafer stepper or a wafer scanner asymmetric grid error to correct, as usual the control of the substrate holder during the start of the exposure field position independent in x and y direction can be done.

One in the successive structuring of several layers with different ones Exposure devices so far little noticed problem is the above mentioned different ones Sources of error in the exposure of the first layers with a Correct wafer scanner. The correction is asymmetric posts to the interfield and intra field errors crucial for a high positional accuracy of the layers to each other. Additionally difficult is a precise analysis of the different sources of error thereby, that also distortions may occur, which are dependent on the exposure device used. these can For example, caused by lens aberrations in the projection apparatus and lead as described above, to a size-dependent mispositioning the overlay targets. An insufficient or incorrect assignment of the Overlay error results however, at a significantly reduced overlay budget. This can be done in the Extreme case lead to failure of the circuit to be produced. Especially So far, no method is known, the above-mentioned different Sources of error in the mapping from measurements of the various To extract overlay targets and according to their origin Interfeld or the Intrafeld contributions assigned.

The The object of the invention is, therefore, the above-mentioned problems to overcome and to provide a method that provides improved registration the different layers in photolithographic structuring made possible by means of various projection devices.

• – Bereitstellen eines ersten Musters und eines zweiten Musters zur Strukturierung je einer Schicht bei der Herstellung einer integrierten Schaltung, wobei das erste Muster mehrere erste Messmarken und das zweite Muster mehrere zweite Messmarken umfasst;
• – Bereitstellen eines ersten Projektionsgeräts, wobei das erste Projektionsgerät geeignet ist, eine Belichtung in mehreren Belichtungsfeldern durchzuführen;
• – Bereitstellen eines Simulationsmodells mit einer mehrere Parameter aufweisenden Berechnungsvorschrift zur Korrektur der bei der Belichtung mit dem ersten Projektionsgerät auftretenden Interfeld-Fehlern;
• – Bereitstellen eines zweiten Projektionsgeräts;
• – Bereitstellen einer Vielzahl von Halbleiterwafern, wobei für jeden Halbleiterwafer folgende Schritte ausgeführt werden: (a) Sukzessives photolithographisches Strukturieren einer ersten Schicht des Halbleiterwafers entsprechend des ersten Musters mit dem ersten Projektionsgerät in den Belichtungsfeldern; (b) Sukzessives photolithographisches Strukturieren einer über der ersten Schicht angebrachten zweiten Schicht des Halbleiterwafers entsprechend des zweiten Musters mit dem zweiten Projektionsgerät in den Belichtungsfeldern; (c) Bestimmen von Versatzwerten der ersten Messmarken zu den zweiten Messmarken auf dem Halbleiterwafer; und (d) Bestimmen der Parameter der Berechnungsvorschrift für das erste Projektionsgerät anhand der Versatzwerte, so dass nachfolgende Belichtungen mit dem ersten Projektionsgerät unter Berücksichtigung der Interfeld-Fehler durchgeführt werden.

This object is achieved by a method for correcting the overlapping of multiple layers in the photolithographic patterning by means of various projection devices, wherein the following steps are carried out:

• - Providing a first pattern and a second pattern for structuring a layer in the manufacture of an integrated circuit, wherein the first pattern comprises a plurality of first measuring marks and the second pattern comprises a plurality of second measuring marks;
• - Providing a first projection device, wherein the first projection device is adapted to perform an exposure in a plurality of exposure fields;
• - Providing a simulation model with a multi-parameter calculation rule for correcting the occurring during exposure to the first projection device inter-field errors;
• - Providing a second projection device;
• - Providing a plurality of semiconductor wafers, wherein for each semiconductor wafer, the following steps are carried out: (a) successive photolithographic patterning of a first layer of the semiconductor wafer corresponding to the first pattern with the first projection device in the exposure fields; (b) successive photolithographic patterning of a second layer of the semiconductor wafer mounted over the first layer corresponding to the second pattern with the second projection device in the exposure fields; (c) determining offset values of the first measurement marks to the second measurement marks on the semiconductor wafer; and (d) determining the parameters of the calculation rule for the first projection device based on the offset values so that subsequent exposures are performed with the first projection device taking into account the inter-field errors.

One The basic idea of the invention is that of lithography a second layer with a projection apparatus not correctable Error as an interfield error to a projection device used for photolithographic structuring of the first layer provided is due. This leads in particular to that asymmetric errors already in the exposure or photolithographic Structuring the first layers are corrected. This can be a substantial improvement of the overlay (overlay) of different Layers reach, resulting in a higher yield in the production integrated circuits leads.

In a further embodiment, the step of determining offset values of the first measurement marks relative to the second measurement marks further comprises storing the inter-field errors of the first projection device calculated from the offset values in order to provide statistical control of the inter field error of the first projection device.

According to this The procedure becomes one with the lithography of the first layer used projection apparatus with regard to its occurring Interfeld error controlled, for example, to determine whether a recalibration of the projection apparatus is necessary.

advantageous Further developments of the invention are specified in the subclaims.

The The invention will now be described with reference to the accompanying drawings. In show the drawing:

1 an exposure device in a schematic cross-sectional view of the application of the method according to the invention;

2 schematically a semiconductor wafer with exposure fields in a plan view;

3 schematically an exposure field of a semiconductor wafer in a plan view;

4 an overlay measuring device in a schematic cross-sectional view of the application of the method according to the invention;

5 schematically a further exposure field of a semiconductor wafer in a plan view;

6A to 6D an exposure device in a schematic cross-sectional view of the application of the method according to the invention; and

7 a plan view in a diagram measured and simulated structure widths that are used to optimize the method according to the invention.

The inventive method will be below for a photolithographic structuring of a first layer in one Exposure field with a wafer scanner and a second layer described with a wafer stepper, each the same size of the exposure field exhibit. The invention is also on several layers with different configuration of the exposure devices used. So it is also possible several re the smallest dimensions to expose critical layers with a wafer scanner and subsequently to perform an exposure with a wafer stepper.

In 1 is a schematic cross-sectional view of the structure of an exposure device 5 shown. The exposure device 5 includes a movable substrate holder 10 , On the substrate holder 10 is a semiconductor wafer 12 filed on the front of a resist layer 14 is applied for example by spin coating. The exposure device 5 further includes a light source 16 that over the substrate holder 10 is arranged, and is suitable to emit light, for example, with a wavelength of 248 nm or 193 nm. That from the light source 16 radiated light is transmitted through a projection lens 18 on the surface of the semiconductor wafer 12 projected. Between the light source 16 and the projection lens 18 is a reticle 20 attached, which is provided with the pattern of the corresponding layer. In the case of a wafer scanner, an exposure slot (not in 2 shown) between the reticle 20 and the projection lens 18 appropriate.

The exposure of the layers takes place in individual exposure fields 22 , as in 2 is shown. This is done every exposure field 22 on the front of the semiconductor wafer 12 assigned a single grid point (grid). By controlling the substrate holder 10 becomes the semiconductor wafer 12 aligned accordingly. The exposure field 22 usually has a maximum size of about 26 mm in length and 35 mm in width. In 2 are for the individual exposure fields 22 each selected a size of about 20 mm in length and 20 mm in width, so that in a semiconductor wafer 12 about sixty mm in diameter, about sixty complete exposure fields 22 on the front of the semiconductor wafer 12 be housed.

For integrated circuit fabrication, a circuit design is used which typically includes multiple layers. In 3 is schematically a first pattern 21 a first layer that within a substantially rectangular sawing frame 23 is arranged.

In the first pattern 21 become first substructures 50 provided, the first substructures 50 are adapted to each form the first part of an interlocking target. Also, in the first pattern 21 second substructures 54 provided, wherein the second sub-structures are adapted to each form the second part of the interlocking target.

As in 3 shown, includes the first pattern 21 at least eight first substructures 50 and eight second substructures 50 , each in an imaginary extension of the saw frame 22 and outside the saw frame 22 to be ordered. After exposure of all exposure fields 22 form the first substructures 50 and the second substructures 54 together with the first substructures and the second substructures of the adjacent exposure fields 22 a total of eight interlocking targets for each exposure field.

To fulfill the function of interlocking targets, the first substructures exhibit 50 of the first pattern 21 The shape of a frame whose outer dimension is about 27 microns in length and 27 microns wide in current technologies with a pattern resolution of 70 nm of the exposure equipment. For the second substructures 54 of the first pattern 21 For example, the shape of a square surface is provided whose outer dimension is about 12 μm in length and 12 μm in width. The exact form of the first substructures 50 and the second substructures 54 however, is not essential to the practice of the invention. In addition to the box-in-frame targets described here, other targets can also be used, such as bar-in-bar targets with linear first substructures 50 and second substructures 54 or substructures, which in turn have a substructuring to avoid structure-dependent aberrations, are used. Other targets known to those skilled in the art are not excluded.

After the photolithographic projection, the positional accuracy of the currently exposed layer becomes relative to the adjacent exposure fields 22 with an overlay meter 40 determines how in 4 shown. On the front of the semiconductor wafer 10 is a resist structure 14 ' formed by developing from the resist layer 14 originated.

The term layer here and below in an overlay measurement both the resist structure 14 ' as well as one example by means of the resist pattern 14 ' as etch mask structured layer of the semiconductor wafer 10 to understand. Usually the measurements are done with the overlay meter 40 at the resist structure 14 ' performed to large deviations from overlay specifications, the semiconductor wafer 10 to be reworked. When reworking to the cost savings, the resist structure 14 ' removed, applied a new resist layer and the semiconductor wafer 10 re-exposed.

The overlay meter 40 includes another light source 42 to the front of the semiconductor wafer 10 with light 46 to irradiate. That from the front of the semiconductor wafer 10 reflected light 48 is in a microscope 44 demonstrated. By means of the microscope 26 become the offset values between the first substructure 50 and the second substructure 54 the interlocking targets of the individual exposure fields 22 certainly.

The by means of the microscope 26 certain offset values are evaluated with a simulation model containing a calculation rule. The aim is to correct the inter-field errors that occur during the exposure with the first projection device. In general, the offset values are composed of systematic position errors, which can be corrected for subsequent exposures using the simulation model, and a stochastic component. For the determination of systematic positional errors with the simulation model, the following calculations are carried out, for example, for a CANON wafer scanner: Ovl_X (x, y) = TransX + CF (x) * GMagX - CF (y) * GRotY + IF (x) * FMagX - IF (y) * FRotY, and Ovl_Y (x, y) = TransY + CF (y) * GMagY + CF (x) * GRotX + IF (y) * FMagY + IF (x) * FRotX.

In this calculation rule, x denotes the position of the exposure field along the first coordinate axis and y the position of the exposure field along the second coordinate axis. The aim of the calculation is to determine the systematic position error Ovl_X (x, y) or Ovl_Y (x, y) in both coordinate directions. This position error consists of the following contributions: TransX or TransY are parameters of the translation error, GMagX or GMagY represent parameters of the grid magnification error, GRotX or GRotY parameters of the grid rotation error, FMagX or FMagY parameters of the field magnification error and FRotX or FRotY parameter of the field rotation error. These are each indicated in x-direction and y-direction.

The symbols CF and IF represent a decomposition of the coordinate values into a contribution on the semiconductor wafer or within an exposure field, ie for the coordinate values in the x-direction and y-direction, the following applies: x = CF (x) + IF (x), and y = CF (y) + IF (y).

Subsequently, for each interlocking target in each exposure field 22 a residual error value is determined.

The residual error value is calculated for interlocking targets according to the following equations: Res_X = M_X - Ovl_X (x, y), and Res_Y = M_Y - Ovl_Y (x, y).

there represent Res_X or Res_Y the residual error value in the x or y direction and M_X or M_Y the offset value in the x or y direction.

Subsequently, will the standard deviation of the residual error value in the x and y direction certainly. Their value is calculated from the root of the sum of Squares the residual error value in the x or y direction. These Calculation is known in the art and therefore will not be here explained in more detail.

Subsequently, will the standard deviation of the residual error value in the x and y direction for determining the ten parameters of the simulation model of the projection apparatus used. For this purpose, a linear equation system is set up, being for all parameters of the simulation model of the projection apparatus of the minimum value of the standard deviation is determined. These parameters of the simulation model are returned to the projection apparatus to to correct the respective positional error already during the exposure.

Table 1 summarizes the result of a simulation calculation. The basis of the simulation calculation are offset values of interlocking targets according to 3 , where the individual possible sources of error (grid or rotation errors) were simulated independently of each other. For two selected interlocking targets T1 and T2 located in the upper right corner of the exposure field (see FIG 3 ), the offset values are calculated. The rotation errors for grid and field contributions are selected with a rotation of 1 μrad, while the magnification errors are 1 ppm.

The simulated offset values are for both interlocking targets each separately for a contribution in the x-direction and in the y-direction specified. One recognises, that the grid and field errors are not differentiated can, because both sources of error - until on the sign - the provide equal offset values.

So leads to Example a grid magnification error GMagX in the x-direction by 1 ppm to an offset value of -20 nm in x-direction. One Field-magnification error FMagX leads in the x-direction by 1 ppm also to an offset value of 20 nm in the x direction. Thus it is at this point the litigation after exposure of the first layer with the scanner not possible, the measured offsets either the grid errors or the field errors assigned. In practice, this means that optimizing the Exposure conditions can only be performed under certain assumptions can, because the exact source of error is unknown.

Table 1

A possibility is all when exposing the first layer certain error as a field error to watch. These are used to control the first projection device, so that subsequently executed Exposures are corrected by the contribution of these sources of error.

In 5 another embodiment of interlocking targets is shown. In the first pattern for structuring the first layer, first substructures are again 50 provided, the first substructures 50 are adapted to each form the first part of an interlocking target. In addition, in the first pattern, second substructures become 54 provided, wherein the second sub-structures are adapted to each form the second part of the interlocking target.

As in 5 shown, includes the first pattern 21 in this embodiment, four first substructures 50 and four second substructures 54 , The first substructures 50 are in a corner of an imaginary subframe 52 who the sawing frame 22 surrounds, arranged. The second substructures 54 For example, they are diagonally offset and outside the subframe 52 arranged. After exposure of all exposure fields 22 form the first substructures 50 and the second substructures 54 together with the first substructures and the second substructures of the adjacent exposure fields a total of four interlocking targets for each exposure field 22 ,

The dimensions of the interlocking targets, for example, analogous to those of the embodiment according to 3 selected. This is the way the first substructures look 50 of the first pattern 21 the shape of a frame, its outer dimension approximately 27 μm length and 27 μm width is. For the second substructures 54 of the first pattern 21 For example, the shape of a square surface or a frame is provided whose outer dimensions are about 12 microns in length and 12 microns in width. The exact form of the first substructures 50 and the second substructures 54 is for the implementation of the proceedings according to the invention, however, not essential and other known to those skilled targets are not excluded.

Table 2

Table 2 shows simulated offset values that are obtained when measuring the interlocking targets according to 5 would result. The sources of error are chosen as in the discussion in connection with Table 1. It can be seen that the offset values in turn do not allow separation of the grid and field errors, but it should be noted that the interlocking targets according to 5 although with the same simulated errors in terms of amount the same offset values compared to the interlocking targets according to 3 deliver, however, the interlocking targets according to 5 offset both in grid and field errors. By using interlocking targets according to 5 Thus, the sensitivity to grid and field errors in exposing the first layer to a wafer scanner can be improved. However, a separation between grid and field errors is also consistent with the interlocking targets 5 not possible.

To the exposure of the first layer takes place with the first pattern the photolithographic patterning of a second layer by means of a second projection device. For the second projection device For example, a wafer stepper becomes less critical layers used.

The first pattern comprises in addition to the already mentioned first substructures 50 and the second substructures 54 In addition, several first brands. For the second pattern also several second measuring marks are provided. The first measuring marks of the first pattern 21 are arranged on at least each side outside of the saw frame, wherein the first measuring marks are adapted to each form the first part of an overlay target. The second measuring marks of the second pattern are likewise arranged at least on each side of the sawing frame, wherein the second measuring marks are suitable for respectively forming the second part of the overlay target.

The first measuring marks of the first and the second measuring marks of the second Layer are, as discussed in the interlocking targets, in the form of a framework or a surface formed so that, for example, overlay targets as box-in-box or box-in-frame structures arise. The exact form of the first and second marks is for the implementation However, the process is not essential. So besides the ones described here Box-in-frame targets also other targets, such. Bar-in-bar targets with line-shaped first and second measuring marks or also first and second measuring marks, which in turn to avoid structure-dependent aberrations a Substructure have to be used. Others the expert known targets are not excluded.

With reference to the 6A to 6D In the following, the problem of correcting the exposure of several layers will be explained again.

First, the successive photolithographic patterning of a first layer of the semiconductor wafer takes place. This is done in the resist layer 14 a structure corresponding to the first pattern with the first projection device 5 successively transferred to the exposure fields. This is schematically in 6A shown.

In 6A are exemplary four exposure fields 22 on a semiconductor wafer 12 shown having a determined by the design of the first pattern length and width. These dimensions are in 6A schematically as a y-dimension 24 or x-dimension 26 located.

In an error-free lithographic projection step, the four exposure fields become 22 so mapped to the resist layer of the semiconductor wafer that the interlocking targets show no offset values.

For an asymmetrical error, the position of the exposure fields 22 ' for example, shifted or twisted in one direction. It is of course also possible that the location of the exposure fields 22 ' is shifted or twisted in both directions by a different value. As in 6B For example, mispositioning along the x-direction results in a distance 28 between two adjacent columns of exposure fields 22 ' ,

Around correcting this mispositioning becomes this offset value the first layer supplied to the simulation model of the first projection device. As already described above, is a breakdown in Interfeld- or Intrafeld posts not possible, so the correction for further exposures are performed solely taking Intrafeld errors into account. By measuring the interlocking targets thus becomes only a value for Intrafield error in the exposure of the first layer determined.

This results in subsequent exposure steps of the first layer, a multiple arrangement of the exposure fields 22 '' , as in 6C shown. The exposure field is corrected by correcting the asymmetrical interfield error as an intra-field error 22 '' now in the x-direction an enlarged x-dimension 30 on while the y-dimension 24 remained unchanged.

Table 3

After the first layer of the semiconductor wafer has been patterned with the first pattern, the first layer is exposed in the exposure fields 22 a successive photolithographic patterning of a second layer of the semiconductor wafer 10 according to the second pattern 32 , The photolithographic patterning is performed with the second projection device.

After the photolithographic projection, the first measuring marks and the second measuring marks of the overlay targets in all or in a few selected exposure fields on the semiconductor wafer are produced with an overlay measuring device 12 measured. Both the contributions of the intra-field errors and the inter-field errors of the second layer are determined. The parameters of the simulation model of the second exposure device 5 as already mentioned in connection with the 4 discussed, determined by minimizing the residual error. The values for intra-field errors and for inter-field errors of the second layer structured with the second pattern are transmitted to the second projection device, so that further exposures are performed in consideration of this correction.

As a result, the second layer will be placed on subsequent exposures with minimal residual errors, as in FIG 6D shown. However, since the wafer stepper can not correct for asymmetrical intra-field errors, due to the different first x-dimension in the x-direction 26 and second x dimension 30 An overlay error has occurred that could cause the integrated circuit to fail.

The inadequate correction of asymmetric errors is also in table 3 is shown using a manufacturing process with three layers, wherein the first two layers with a wafer scanner and the third layer with a Wafer stepper be lightened. Indicated are the means of the Based on the measured overlay values for several semiconductor wafers of a Production-free calculated parameters of the simulation model of the Projection equipment.

It can be seen that, with the corrections made so far, ie the determination of the intra-field errors of the first layer based on the interlocking targets and the determination of the intra-field errors and inter-field errors of the second and third layers on the basis of the overlay targets, the exposure with the Wafer scanner has only negligible errors. After exposure to the wafer stepper, however, asymmetric, ie in the x direction and y direction, very different, intra-field errors occur. However, these can no longer be corrected with a wafer stepper since the size of an exposure field can not be varied independently in the x-direction and y-direction. On the contrary, any asymmetrical interfield errors which may occur are also to be corrected during the exposure with a wafer stepper since the control of the substrate holder 10 can take place independently in the x-direction and y-direction.

In order to correct the remaining asymmetrical errors, parameters of the inter-field errors of the first projection device are subsequently calculated from the offset values 5 calculated. The parameters are in the first projection device 5 transfer, so that subsequent exposures with the first projection device 5 taking this correction into account.

It is also provided within the scope of the invention that the offsets calculated inter-field error of the first projection device in one suitable storage medium abge stores to a statistical Check the inter-field errors of the first projection device. This For example, it can be a value for the frequency and temporal stability of grid errors to determine.

As already mentioned above, Distortions often occur during exposure to wafer steppers or wafer scanners which are caused by lens aberrations of the projection devices and incorrect positioning of the overlay targets or interlocking targets to lead. Distortions in the structuring of the first layer and distortions in the structuring of the second layer according to the invention in the calculation the inter-field error of the first projection device are taken into account. This can, for example the values for Distortions of the first layer and the values of distortion of the second Layer corrected with the simulation model of the first projection device become.

In the following, an embodiment of the method according to the invention with reference to a flowchart of 7 summarized.

In a first step 100 the provision of a first pattern comprising a plurality of first measurement marks and a second pattern comprising a plurality of second measurement marks.

Subsequently, in step 102 a first projection device is provided, wherein the first projection device is adapted to perform an exposure in a plurality of exposure fields.

In step 104 the provision of a simulation model with a calculation rule for correcting the inter-field errors occurring during the exposure with the first projection device takes place.

Subsequently, in step 106 provided a second projection device.

In step 108 the provision of a plurality of semiconductor wafers takes place

For each Semiconductor wafers are subsequently the following steps are performed.

In step 110 the successive photolithographic patterning of a first layer of the semiconductor wafer corresponding to the first pattern with the first projection device takes place in the exposure fields.

In step 112 the successive photolithographic patterning of a second layer of the semiconductor wafer applied over the first layer takes place in accordance with the second pattern with the second projection device in the exposure fields.

Subsequently, in the step 114 Offset values of the first measuring marks to the second measuring marks determined.

Then in the step 116 the adaptation of the calculation rule for the first projection device based on the offset values, so that subsequent exposures are performed with the first projection device taking into account the inter-field errors.

5

exposure unit

10

substrate holder

12

Semiconductor wafer

14

resist layer

16

first light source

18

projection lens

20

reticle

21

first template

22 22 ', 22' '

exposure field first shift

24

y dimension

26

first x dimension

28

offset

30

second x dimension

32

exposure field second layer

40

Overlay meter

42

second light source

44

microscope

46

mirror

50

first substructure

52

ledger line

54

second substructure

100-116

 steps

Claims (19)

Method for correcting the overlapping of multiple layers in the lithographic projection by means of various projection apparatuses, the following steps being carried out: providing a first pattern and a second pattern for structuring a layer in the production of an integrated circuit, wherein the first pattern comprises a plurality of first measuring marks 50 ) and the second pattern several second measuring marks ( 54 ); Providing a first projection device ( 5 ), wherein the first projection device ( 5 ) is suitable, an exposure in several exposure fields ( 22 ) perform; Provision of a simulation model with a multiple-parameter calculation rule for correcting the exposure with the first projection device ( 5 ) occurring interfield errors; - Providing a second projection device; Providing a multiplicity of semiconductor wafers, the following steps being carried out for each semiconductor wafer: (a) successive photolithographic patterning of a first layer of the semiconductor wafer ( 12 ) corresponding to the first pattern with the first projection device ( 5 ) in the exposure fields ( 22 ); (b) successive photolithographic patterning of a second layer of the semiconductor wafer (above the first layer) ( 12 ) according to the second pattern with the second projection device ( 5 ) in the exposure fields ( 22 ); (c) determining offset values of the first measurement marks ( 50 ) to the second measuring marks ( 54 ) on the semiconductor wafer and (d) determining the parameters of the calculation rule for the first projection device ( 5 ) based on the offset values, so that subsequent exposures with the first projection device ( 5 ) taking into account the inter-field errors. The method of claim 1, wherein the step of Providing the first projection device includes that first projection device a wafer scanner is provided. Method according to one of claims 1 or 2, wherein the step the provision of the second projection device comprises that as the second projection device a wafer stepper is provided. Method according to one of claims 2 or 3, wherein the exposure field a size of about 25 mm Length and 35 mm wide. Method according to one of claims 1 to 4, wherein the step providing the first and second patterns comprises: - Arrange the first pattern and the second pattern within a substantially rectangular sawing frame; - Arrange the first measuring marks of the first pattern at least on each side outside the saw frame, wherein the first measuring marks are suitable, in each case the first part an overlay target; and - Arranging the second measuring marks the second pattern at least on each side of the saw frame, wherein the second measuring marks are suitable, in each case the second Part of the overlay target to build. Method according to Claim 5, in which the first measuring marks of the first pattern have the shape of a frame whose outer dimension approximately 30 μm in length and 30 μm width or less, and in which the second measuring marks of the second pattern take the form of a square area have, the outer dimension approximately 20 μm in length and 20 μm width or less. Method according to claim 5 or 6, wherein the step determining offset values of the first marks to the second Measuring marks comprises using an overlay measuring device that is suitable the offset between the first measuring marks and the second measuring marks to determine. Method according to one of claims 5 to 7, wherein the step the provision of the circuit design comprises - Provide first substructures in the first pattern, wherein the first substructures are suitable, in each case the first part of an interlocking target to build; and - Provide second substructures in the first pattern, the second substructures are suitable, in each case the second part of an interlocking target to build; The method of claim 8, wherein the first pattern at least four first substructures and four second substructures includes, each diagonally from a corner of the saw frame and outside of the saw frame be arranged so that they are together with the first substructures and the second sub-structures of adjacent exposure fields the Form interlocking targets. The method of claim 8 or 9, wherein the first Partial structures of the first pattern have the form of a frame, its outer dimension approximately 30 μm in length and 30 μm width is, and wherein the second substructures of the first pattern are the shape a square area have, the outer dimension approximately 20 μm in length and 20 μm width is. A method according to any one of claims 8 to 10, wherein the step of successive photolithographic patterning the first step is carried out the following step: - Determine a value for Intrafield error when exposing the first layer to the first Pattern by measuring the interlocking targets. The method of claim 11, wherein the step determining the value for Intrafeld error of the first layer includes that the interlocking targets measured with an overlay measuring device become. A method according to claim 11 or 12, further comprising the value for Intrafeld error of the first layer transmitted to the first projection device will, so that further exposures taking into account the correction the intra-field error was done become. Method according to one of Claims 1 to 13, in which the following steps are additionally carried out: determining a value for intra-field error of the second layer by measuring the overlay targets; and Determining a value for inter-field error of the second layer by measuring the overlay targets; The method of claim 14, further comprising the value for Intrafeld error of the second layer and the value for interfield error the second layer are transmitted to the second projection device, so that more Exposures under consideration this correction is done become. Method according to one of claims 1 to 15, wherein in addition Distortions of the first layer and distortions of the second layer considered become. The method of claim 16, wherein the step determining offset values of the first marks to the second Measuring marks includes the values for distortions of the first layer and the values for Distortions of the second layer based on the simulation model of the first projection device Getting corrected. The method of claim 17, wherein the simulation model of the first projection device includes a calculation rule with parameters that are appropriate is, intra-field rotation error, intra-field magnification error, inter-field rotation error, Inter-field magnification error and translation errors in two coordinate directions, respectively describe. Method according to one of claims 1 to 18, wherein the step determining offset values of the first marks to the second Measuring marks above In addition, the interfield error calculated from the offset values includes of the first projection device be saved to a statistical control of the interfield error of the first projection device perform.