DE102004007409B4 - Non-conforming manufacturing method for a semiconductor structure - Google Patents

Abstract

Manufacturing method for a semiconductor structure with the steps:
Providing a semiconductor substrate (1) with a trench (5); and
Depositing a doped silicon fill layer (10b) to fill the trench (5) and cover the surrounding structure by a non-conforming deposition method having a non-conforming deposition rate caused by a doping concentration gradient, thereby at least partially filling the trench (5) from bottom to top ;
wherein prior to depositing said fill layer (10b), a step of depositing a liner layer (10a) of undoped silicon to line the walls and bottom of the trench (5) and cover the surrounding structure; and wherein AsH ₃ , SiH ₄ and H _{2 are used} as process gases, the ratio of mass flows AsH ₃ : SiH _{4 is} between 0.0781 and 0.109 and the over-conformity is between 120 and 150.

Description

The The present invention relates to a manufacturing method for a semiconductor structure.

From the EP 0 429 885 B1 For example, a semiconductor structure fabrication method is known in which a doped silicon fill layer for filling a trench and covering the surrounding structure is formed by CVD deposition in a reactor that is diffusion-conforming. In this known method, a liner layer of thermal silicon oxide is provided in the trenches prior to deposition.

The EP 0 591 082 A2 describes overconforming deposition from a fill layer of doped silicon to fill a trench and cover the surrounding structure, wherein the over-conformity is achieved by collimating the deposition source.

The US 5,863,598 describes a CVD method for depositing doped silicon on a substrate, wherein the step coverage is defined as a function of the ratio silane gas / doping gas.

The JP 01039019 A describes a super-conforming silicon deposition by means of a laser beam CVD method.

The US 5,956,602 A describes a method of depositing a silicon film in which breaks for doping occur.

The US 5,141,892 A describes a method for filling a trench with polysilicon by fixing the deposition of doped and undoped silicon layers and a final annealing step.

Out SHIM, K.-H., et al.: Low-temperature growth of in situ phosphorus-doped silicon films: two-step growth utilizing amorphous silicon buffers, Thin Solid Films, Vol. 369, 2000, pp. 185-188 discloses a low temperature deposition process of in-situ doped silicon with respect to the quality of the silicon layer to improve that an undoped silicon layer as Liner layer is used.

Even though in principle be applicable to any integrated circuits The present invention and the underlying problem in relation to integrated trench capacitor memory circuits in silicon technology explained.

at the scaling of structures of integrated memory circuits In silicon technology trenches with high aspect ratios often occur on, in particular in memory circuits with so-called deep trench capacitors (DT≡ "deep trenches"). Typically to lead these aspect ratios for structures below of 100 nm partially at an opening angle of the order of 0.1 °. This very much steep profiles make it increasingly difficult to dig the trench structures with conductive fillers, such as. As doped polysilicon, to fill.

In spite of Sophisticated deposition process does not succeed in such trench structures to fill, without voids (ie cavities ≡ "voids") or seam seams in the trench this tendency is naturally reinforced, if it comes even to the slightest profile fluctuations. All known processes in LPCVD batch furnace processes achieve this only step covers, which are smaller than 100. The Voids are particularly disadvantageous in subsequent recessing steps and increase that Film resistance of the filling.

2 illustrates such problems as occur in a conventional manufacturing process of a semiconductor structure.

In 2 denotes reference numeral 1 a silicon semiconductor substrate into which one of a pad oxide layer 2 and an overlying pad nitride layer 3 existing hard mask a ditch 5 has been etched. The trench depth d1 is typically 6 μm to 8 μm. By means of an LPCVD batch oven process is a fill layer 10 from arsenic doped amorphous silicon has been introduced into the trench, which has a seam seam S and a voids V in the trench, wherein the voids depth d2 is typically 1 micron to 1.5 microns.

3 shows an exemplary approach to solving the problems that in the conventional manufacturing method of a semiconductor structure after 2 occur.

At the in 3 As shown in the exemplary approach, a taper T has been provided at the top of the trench and at the hard mask to provide a V-shaped upper opening of the trench. This creates a relaxation of the conditions for the deposition of the filling layer 10 of amorphous arsenic doped silicon. By this structural measure can thus avoid the formation of voids V. However, this structural measure requires additional space, which precludes increasing miniaturization of the integrated components. Also, the taper T in semiconductor memory devices with trench capacitors disturbs the available trench depth and thus the achievable storage capacity.

Therefore It is an object of the present invention, a manufacturing method for one To provide a semiconductor structure that eliminates the above filling problems, without that the trench structure must be modified.

According to the invention this Problem solved by the manufacturing method specified in claim 1.

The The idea underlying the present invention is that a deposition process for the filling layer to provide, which a überkonforme Deposition rate. In other words, the deposition rate decreases into the depths of the ditch to, so that the ditch as it were from bottom up with the fill layer accrues. Accordingly, it does not interfere with the formation of voids or cavities. A previously deposited liner layer of undoped silicon creates an optimized starting position.

Of the inventive deposition process let yourself in both LPCVD batch furnace processes and CVD single wafer reactor processes realize.

In the dependent claims find advantageous developments and improvements of respective subject of the invention.

According to one Another preferred embodiment is after the deposition of filling layer a step of depositing an overcoat of undoped silicon to the full Fill up trenching and covering the surrounding structure.

According to one Another preferred development is the over-conforming deposition process a gas phase separation process in a batch reactor or a Single wafer reactor.

According to one Another preferred development is the deposition of a filling layer performed in at least two steps and between steps an in-situ doping step to generate an additional one Doping the filling layer carried out, a tempering step for activating and outdiffusing the doping the filling layer carried out becomes.

According to one Another preferred embodiment is on the semiconductor substrate leave a hard mask previously used to make the trench.

embodiments The invention is illustrated in the drawings and in the following Description closer explained.

1a - e show schematic representations of successive process stages of a manufacturing method of a semiconductor structure as a first embodiment of the present invention;

2 shows problems that occur in a conventional manufacturing process of a semiconductor structure; and

3 shows an exemplary approach to solving the problems that in the conventional manufacturing method of a semiconductor structure after 2 occur.

In the same reference numerals designate the same or functionally identical Ingredients.

1a - e show schematic representations of successive process stages of a manufacturing method of a semiconductor structure as a first embodiment of the present invention.

In 1 denotes reference numeral 1 a silicon semiconductor substrate in which by means of one of a pad oxide layer 2 and a pad nitride layer 3 existing hard mask a ditch 5 with a depth d1 of typically 6 microns to 8 microns has been introduced.

In a first process step is over the structure with the trench 5 and the hard mask 2 . 3 a liner layer 10a deposited from amorphous, undoped silicon of typically 10 nm to 15 nm thickness at 500 ° C. This can be done for example in an LPCVD batch oven. This process step is to provide a surface with less roughness for the following filling steps.

Regarding 1b Then, the deposition of a filling layer 10 b made of doped silicon for filling the trench and covering the surrounding hard mask structure by means of a non-conforming deposition process. The ditch grows 5 from bottom to top so that the thickness of the deposited silicon layer in the lower region t _{U is} greater than the thickness of the deposited silicon layer in the upper trench region t _o , as in 1b indicated by corresponding arrows.

The cause of the overdecorresponding precipitation rate lies in a concentration gradient of the dopant in the trench in the present gas-phase deposition, wherein SiH _{4 are used} as filler gas and AsH ₃ (or an alternative n-type doping gas such as PH ₃ ) as the dopant gas.

The diffusion of the Dotierstoffspezies namely decreases with increasing trench depth, so that the doping profile of the filling layer DF, which is also in 1b is shown to have a negative gradient with respect to progressing trench depth.

If the resulting dopant concentration of the filling layer 10b is insufficient, the overconforming deposition process can be carried out step by step, with an in situ doping step between individual steps for generating an additional doping D1 or D2 in FIG 1b is carried out.

typical Process conditions for such a overconfident Separation process in a LPCVD batch reactor and in a CVD single wafer reactor are listed in the table below.

In 1c the dependence of the conformity on the ratio AsH ₃ / SiH _{4 is shown} .

Clear it can be seen that the over-compliant e range to a certain ratio range of these process gases is limited.

Continue with reference to 1d is shown the process state in which the filling layer l0b the ditch 5 has almost completely filled, the filling is void-free and there is only one seam seam SN in the trench where the opposite grown-up layers collide.

Regarding 1e then becomes an amorphous, undoped silicon layer L0C deposited over the resulting structure, which is planarized in a later chemical-mechanical polishing process.

Finally, in a final process step, the activation and outdiffusion of the dopant in a high-temperature annealing step, for example, at 1100 ° C in N ₂ atmosphere for a period of 20 minutes, alternatively, the activation of the dopant by a process flow in the sequence provided (eg Oxidation step) of high temperature steps.

Even though the present invention above based on a preferred embodiment It is not limited to this, but in many ways and modifiable.

Especially the invention is in principle for Any trench structures applicable.

1

Semiconductor substrate

2

pad oxide layer

3

pad nitride layer

5

dig

d1

grave depth

d2

Lunkertiefe

10a

undoped liner layer

l0b

gradually doped filling layer

L0C

undoped topcoat

t _u

thickness the filling layer in the lower trench area

t _o

thickness the filling layer in the lower trench area

SN

hem seam

C

concentration

d

depth

V

Lunker

T

Taper

DF

doping profile the filling layer

D1, D2

additional allocations

Claims (6)

A semiconductor structure manufacturing method comprising the steps of: providing a semiconductor substrate ( 1 ) with a ditch ( 5 ); and depositing a filling layer ( 10b ) of doped silicon for filling the trench ( 5 ) and covering the surrounding structure by means of a non-conforming deposition method which has a non-conforming deposition rate caused by a doping concentration gradient, whereby the trench ( 5 ) is at least partially filled from bottom to top; wherein before the deposition of the filling layer ( 10b ) a step of depositing a liner layer ( 10a of undoped silicon for lining the walls and the bottom of the trench ( 5 ) and covering the surrounding structure; and wherein AsH ₃ , SiH ₄ and H _{2 are used} as process gases, the ratio of mass flows AsH ₃ : SiH _{4 is} between 0.0781 and 0.109 and the over-conformity is between 120 and 150. Method according to claim 1, characterized in that after the deposition of the filling layer ( 10b ) a step of depositing a cover layer ( 10c ) of undoped silicon to completely fill the trench ( 5 ) and covering the surrounding structure. Method according to one of the preceding claims, characterized in that the überkonfor me deposition method is a gas phase separation method in a batch reactor or a single-wafer reactor. Method according to one of the preceding claims, characterized in that the deposition of a filling layer ( 10b ) is performed in at least two steps and between the steps a doping step in situ for generating an additional doping (D1, D2) of the filling layer ( 10b ), and in that an annealing step for activating and out-diffusing the doping of the filling layer ( 10b ) is carried out. Method according to one of the preceding claims, characterized in that on the semiconductor substrate ( 1 ) one for producing the trench ( 5 ) previously used hardmask ( 2 . 3 ) is left. Method according to one of the preceding claims, characterized in that the temperature is 530 ° C, the pressure 40Pa, the gas flow of AsH ₃ 20-40 sccm, the gas flow of SiH ₄ 0.64 slm and the gas flow of H ₂ 60-70 sccm is.