DE102004006102A1 - Search machine architecture for a packet network router in which ternary content-addressable memory is combined with conventional dynamic RAM to enable the use of very large routing tables for quick packet forwarding - Google Patents

Abstract

Search machine architecture for a packet network router combines ternary content-addressable memory with conventional dynamic RAM by use of the physical properties of the dynamic RAM. This enables use of very large routing tables to quickly forward packets in a hardware based manner.

Description

Of the Invention is based on the object, a router for packet-oriented To build data networks, the packet routing even with very large route tables very fast, without breaking the limits of cost-effectiveness.

Previous routers rely on a tree-oriented representation in a conventional memory such as in EP1155537 or US5909440 described or on a nested representation as in US6631419 shown. Conventional memory is nowadays very inexpensive with large capacity available due to considerable progress of semiconductor technology, the common name in the art for this is RAM (Random Access Memory).

The offer the largest capacities doing dynamic memory (DRAM), where information through a charge of a capacity represents is and only another MOS transistor for coupling the memory matrix is needed becomes. However, dynamic memory has the disadvantage of having a Fast addressing only within an already selected page and line of a memory matrix possible is because in the process of selecting this page and line loads transferred from the storage capacitors of each row in the sense amplifier and previously the contents of the previously selected line by a return transfer again must be made (Precharge). On the other hand, one or more bits may be held by one in the sense amplifier Line can be accessed very quickly by a multiplexer or burst transfer.

A Another alternative is the use of static RAM memory, these keep the information fed back Memory cells, which can take two states statically anyway. The access can apply here to every single storage element without the limitations charge transfer, however, each memory cell requires significantly more space on the semiconductor, as a variety of space-consuming MOS transistors per memory cell is required.

It is usual also a coupling of dynamic memory with static memory by so-called cache architectures, thereby becoming necessary whole data blocks transferred from the dynamic to the static memory to there for expected future Accesses for quick retrieval.

For use In network routing, however, this architecture has the disadvantage that with suddenly rising Traffic in different directions for example through rampant computer virus programs (also called "bad weather condition" in the professional world called) extremely many accesses to different addresses take place and thus a cache architecture, regardless of whether it refers to the RAM or already found routing destinations, loses its advantage and this by the additional Administrative effort can even turn into a disadvantage, in extreme cases this already to network breakdowns guided.

Another approach is the use of simple content-oriented memory, abbreviated CAM (Content Addressable Memory), as it is used in US6658002 is used.

at Content-addressable memory is typically static RAM and each memory cell associated with a comparator. If a data word is now applied to the memory, then one recognizes Memory line using the comparator a full match and thus, for example, gives a signal to a priority encoder, which in turn codes the address of the line from this. A typical one Field of application is the resolution of MAC addresses on a local IEEE 802.3 LAN network in mapped Switch ports or IP addresses.

A another possibility is the use of ternary content-addressable memory, abbreviated TCAM. This storage type becomes common not used in conventional computer systems, but became primary for network hardware designed to make a quick routing decision for certain Destinations based on the IP address or to filter measures based on the source and destination address. This is located as a special feature of this type of memory to two memory cells for each One bit is a logic circuit that stores the contents of these memory cells compared with a created data pattern. It determines that first bit of a memory cell pair, which data bit is expected while the second bit sets, if any a comparison should take place, this bit is therefore also as a mask bit as it is the comparison result for this ternary memory cell masked if necessary. Alternatively, a bit may also have a compulsory one date or alternatively do not select a comparison while the other bit determines a compulsory zero date or no comparison that Conversion between both representations results from a simple Logic table.

In the TCAM memory is now in addition to the usual read / write normal RAM in the possibility that the memory field, an external data word for comparison purposes is created. In order to be able to determine a match for a data word within the memory field with the external data word, all logic circuits of the memory cell pairs of a data word must agree to this determination (AND link), either by detecting a direct match of the respective data bit or by the mask bit of the memory cell pair signals that no match is necessary. Since there are at least three sensible states for a memory element ("equal-one", "zero-zero", "no-compare-required"), this memory type is also referred to as a ternary content-addressable memory, even if, for example, with "data word disabled" on fourth state for a memory cell pair would be conceivable.

Provided is found by such a comparison, a data word is either directly the address of the data word returned or over this Address Index addressed another static RAM memory, which its associated data for that word, e.g. a pointer to an object, to return can. In the IP routing area you will usually find the address of the subsequent router and the name of the destination interface.

adversely is, however, that despite advances in semiconductor technology so far only relatively small memory sizes in the region up to a maximum a megaworld can be realized, also have TCAM memory one relatively high power dissipation. Already today's global routing table let yourself only under considerable restrictions or store costs in such a store, which is why he mainly for switches with only local targets.

On the other hand Represents the planned migration of global Internet routing from 32 bit addresses within the scope of the IPv4 protocol to 128 bit addresses in the context of the IPv6 protocol completely new demands on the Internet Routers that are insufficiently met by today's devices and therefore currently a limitation of the IPv6 condition on only provideraggregierbaren address space, which is the goal of a lifelong allocation of an address space a person, organization or to a device completely contrary to and thus very much question the commercial success of the new IPv6.

One special problem is the mixture very large with a multitude of small address ranges, this leads to a tree-oriented search too big Tree depths and long seek times, while prohibiting the size of the routing table by far a complete filing in a TCAM memory alone because of economical reasons.

The problem is solved according to the invention by the device described in claim 1, whose function will be explained below with reference to an embodiment:
The individual routing destinations are represented by table entries which on the one hand describe the area to be routed and on the other hand contain the forwarding information such as the address of the next router (Next Hop), the outgoing interface and possibly further filtering and processing rules. It is also possible to encode the data source in order to be able to combine several separate routing tables, for example for virtual routers.

Several table entries are now combined by means of a suitable algorithm to provide this in particular cluster algorithms or in an advantageous execution the invention according to dependent claim 12 also algorithms with defined partition criteria similar to one B-tree on.

To The grouping of the table entries will now be related entries in a row a dynamic RAM memory and that of this DRAM line assigned entry in the TCAM memory set so that only all the Cluster common bits of the destination address in the TCAM marked as valid On the other hand, all bits which have distinctions are masked out become.

There the TCAM is typically one according to the order of entries priority assigns, can according to dependent claim 11 also a hierarchically shared address range well mapped become. So can For example, multiple destinations with small address ranges in one DRAM line, which in turn, in the case, that none of these areas is hit, by default entry the parent larger address range refers. This one would also directly through its lower priority entry in the TCAM found if the address is not within the cluster of the small Goals and therefore equal this lower prioritized, but a larger address range covering entry with its associated DRAM line to bear comes.

The actual perception of these administrative tasks described here is usefully done by running on a control computer Software, the administrative tasks are in contrast to the actual Process of packet forwarding usually not time critical.

In the embodiment of the invention described below is exactly its application for the rapid determination of packet forwarding information shown, the individual destination address ranges for the destination addresses of the data packets assigned.

As Figure 1 shows the query when the destination address arrives of the TCAM memory (TC1), this becomes in the case that the address in the address range of a known routing entry, an index output. This can now according to dependent claim 2. by means of direct coupling to the dynamic DRAM memory or the associated controller of the memory, in the latter case typically consisting of multiplexers and registers in the address path to the DRAM, used to address a row of the DRAM memory.

A another possibility is the previous conversion of the index to an address using an arithmetic unit according to dependent claim 3., for example, an offset for multiple use of the DRAM also for to create other storage or different tables various virtual routers to address.

According to one particularly advantageous embodiment according to the invention according to claim 4. finds another, in particular static RAM for determining the address mapping Use, thereby need with dynamic changes the routing table according to new incoming routes via dynamic protocols no data blocks in dynamic RAM are moved, it is sufficient for this, during shifts as a result of priority changes in the TCAM the mapping of the index values to the DRAM pages and lines in the further static RAM to change. It makes sense to be in the assignment of the TCAM memory initially gaps completely invalid search words To keep clear here, too, a shift of whole areas initially avoid. However, if this is no longer possible, then according to dependent claim 4 at least one data shift in the DRAM largely avoided. This variant was selected in Figure 1 with the mapping RAM (MR1).

After this the page and row address is present at the dynamic RAM (DR1), Now this memory can be given the command to read the selected line become. The process is inventively by a control logic (CL1) initiated, which in the presence of the index and after executed address translation becomes active. For the Now following search within the line can do this either be kept open or it will be the entire contents of the line a burst mode into an intermediate register or cache transferred and immediately the precharge to prepare for the next access triggered.

Here shows the particular advantage of the invention: By the unique Assignment of a cluster of entries to a row of the DRAM Memory is avoided further time consuming access, nevertheless can be cheaper DRAM memory can be used to hold an extremely large table. The slow line access speed of the DRAM is thus defused.

After this The contents of the line can now be accessed quickly This line continues the search for the destination address. In the example shown in Figure 1, this makes a search engine (SE1), it also provides the forwarding data for the package. Just like that However, the use of the main CPU of the router is conceivable. These is usually required anyway for the maintenance of the data in the various memory modules. According to dependent claim 5. The routing destinations are filed as areas, taking for further search In principle, only one range limit or one cut-off value is required.

A another possibility is the immediate storage of the start address of a destination address block and the size of this Blocks, in particular the coding of the number of valid address bits in the common IP prefix notation according to dependent claim 6. makes sense.

Especially advantageous is the latter coding in interaction with a parallel Comparator according to dependent claim 9. A particularly high search speed results in an immediate on the DRAM integrated parallel ternary register, which over the - accordingly the number of address entries stored in the line strung together - searched Address, if necessary plus skipped by masking Data fields, is queried. about priority encoder may be the same Determined area, from which immediately follows the sought Entry.

however let yourself also with commercially available standard memory modules perform a quick search within the selected DRAM line Advantageous way is with the sorted bin and a binary search in Under claim 7. described.

Especially simply designed a search in hardware, if according to dependent claim 8. For example, always two bits of the relative address of the entry be replaced in the DRAM line.

An example should clarify this: Gege Let ben be a relative binary start address 1000. If the first comparison results in a match, the search is completed. For a searched data word, which is smaller than the entry at the start address, the top two bits are replaced by the pattern 01, thus results in 0100 as the next address for an entry to be tested. In the case of a larger data word, on the other hand, the top two bits are replaced by the pattern 11, so 1100 is created as the next test address. In the former case, a hit can again be made directly under 0100, or it is now shifted by one bit to the right, the address by replacement according to the same scheme, but now for the second and third most significant bit, 0010 for a smaller keyword or 0110 manipulated. In the second case, if no direct hit was achieved, 1010 is searched for with a smaller search word or 1110. In this case, it would continue without hits at 1101 or 1111, then the search is completed.

The relative address 0000 is never reached in this procedure, it is obvious, this to save the default entry according to dependent claim 11 to use.

A different possibility is the use of a hash function according to dependent claim 13. The simplest Case of a linear hash offers itself here, by means of barrel shifter the first bit, which due to masking no longer by the TCAM Entry is uniquely determined as the topmost bit of the line-relative Address to use following bits following this bit accordingly with postponed. As a result, for example, the TCAM entry a / 20 IP Prefix cover, the hash key could then be for example 64 entries code one / 26 network per DRAM line, whereas one / 25 Network on two / 26 entries would be distributed.

A another possibility is the combination of a burst transfer according to dependent claim 14 with a Sequential search according to dependent claim 15., this process only works for smaller DRAM line lengths and fast DRAM's otherwise the sequential search takes too much time takes.

Of course you can the target address described here also contain further data encoded, for example information about the selection of one of several available routing tables or one Protocol type, a desired Service class or service quality or data path bandwidth.

As a general rule The invention is not only suitable for determining targets of Data packets, obvious is first the shared use of a such device in a router for the realization of filter lists for certain Source and destination addresses or protocols, here is also a staggered multiple search in the selected DRAM line possible.

Furthermore, the application as a database processor is conceivable, or even the use as an optional unit of a central processing unit (CPU) of a computer to support garbage collection, as described in the following example:
A conventional computer is used, with a special command to store pointers to data blocks. Hereby, when a pointer is written to the conventional memory, the main CPU signals the pointer property over a line, the ancillary unit can then store the pointer's destination address in a free entry of a DRAM line of the invention defined by the destination address and pointer address combination , Now, if the pointer is changed, it can be quickly discharged again by previously reading the old destination address and recombining with the pointer address to the search word. In the case of examining a memory block in the context of garbage collection, the base address of this block can now be used as a search term shortened to only the destination address by means of a mask; the invention then provides a list of the affected pointers which are to be corrected when this block is moved. With a zero result of the search, the block is no longer referenced and can be released.

Claims (15)

Data processing device for rapid search of data words in a database, in particular for the search of network address ranges based on a given address, here again preferably for quickly determining the forwarding information of a data packet in a router or switch in a data network based on the destination address of the data packet, characterized in that (1) the data word to be found, in particular the destination address, initially to at least one ternary content addressable memory (hereinafter called TCAM) is applied for query, the TCAM assigns by parallel comparison of the applied data word with its contents the data word at least one index of a matching content data word the TCAM, wherein the comparison is limited to selected bits per content data word due to the ternary nature of the memory, and in the case of no such partially matching content data word, this search is terminated, (2) the index thus determined and output by the TCAM via at least one address assignment of at least one page or row address of a dynamic RAM memory (hereinafter also generally referred to as synchronous dynamic memory DRAM (3) at least one page or row of the DRAM addressed after the index has been provided and after execution of the address assignment by a control logic, in particular a sequence control started with the successful provision of the index, selected and read - in particular by charge transfer in the sense amplifier or row register - is opened, (4) in the thus provided data of the page or line, a further conventional search for at least one entry matching the data word is performed. The access to this data can be done either directly or via at least one intermediate logic or at least one intermediate register or at least one cache memory. Device according to claim 1, characterized that the assignment to (2) is a linear assignment of the index to the page or row address is, which by direct assignment of the index signal lines to the address lines of the dynamic RAM memory becomes. Device according to claim 1, characterized that the assignment to (2) by at least one arithmetic arithmetic unit made from the index by means of predetermined calculation rule becomes. Device according to claim 1, characterized that the assignment to (2) by means of at least one further assignment memory, especially static RAM memory, is produced thereby, that the index is created as an address to the branch memory and the data word thus addressed in that allocation memory Includes page or row address of the DRAM. Device according to claim 1, characterized that the entries to (4) in the page or row of the DRAM area boundaries, in particular Upper or lower limits are or for the separation of two areas are suitable intermediate values (division values). Device according to claim 1, characterized that the entries to (4) in the page or row of the DRAM address prefix from base address and prefix length - the latter in particular encoded as the number of valid address bits - are, where the prefix length indirectly the size of the address range of the respective entry whose dual logarithm encodes. Alternatively, the prefix length can also stored as a bit mask, which encodes the address-relevant bits be. Device according to claim 1, characterized that the associated entries to (4) are stored sorted in the page or row of the DRAM and the conventional search a binary search or a tree search is. Device according to claim 1 or 6 or 7, characterized characterized in that the associated entries to (3) in the respective Page or line of the DRAM are stored in such a way that this in the Frame of a binary Search by iterative formation of the page or line relative (column) Address can be found. For this purpose, starting from a starting address step by step a bitwise address change, in particular on adjacent bit pairs starting from the most significant Address bit, performed in this way, that first a comparison of the searched data word with that at this time addressed entry and, if not immediately a match is determined, depending from the comparison result a replacement at the to this iteration belonging Replacement point in the address word according to a fixed substitution rule is made and then the next iteration step started becomes. Device according to claim 1, characterized that for faster search of the data word to be found after the Access to the page or row address of the DRAM in parallel multiple Contents of the thus addressed page or row of the DRAM in a parallel Comparative unit to be conducted. Device according to claim 9, characterized again, the comparison unit is a ternary register or another ternary storage This can also be in the form of a cache memory on the DRAM chip itself integrated. Device according to claim 1 or 5 or 6 or 7. or 8., characterized in that for at least one side or Line of the DRAM there is another (default) entry which then selected in the context of the search if it does not find a more appropriate entry in this line, in particular, a hierarchical nesting of address prefixes to map efficiently to the database. Device according to claim 1, characterized in that for the construction of the content data words of the TCAM at least one defined division criterion and in the case of dynamic changes of the database content at least one summing criterion is used, which in case of overflow of one page or row of the DRAM due to further required entries distribution to others Sets pages or rows of the DRAM uniquely and leaves only the bits common to all entries of a page unmounted as valid bits in the corresponding TCAM content data words. In the case of dynamic changes, the summary criterion si If a page or line is not used, it may be merged with its logical neighbors. Device according to claim 1 or 5 or 6, characterized characterized in that each index value of the TCAM or each page or row address of the DRAM another data word, which in particular the starting position of the first masked bit of the respective TCAM Content data word encoded, assigned to form a hash key is, which in particular by bit shifting of the search data word with a displacement distance derived from the starting position can be won. Based on this hash key can then in the selected Side or row of the DRAM at least one with high probability directly matching entry can be used for comparison. Device according to claim 1, characterized that to carry look for a burst transfer of the page or row data from the DRAM is made. Device according to claims 14 and 5 or 14 and 6., characterized in that the data in the context of burst transfers immediately be passed to a comparator successively, which is based on the range boundaries or based on the expanded to a mask Prefix length specification, which the difference from the base address of the address prefix and the searched Address masked, or based directly on the page or line filed mask data a matching address prefix as a result the search determined. The difference is here in particular by an exclusive or surgery formed.