DE10134230A1 - Integrated semiconductor memory component with active ON/OFF signal separating circuit - Google Patents

Abstract

The signal separating circuit (2) is activated by a release circuit (3), and there is also a clock pulse generating circuit (4) for ON/OFF of the signal separating circuit, dependent on external system clock (5).The clock pulse generating circuit contains a delay-or-phase-rigid circuit, whose clock pulse signal (DLL-clock), is synchronized with system clock. A clock signal (OCD) is supplied to data output driver circuit (6).

Description

The invention relates to an integrated Semiconductor memory component that can be actively switched on and off Signal termination, an enabling logic circuit to enable the Signal termination and a clock generating circuit, which, depending on a system clock supplied from outside, an internal clock signal (DLL clock) at least for clocked switching on and off of the signal termination generated.

Those currently under development highly integrated semiconductor memory devices provided active Signal termination circuit that can be switched on and off must be used Adherence to precise timing conditions for the data that is about a bidirectional bus between the Semiconductor memory component and, for example, a controller module be transmitted, switched on and off clock-controlled.

The accompanying FIG. 4 shows a signal-time diagram which shows the time relationships when the signal termination is clocked in a highly integrated semiconductor memory component.

A clock signal (internal clock) is generated internally from a system clock 5 supplied to the semiconductor memory component, and this internal clock clocks the switching on of the termination when an enable signal EN generated by an internal enable logic is logic 1. The internal clock is generated based on the system clock with a delay τ _CLOCK , while the switch-on time of the completion is generated based on a leading edge of the internal clock with a time delay τ _CLOSE . The situation when switching off is similar. The switch-off time is controlled with the same time delay τ _CLOSE depending on a leading edge of the internal clock.

The illustrated and described above in FIG. 4 previous use of the internal clock signal has the disadvantage that the delay times τ and τ _{CLOCK STATEMENTS} of the voltage, the manufacturing process and temperature dependent. At the same time, the clock period T of the system clock 5 is dependent on the frequency. As a result, it turns out that the switch-on / switch-off times of the termination vary relative to the system clock 5 . For this reason, the switch-on and switch-off times, as seen from outside the semiconductor memory component, cannot be defined exactly. This uncertainty means that large tolerances have to be taken into account for the signal time specification of the external system in order to take into account the "worst case" time conditions. This solution therefore has disadvantages, since the system efficiency and the data throughput are reduced.

It is an object of the invention, a generic Integrated semiconductor memory device with an improved Precision of the switching on and off during active completion to enable, in particular when connecting the Semiconductor memory component to a bidirectional bus Conflicts and resulting signal interference on the Avoid signal lines.

To solve this task, it is the rhythm of entering and leaving Turning off the clock generating circuit generating the termination a delay locked (DLL) or a phase locked (PLL) Clock generation circuit which is one of the internal Enable logic circuit supplied clock signal generated with the Semiconductor memory component supplied from the outside System clock is synchronous and the one with the clocking of the Memory device output data matching time Location.

This precise timing of the entry and exit Deactivating the completion of the Semiconductor memory component can be connected to a bidirectional Use the signal bus more efficiently since the previously required Waiting times when switching on and off the degree and Signal conflicts are avoided. In one Semiconductor memory component, for example one that can be operated in DDR operation SDRAM, in which the driver circuits for the output data are driven by the same precise clock signal as the mentioned signal termination, you save yourself a second DLL or PLL clock generation circuit and also for it necessary internal chip wiring that would be necessary if separate clock signals each for clocking the Output data driver and signal termination are used.

An exemplary embodiment of a semiconductor memory device according to the invention with reference to the Drawing explained in more detail.

The drawing figures show in detail:

Fig. 1 shows schematically a block diagram of a bi-directional signal bus connected to a semiconductor integrated memory device according to the invention;

Fig. 2 in table logic signal conditions on and off of the accounts;

Fig. 3 is a signal timing diagram illustrating the timing relationships in the inventive clocked switching on and off of the completion and

Fig. 4 shows the signal timing diagram already described, which illustrates the disadvantageous way of clocked switching on and off of the termination.

In Fig. 1 an integrated semiconductor memory device 1 includes an internal signal termination circuit 2, the clock-controlled by a finish clock (AT-clock), and when an enable signal EN assumes a defined logic value, switched on or off. An activated termination of the signal firing circuit 2 terminates signal lines of a bidirectional bus 11 , for example signal lines that lead output data DQ from an output data driver circuit 6 to a memory controller 10 . The enable signal EN is generated by an enable logic circuit 3 as a function of further input signals 8 that are not specified. Further essential components in the semiconductor memory component 1 are a delay-locked or phase-locked clock generation circuit 4 , which generates a clock signal “DLL clock” in delay-locked or phase-locked time relation to a system clock supplied to an external connection 5 . A circuit unit 9 generates an internal clock for clocking further (not shown) circuits of the memory component 1 . A circuit block 7 denotes data receivers. According to the invention of the termination circuit 2 supplied AT-cycle of the generated by the DLL or PLL circuit 4 DLL clock. Furthermore, the invention proposes that the clock "OCD clock" supplied to the driver circuits 6 for the output data DQ is the same DLL clock generated by the DLL or PLL circuit 4 .

Fig. 2 is a truth table shows in the form of the logical conditions on and off of the signal conclusion by the termination circuit 2: when the enable signal EN is a logic "0", the closure 2 through the circuit 2 with the leading edge of the AT-clock is the is equal to the DLL clock, switched off. In contrast, the termination 2 with the leading edge of the AT clock (= DLL clock) is switched on when the enable signal EN is logic "1".

The time relationships when the closure is switched on and off are explained in the signal-time diagram of FIG. 3. The "DLL clock" clock generated by the DLL or PLL clock generation circuit 4 , which is shown in the second line of FIG. 3, is compensated for voltage, process, temperature and frequency changes. This makes it possible to make the time delay τ _DLL between a leading edge of the DLL clock and the switch-on transition of the termination so large that the termination is switched on with the system clock 5 , ie with its leading edge. Thus, τ _DLL = τ _{CLOSE the} same temporal relationship applies when the termination is switched off, if the enable _signal EN has logic "0".

In a preferred development, the DLL clock generated by the DLL or PLL clock generation circuit 4 from the system clock 5 is also the same as the OCD clock which is used to clock the output data drivers 6 . The circuit outlay on the semiconductor memory component is thereby reduced.

By using the DLL clock generated by the DLL or PLL clock generating circuit 4 from the system clock 5 for switching the termination 2 on and off and, as preferred, also for switching the output data driver 6 on and off, since the switching on and the switch-off time of the termination 2 is brought into agreement with the edges of the system clock 5 , a more efficient use and increase in the data throughput of the signal lines of a bidirectional bus system 11 is made possible because the signal lines can be terminated with very small time tolerances, so that no signal conflicts occur. Reference numeral list 1 semiconductor memory device
2 termination circuit
3 enable logic circuit
4 DLL / PLL clock generation circuit
5 system clock
6 output data drivers
7 receiver circuit
8 external control signals
9 internal clock generation
10 memory controllers
11 bidirectional data bus
DQ output data
EN enable signal
AT clock rate, which is fed to the termination circuit 2
DLL clock clock output from the DLL / PLL circuit 4
OCD clock Clock for the output data drivers
τ _CLOCK Delay between the internal clock and the system clock
τ _TERMINATION ; Delay between the internal clock and the closing on or off
τ _DLL delay between the DLL clock and the system clock

Claims (4)

1. Integrated semiconductor memory component, which has an actively switchable signal termination ( 2 ), an enabling logic circuit ( 3 ) for enabling the signal termination ( 2 ) and a clock generating circuit ( 4 ) which, depending on a system clock ( 5 ) supplied from the outside Internal clock signal generated at least for the clocked switching on and off of the signal termination ( 2 ), characterized in that the clock generating circuit ( 4 ) has a delay-locked or phase-locked clock generating circuit, the clock signal (DLL clock) supplied to the enabling logic circuit ( 3 ) with the system clock ( 5 ) is synchronous and has a temporal position which corresponds to the position of a clock signal (OCD clock) fed to a data output driver circuit ( 6 ) of the memory component ( 1 ). 2. Integrated semiconductor memory device according to claim 1, characterized, that it is an SDRAM component that can be operated in DDR operation is. 3. Integrated semiconductor memory device according to claim 1 or 2, characterized in that the delay-locked or phase-locked clock generating circuit ( 4 ) is the same circuit that also generates the clock signal for the data output driver circuit ( 6 ) for outputting the data from the memory component ( 1 ). 4. Integrated semiconductor memory component according to one of the preceding claims, characterized in that the signal termination ( 2 ) which can be actively switched on and off terminates signals on a bidirectional signal bus ( 11 ).