DE10128474B4 - Method and circuit arrangement for compensation of runtime differences in the clock synchronization - Google Patents

Abstract

method to compensate for runtime differences in the clock synchronization a plurality of ASICs supplied with a common synchronous clock (T), partly as data sources (Q1-Qn) and partly as data sinks (S) operate, wherein from each data source (Q1-Qn) clocked information via data transmission paths (D1-Dn) with any term to at least one data sink (S) transferred be characterized in that time differences of the Data transmission paths (D1-Dn) determined at the data sink and individually by generating delays be compensated.

Description

The The invention relates to a method and a circuit arrangement for compensation of propagation time differences in the clock synchronization according to the generic terms of patent claim 1 or claim 7.

at the interconnection of multiple data sources that transmit data to a data sink, is it necessary this digitally transmitted Data sent at certain clock frequencies, so too sync that for the a source incoming clocked data meaningful further processing possible is.

It it is well known to create this synchronization by the existence common clock signal for both the timing of the data source as well as the timing of the data sink, So the target of the data is used, which usually causes a adequate synchronization of the data sources and the data sink results.

For this For example, the article by "Hyun Lee; Han Quang Nguyen; Dotter, D.W .: Design self-synchronized clock distribution networks in SoC ASIC using DLL with remote clock feedback. In: Proceedings of the ASIC / SOC Conference. IEEE, 2000, pp. 248-252. "From this document is a circuit arrangement or a method for compensation term differences in ASIC's known in which a return of a Synchronization clock is provided, the transit time differences then determined in the data source and there by appropriate delays be compensated.

Complementing the documents US 6,320,436 B1 and US 6,031,847 A These documents deal with the synchronization of data sinks and data sources, which are not connected via a common synchronous clock, but are individually clocked.

It shows up with that increasing processing speed of electronic components, in particular of ASICs, this hitherto known principle of clock synchronization is not enough and increasingly data transfer problems occur, with these problems show up especially when between the individual electronic components the data to one certain target component are transmitted and different lengths of data transmission paths and thus have time differences.

It is therefore an object of the invention in the method and a circuit arrangement of the type indicated, which make it possible to the occurring time differences in a simple and safe way to compensate.

The The object of the invention is achieved by the features of the independent claims 1 and 7th

Of the Inventor has recognized that at the high clock frequencies of electronic ASICs used today already short differences in length of data transmission lines sufficient to generate clock shifts of the order of magnitude individual clock periods of the signals to be processed. A different length two data transmission lines from two data sources to a common target of about 10 cm already off to a runtime difference of the two signals of approx. 700 ps. At a clock frequency of about 622 MHz corresponds almost half a clock period, so that processing this Both signals by means of a common clock is hardly possible.

to solution this problem strikes the inventor therefore, the time differences of the individual clock signals different data sources either directly to the data sink or in a maturity-equivalent Distance from the data sink to measure and based on the measured Delay difference delays in the field of incoming data to perform individually for each data source, so that the Delay differences at the destination of the data transmission, ie at the data sink, be compensated.

Corresponding According to the basic concept of the invention, the inventor proposes a method to compensate for runtime differences in the clock synchronization multiple data sources operating on synchronous clocks, of each data source clocked information via data transmission paths with any Transfer duration to a data sink be to improve to the effect that the transit time differences the data transmission paths determined at the data sink and individually by generating delays be compensated.

by virtue of the generation of individual delays per data transmission path is it possible this delays to be adjusted so that the data sink itself reaches a much more accurate synchronization being completely independent of the length the data transmission paths from the data sources to the data sink.

Advantageous can this delay be designed so that they takes place at the clock supply itself to the data source. That is, it will a clock shift with respect to the timing of the data source performed.

A Another variant is that the individual delay on the data transmission path takes place between the data source and the data sink. in this connection Is it possible, to leave the clock behavior of the data source unaffected and only to generate a temporal buffer in the data transfer.

According to the invention can Realization of a clock delay a variety of optional selectable and in series delay elements be used. Although this is not a continuous adjustment the delay possible, however, you can the individual delay steps chosen so small be that these be much smaller than the clock width, so that a sufficient Synchronization can be achieved.

Of Another can be used to determine the necessary delay independent Reference clock signal are used, or it is the clock of a specific data source to which the remaining other data sources then sync, used.

Next the inventive method proposes also a circuit arrangement with a plurality of clock-controlled data sources before that over Data transmission paths of any length transmitted clocked information to a data sink, said circuitry is improved so that at least an individually controlled delay element and a phase detector are provided, whereby one by different Run-time-related phase shift of the incoming data signals can be reduced at the data sink.

Advantageous this can be at least one delay element be upstream of the clock input of the data source and / or at least a delay element in the transmission path be arranged between data source and data sink.

According to the invention can continue the phase detector may be a D flip-flop. This is a flip flop, at the data pending at input D with the next positive or negative Accepted clock edge be and until the next positive or negative clock edge at the output Q pending, the one Respond to up / down counter, which in turn is the delay element controls. With the possibility attach the phase detectors directly to the phase sink and to measure the phase shift there, there is also the possibility the phase detectors in a time-equivalent distance in the data transmission path to arrange the data sink. This ensures that the phase differences in the term equivalents intervals be measured to the data sink, until reaching the data sink Don `t change.

A further configuration option is that at least a data transfer from a data source to the data sink is associated with an accompanying clock. This means that so parallel to the data transmission paths transmit a clock signal which experiences the same runtime situations as the transferred ones Data, so that this accompanying act as a reference for possible Clock shifts can be used.

Further advantageous embodiments are defined in the subclaims and the following description of preferred embodiments.

The Figures show in detail:

1 : Representation of the basic principle of the circuit arrangement according to the invention;

2 : First exemplary embodiment of a circuit arrangement according to the invention with main clock supply via a data source to the data sink;

3 : Time behavior of the reference clock signals with associated output signal at the output of the D flip-flop;

4 : Exemplary clock delay with a plurality of identical, successively switchable delay elements;

5 : Another exemplary clock delay with a plurality of successively switchable delay elements with binomially increasing delay time;

5a : Circuitry of an in 5 used 2: 1 multiplexer;

6 : Second embodiment of a circuit arrangement according to the invention with separate main clock supply to the data sink;

7 : Time response of a reference clock signal RT1 to the clock signal T and the corresponding output signal at the output of the D flip-flop.

The 1 shows in a highly schematic way the problem of synchronization of data transmission between the data sources Q1 to Qn and a data sink S. Both the data sink S, and the data sources Q1 to Qn are supplied by a common clock T. The data sources transmit via the data transmission paths D1 to Dn - which may each consist of a single data transmission line or a bundle of m data transmission lines - their data to the data sink S, parallel to the data transmission paths D1 to Dn reference clocks RT1 to RTn are transmitted, which in principle correspond to the timing information of the data sources.

There the data transmission paths D1 to Dn between the data sources Q1 to Qn and the data sink S different lengths may have Here, due to the differences in transit time phase differences between the reference clocks RT1 to RTn and the common clock T. additionally It should be noted here that alone the transfer of the common clock T over a line of finite length already can lead to a clock shift. At the destination of data transmission, the data sink S, is now determined which runtime difference, more precisely which phase shift, between the common clock T and the individual reference clocks RT1 to RTn with respect to respective data source Q1 to Qn is present. On the dotted shown Connections are then individually for each data source Q1 to Qn the information about the phase shift between the clock T and the reference clock RT1 to RTn upstream of one of the data sources Q1 to Qn or downstream delay element TV1 to TVn communicated, which according to the information received a delay in an order of magnitude causes all incoming data from the data sources with respect to their clock without phase shift reach the data sink S

is the delay element TV1 to TVn downstream of the respective data source Q1 to Qn, However, it is necessary in addition to the clock signal at the same time the data signals of the data transmission lines Delay D1 to D2 accordingly.

Complementary nor to point out that it to carry out the method according to the invention is not absolutely necessary that the data sink S directly to the general clock T is connected. It is enough, if any, of is selected from the data source clock and the remaining Data sources are synchronized to these, with the data sink also operated with this clock.

A concrete example of this method according to the invention described above and of the basic circuit arrangement is shown in FIG 2 shown. On the right side of the dashed vertical line are the circuits of a target ASIC S, while on the left side the source ASICs Q1 to Qn are arranged, which send data to the target ASIC S via n-times data transmission paths D1 to Dn transfer. Parallel to the data transmission paths, the reference clocks RT1 to RTn are routed from the source ASICs Q1 to Qn via clock lines from the assigned source ASICs to the destination ASIC. In addition, from the first source ASIC Q1, a clock line T1 leads to the destination ASIC S.

in the Target ASICs S are n-1 D flip-flops FF2 to FFn provided on the Clock input on the one hand, the reference clock RT1 of the first source ASICs Q1 supplied is at the D input of the D flip-flops FF2 to FFn the respective Reference clock RT2 to RTn of the associated source ASICs Q2 to Qn is applied. Depending on the timing of the reference clock RT1 to the reference clocks RT2 to RTn are at the outputs FF2A to FFnA of the D flip-flops FF2 to FFn in the case of the override of the reference clock RT1 a logic "0 signal" and in the case of lag a logical "1 signal" occur. These Information is now for that used to drive TA2 at the source ASICs Q2 to Qn to TAn opposite to delay the working clock TA1 of the source ASICs Q1 individually or the delay to reduce.

Around apply this influence in both directions from the basic clock to be able to has the first ASIC Q1 over a fixed clock delay TV1, which is advantageously set to an approximately average accepted clock delay is. The clock delay devices TV2 to TVn, which precedes the clock input of the source ASICs Q2 to Qn or implemented in the ASICs are used by up / down counters in Dependence of applied information of the associated D flip-flops controlled.

An example of the clock behavior of the individual reference clocks RT1 to RTn and their effects on the outputs FFxA of the associated D flip-flops is in the 3 shown.

In addition, it should be pointed out that the frequency of the clock T due to clock conversions in the ASICs Q1 to Qn may be different from the reference clocks RT1 to RTn, wherein the frequency of the clock T1 is not equal to the frequency of the reference clocks RT1 to RTn. It is essential, however, that the reference clocks RT1 to RTn have the same frequency. By this configuration, it is possible, for example, to make a clock synchronization such that this not only bit-wise, but for example byte-way, the means in eighth steps, or even comprising a pulse frame with several bytes takes place.

The 4 shows an embodiment of a clock delay device TV, in which by the alternately back to another switching several delay elements VE1 to VE8 the respectively desired delay time is set. The delay elements VE1 to VE8 are connected in chain form in the inputs of a multiplexer MUX and each cause a certain delay time. Furthermore, the multiplexer MUX is controlled by the up / down counter Z, wherein depending on the concern of the address none of the delay elements are led to all successively connected delay elements to the output of the multiplexer and deliver the power stroke TA of the respective source ASICs. The up / down counter Z is controlled by the timing clock ZT and the control signal SS, which comes from D flip-flops from the target ASICs S.

On experiences this way the input clock TE, depending on the address of the up / down counter Z, a different one delay until the output of the working cycle TA and thus also until the output of the Reference clock RT.

in the Operation is thus in the up / down counter Z of Timing ZT supplied and depending on the applied control signal, the counter is set to count up / down. Is the control signal logic "0", which is a lag of the respective reference clock RT2 to RTn with respect to the reference clock RT1, so will the counter causes it to count down so that the Decrease delay time becomes. If the control signal is logical "1" corresponds this a lead and the counter is caused to count up and thus a greater delay time set. In the steady state, thus, the reference clocks RT2 to RTn by a maximum of +/- the Delay Time a delay element V opposite deviate from the reference clock RT1.

Since the data signals are generated in the same way as the reference clocks, this also ensures that the data signals D1 to Dn of all source ASICs Q1 to Qn can differ from each other by only a maximum of +/- the delay time of one delay element. This ensures that the data signals of the n source ASICs Q1 to Qn in the subsequent processing in the target ASIC S, for example, the flip-flops FFD1 to FFDn shown here of the target ASICs can be taken over correctly by means of the clock T1. Will, as in the 2 illustrated, the source ASIC Q1 preceded by a fixed delay of 8V, so a runtime compensation of the reference clocks RT2 to RTn and the data signals D2 to Dn between -8V and + 7V can be made. If a delay V corresponds, for example, to 0.2 clock periods of the clock T, then run-time differences of -1.6 to +1.4 clock periods can be compensated in the system.

Become as reference clocks RT1 to RTn byte clocks or pulse frame clocks used, can through the process runtime differences of half a byte, according to +/- 4 Clock periods or half a pulse frame balanced become. For this the must Number of delays V of course be adapted accordingly.

Another variant of a clock delay device is in 5 shown.

she consists of a chain of 2: 1 multiplexers and delay elements, their delay value increases binomially so that, for example the first delay element VE1 a delay one, the second delay element VE2 of two, the third delay element VE3 of four and the delay element VE4 a delay time of 8 units.

Corresponding the outgoing on the up / down counter Z out logical level on the address lines A0 to A3, then results by a corresponding interaction of the individual delay elements a total delay time for the outgoing clock RT.

The structure of the 2: 1 multiplexer is exemplary in the 5a shown. Alternatively, the 2: 1 multiplexers can also be realized by AND / OR gates.

Another variant of an embodiment of a circuit arrangement according to the invention is in the 6 shown. Compared to the first embodiment - according to 2 The target ASIC S is immediately supplied with a clock T, whereby the supply of the clock T1 from the source ASIC Q1 to the target ASIC S can be dispensed with. In this case, an additional delay compensation is provided between the clock T and the reference clock RT1. For this purpose, in addition to the fixed delay TV1 by 8V, the source ASIC Q1 is additionally preceded by a variable delay of 0 to 7 V and correspondingly integrated in the ASIC.

Furthermore, the target ASIC S is provided with a further D flip-flop FF1, which compares the temporal position of the reference clock RT1 with respect to the clock T. Depending on the timing of the reference clock RT1 relative to the clock T is at the output FF1A - as in the 7 shown - in the case of the lead of the reference clock RT1 generates a logic "0 signal" and in the case of lagging a logical "1 signal". Analogous to the in 2 described method is also achieved in this case that the reference clock RT1 deviates by a maximum of +/- a delay time V from the positive clock edge of the clock T. Since the reference clocks RT2 to RTn are aligned in time to the reference clock RT1, it is ensured that the data signals of the n source ASICs Q1 to Qn in the target ASIC S or - as shown here - in the flip-flops FFD1 to FFDn by means of the clock T correct can be taken over.

If the clock delay devices TVx are integrated in the source ASICs Qx, then it can be achieved by a simple switchover that the source ASIC Q1 can be constructed identically to the source ASICs Q2 to Qn. According to the first embodiment of the 2 For example, in the source ASIC Q1, a fixed delay time of, for example, 8V can be realized by switching the most significant address line of the up / down counter to logic "1" and the three low order address lines to logic "0" in the source ASIC Q1. be placed.

Accordingly, for the second illustrated embodiment of the 6 the source ASIC Q1 a fixed delay time of 8V in addition to a variable delay time of 0 to 7V can be realized by the high order address line of the up / down counter is set to logic "1" in the ASIC Q1 by means of a switch and the three least significant Address lines are controlled by the counter.

The 7 shows clock situations at the inputs of the D flip-flop FF1 in the 6 , wherein the incoming clock T has a higher frequency than the incoming reference clock RT1 and the period of the reference clock RT1 an integer multiple of the period of the clock T has.

All in all Thus, the invention describes a circuit arrangement and a method to compensate for runtime differences in the clock synchronization multiple data sources working with synchronous clocks, of each data source clocked information via data transmission paths with any Transfer duration to a data sink be, whereby by measurement of phase differences respectively Runtime differences and subsequent compensation of the phase differences by interposing different time delays these are compensated.

Ax

address line

D

entrance On the D flip flop

dx

Data transmission paths

FFDx

D flip-flop for data processing

FFx

D flip-flop / phase detector

FFxA

output of the D flip-flop

MUX

multiplexer

muxx

multiplexer

Q

output on the D flip flop

Qx

Data Source

RTx

reference clock

S

data sink

SS

control signal (0/1)

T

clock

TA

power stroke

TE

input clock

sary

firm clock delay

TVx

Takverzögerung / time delay

VEx

delay element

V

Delay (1 Unit of time)

ZT

timing

zx

Up / down counter

Claims (13)

A method of compensating for propagation delays in the clock synchronization of a plurality of common synchronous clock (T) supplied ASICs operating in part as data sources (Q1-Qn) and partly as data sinks (S), each of which data source (Q1-Qn) is clocked information be transmitted via data transmission paths (D1-Dn) with any duration to at least one data sink (S), characterized in that transit time differences of the data transmission paths (D1-Dn) are determined at the data sink and compensated individually by generating delays. Method according to the preceding Claim 1, characterized in that at least one individual delay at a clock supply (T) in front of the data source (Q1-Qn). Method according to one of the preceding claims 1 to 2, characterized in that at least one individual delay on the data transmission path (D1-Dn) to the data sink (S) takes place. Method according to one of the preceding claims 1 to 3, characterized in that for delay a plurality of optional dial-up and series connected delay elements (VE1-VEn) become. Method according to one of the preceding claims 1 to 4, characterized in that the Determining the necessary delay an independent clock signal (T) is used. Method according to one of the preceding claims 1 to 4, characterized in that for determining the necessary delay the reference clock (RT1) of a particular data source (Q1) is used becomes. Circuit arrangement for compensation of transit time differences in the clock synchronization with several with a common synchronous clock (T) serviced ASICs, partly as data sources (Q1-Qn) and partly as data sinks (S) act, being over Data transmission paths (D1-Dn) of any length timed information from at least one data source (Q1-Qn) transmitted at least one data sink (S) be characterized in that at least one individually regulated delay element (TV1-TVn) and a phase detector (FF1-FFn) at the at least one data sink (S) is provided, whereby a due to different maturities phase shift of incoming data signals at the at least one data sink reduced can be. Circuit arrangement according to the preceding claim 7, characterized in that at least a delay element (TV1-TVn) upstream of the clock input of the data source (Q1-Qn). Circuit arrangement according to one of the preceding claims 7 to 8, characterized in that at least one delay element (TV1-TVn) in the transmission path between data source (Q1-Qn) and data sink (S) is arranged. Circuit arrangement according to one of the preceding claims 7 to 9, characterized in that for determining the phase shift a D flip-flop (FF1-FFn) is provided which receives a reference clock signal (RT1-RTn) and an up / down counter (Z) controls. Circuit arrangement according to one of the preceding claims 7 to 10, characterized in that the phase detectors (FF1-FFn) in a maturity-equivalent Distance to the data sink (S) are arranged. Circuit arrangement according to one of the preceding claims 7 to 11, characterized in that at least one data transmission path (D1-Dn) a data source (Q1-Qn) an accompanying clock (RT1-RTn) is assigned to the data sink. Circuit arrangement according to one of the preceding claims 7 to 12, characterized in that at least one data transmission path (D1-Dn) consists of a plurality of parallel data transmission lines.