DE10128474A1 - Circuit arrangement for compensation of time of flight differences in clock synchronized data transfer, where data travels over varying path lengths and a time delay is determined for each data source based on a phase detector - Google Patents

Abstract

Method for compensation of time of flight differences in which the data sources (Q1-Qn) are clock synchronized with a synchronization cycle (T) so that data can be transferred from them over data transfer paths (D1-Dn) that have different time of flights, to a data sink (S). To balance out the time of flight differences (time for data transfer), the differences are determined and a time delay applied to each transfer path so that data is synchronized. An Independent claim is made for a circuit arrangement with a number of clock controlled data sources with different length data transfer paths linking them to a data sink. Each data path has an associated time delay member (TV1-TVn) and a phase detector.

Description

The invention relates to a circuit arrangement and a Process for the compensation of runtime differences at the Clock synchronization of several people working with synchronous clocks Data sources, being clocked by each data source Information about data transmission paths with any runtime a data sink is transmitted.

When interconnecting multiple data sources, the data on transmit a data sink, it is necessary to digitally transmitted data with certain clock frequencies be sent to synchronize so that for the one Source arriving clocked data a sensible Further processing is possible.

It is well known to thereby achieve this synchronization generate a common clock signal for both the Clocking the data source as well as clocking the data sink, that is, the destination of the data, which is what usually adequate data source synchronization and the data sink results.

However, it turns out that with increasing Processing speed of the electronic components, in particular of ASICs, this previously known principle of Clock synchronization is not sufficient and problems with increasing Data transmission occurs, addressing these problems especially show when between each electronic components transfer the data to a specific target component are transmitted and different lengths of data transmission paths and thus have runtime differences.

It is therefore an object of the invention a method and Represent circuit arrangement that allow the occurring runtime differences on simple and safe Way to compensate.

The object of the invention is characterized by the features of independent claims solved.

The inventor recognized that the high clock frequencies of electronic components, especially of ASICs, already short differences in length of Data transmission lines are sufficient to generate clock shifts, the order of magnitude of individual clock periods processed signals. A different length of two Data transmission lines from two data sources to one a common target of approx. 10 cm is sufficient to achieve one Runtime difference between the two signals of approx. 700 ps cause. This corresponds to a clock frequency of approx. 622 MHz almost half a clock period, so processing these two signals using a common clock barely is possible.

To solve this problem, the inventor therefore proposes the runtime differences of the individual clock signals different data sources either directly at the data sink or in a distance equivalent to the runtime from the data sink measure and based on the measured transit time difference Delays in the area of incoming data individually for perform any data source so the runtime differences at the destination of the data transmission, i.e. at the data sink, be compensated.

According to the basic idea of the invention, the Inventor proposed a method for compensation of Runtime differences in the clock synchronization of several with Synchronous clocks of working data sources, whereby from each Data source with clocked information about data transmission paths can be transferred to a data sink for any duration, to improve in that the runtime differences of Data transmission paths determined at the data sink and can be compensated individually by creating delays.

Due to the generation of individual delays each Data transmission path, it is possible to avoid these delays set that at the data sink itself an essential more accurate synchronization is achieved which is completely independent on the length of the data transmission paths from the data sources to the data sink is.

This delay can advantageously be designed so that it takes place at the clock feed itself to the data source. The that is, there will be a clock shift in timing the data source.

Another variant is that the individual Delay in the data transmission path between the Data source and the data sink takes place. Here it is possible to leave the clock behavior of the data source unaffected and only a time buffer in the data transmission produce.

Examples of possible data sinks and / or data sources are so-called ASICs.

According to the invention, a Clock delay a variety of selectable and in series switched delay elements can be used. hereby will not be a continuous adjustment of the delay possible, but the individual delay steps can be so be chosen small that they are much smaller than that Clock width fail, so that a sufficient Synchronization can be achieved.

It can also be used to determine the necessary delay an independent reference clock signal is used, or it becomes the clock of a particular data source that is referenced then synchronize the remaining other data sources, used.

In addition to the method according to the invention, the inventor proposes also a circuit arrangement with several clock-controlled Data sources that are arbitrary via data transmission paths Transmit clocked information to a data sink, this circuit arrangement being improved in that that at least one individually controlled delay element and a phase detector are provided, whereby a through different running times due to phase shift incoming data signals at the data sink can be reduced can.

The at least one delay element can be advantageous Clock input of the data source and / or at least one delay element in the transmission path between Data source and data sink are arranged.

According to the invention, the phase detector can also be a D- Flip flop. This is a flip-flop where the one at the input D upcoming data with the next positive or negative Clock edge are taken over and until the next positive or there is a negative clock edge at output Q, the one Up / down counter responds, which in turn that Delay element controls. With the possibility of Attach phase detectors directly to the phase sink and the It is also possible to measure phase shift there the phase detectors at a time-equivalent distance in Arrange data transmission path to the data sink. hereby it is ensured that the phase differences in the equivalent distances to the data sink measured will not change until the data sink is reached.

Another design option is that at least one data transfer from a data source to A companion measure is assigned to the data sink. This means that that is, a clock signal in parallel with the data transmission paths is transmitted, which has the same runtime situations learns how the transmitted data, so that accompanying clock can be used as a reference for possible clock shifts can.

Further advantageous embodiments are shown in the Subclaims and the following description are more preferred Embodiments can be seen.

The figures show in detail:

Fig. 1 representation of the basic principle of the circuit arrangement according to the invention;

Fig. 2 First embodiment of a circuit arrangement according to the invention with the main clock supply through a data source to the data sink;

FIG. 3 shows timing of the reference clock signals with the corresponding output signal at the output of the D flip-flop;

Fig. 4 exemplary clock delay with a plurality of identical delay elements that can be connected in series;

FIG. 5 shows another exemplary Taktverzögerer with a plurality of successive delay elements with switchable binomisch increasing delay time;

FIG. 5a is a circuit arrangement in Figure 5 used 2: 1-multiplexer;.

Fig. 6 Second embodiment of a circuit arrangement according to the invention with a separate main clock supply to the data sink;

Fig. 7 time behavior of a reference clock signal RT1 to the clock signal T and associated output signal at the output of the D flip-flop.

Fig. 1 shows in a highly schematic manner, the problem of synchronization of data transmission between the data sources Q1 to Qn and a data sink S. Both supplies the data sink p as well as the data sources are Q1 to Qn by a common clock T. The data sources transmit their data to the data sink S via the data transmission paths D1 to Dn - which can each consist of a single data transmission line or a bundle of m data transmission lines - whereby reference clocks RT1 to RTn, which are basically transmitted, are transmitted parallel to the data transmission paths D1 to Dn correspond to the clock information of the data sources.

Since the data transmission paths D1 to Dn between the Data sources Q1 to Qn and the data sink S different Lengths can vary here due to the existing Running time differences between the phases Reference clocks RT1 to RTn and the common clock T result. In addition, it should be noted here that even the Transmission of the common clock T over a finite line Length can already lead to a clock shift. At the Finish the data transmission, the data sink S. is now determined what runtime difference, more precisely which Phase shift, between the common clock T and the individual reference clocks RT1 to RTn with respect to the respective Data source Q1 to Qn is present. On the dotted line Connections are then made individually for each data source Q1 to Qn the information about the phase shift between the clock T and the reference clock RT1 to RTn to one of the Data source Q1 to Qn upstream or downstream Delay element TV1 to TVn communicated, which corresponds to the received information a delay in a Order of magnitude causes that all arriving from the data sources Data regarding their clock without phase shift Reach data sink S.

Is the delay element TV1 to TVn of the respective Data source Q1 to Qn downstream, however, it is In addition to the clock signal, the data signals are also necessary at the same time of the data transmission lines D1 to D2 accordingly delay.

In addition, it should be pointed out that it is for Implementation of the method according to the invention is not essential it is necessary that the data sink S directly on the general clock T is connected. It is also sufficient if any one of the clock originating from the data sources is selected and the remaining data sources are synchronized to them, the data sink also operated at this clock becomes.

A concrete example of this inventive method described above and the basic circuit arrangement is shown in FIG. 2. The circuit of a target ASIC S is located on the right side of the dashed vertical line, while the source ASICs Q1 to Qn are arranged on the left side, which transmit data to the target ASIC S via n-fold data transmission paths D1 to Dn transfer. In parallel to the data transmission paths, the reference clocks RT1 to RTn are routed from the assigned source ASICs to the target ASIC by the source ASICs Q1 to Qn via clock lines. In addition, a clock line T1 leads from the first source ASIC Q1 to the target ASIC S.

In the target ASIC S, n-1 D flip-flops FF2 to FFn are provided, those at the clock input on the one hand the reference clock RT1 of the first source ASICs Q1 is supplied, with the D- at the D input Flip-flops FF2 to FFn the respective reference clock RT2 to RTn of the assigned source ASICs Q2 to Qn. Depending on temporal position of the reference clock RT1 to the reference clocks RT2 to RTn are at the outputs FF2A to FFnA of the D flip-flops FF2 to FFn in the case of advance of the reference clock RT1 logical "0 signal" and a logical in the case of lagging "1 signal" occur. This information is now used for this used to source the source ASICs Q2 through Qn Work cycles TA2 to TAn compared to work cycle TA1 of the source ASIC Q1 individually delay or delay reduce.

To this influence in both directions from the basic clock the first ASIC Q1 has a Fixed clock delay TV1, which is advantageous an approximately average assumed clock delay is set is. The clock delay devices TV2 to TVn that the Clock input of the source ASICs Q2 to Qn upstream or in the ASICs are implemented, are / Down counters depending on the information available of the assigned D flip-flops controlled.

An example of the clock behavior of the individual reference clocks RT1 to RTn and their effects on the outputs FFxA of the associated D flip-flops is shown in FIG. 3.

In addition, it should be noted that the frequency of the Clock T due to clock conversions in ASICs Q1 to Qn can be different from the reference clocks RT1 to RTn, the frequency of the clock T1 also being different from the frequency the reference clock is RT1 to RTn. However, it is essential that the reference clocks RT1 to RTn have the same frequency. This configuration makes it possible, for example, to To establish clock synchronization in such a way that it not only Bit-wise, but for example byte-wise, i.e. in eighth steps, or even a pulse frame with several Comprising bytes.

FIG. 4 shows an exemplary embodiment of a clock delay device TV, in which the desired delay time is set by optionally connecting a plurality of delay elements VE1 to VE8 in series. The delay elements VE1 to VE8 are connected upstream in the form of chains in the inputs of a multiplexer MUX and each cause a specific delay time. Furthermore, the multiplexer MUX is controlled by the up / down counter Z, wherein depending on the address, none of the delay elements up to all the delay elements connected in series are routed to the output of the multiplexer and emit the working clock TA of the respective source ASIC. The up / down counter Z is controlled by the timing ZT and the control signal SS, which comes from D flip-flops from the target ASICs S.

In this way, the input clock TE experiences depending on the address of the up / down counter Z, a different one Delay until the output of the work cycle TA and thus also until the output of the reference clock RT.

In operation, the up / down counter Z is the Time clock ZT is supplied and depending on the control signal present the counter is set to count up / down. Is this Control signal logic "0", which is a lag of the respective Reference clock RT2 to RTn compared to the reference clock RT1 corresponds, the counter is caused to count down, so that the delay time will decrease. Is this Control signal logic "1", this corresponds to an advance and the Counter is caused to count up and thus a greater delay time set. In the steady The reference clocks RT2 to RTn are thus at maximum +/- the delay time of a delay element V differ from the reference clock RT1.

Since the data signals are generated in the same way as the reference clocks, this also ensures that the data signals D1 to Dn of all source ASICs Q1 to Qn can also differ from one another by likewise only a maximum of +/- the delay time of a delay element. This ensures that the data signals of the n source ASICs Q1 to Qn in the subsequent processing in the target ASIC S, for example the flip-flops FFD1 to FFDn of the target ASIC shown here, can be correctly adopted by means of the clock T1. If, as shown in FIG. 2, a fixed delay of 8 V is connected upstream of the source ASIC Q1, the runtime compensation of the reference clocks RT2 to RTn and the data signals D2 to Dn between -8 V and +7 V can be carried out. If a delay V corresponds to, for example, 0.2 clock periods of the clock T, runtime differences of -1.6 to +1.4 clock periods can be compensated for in the system.

Are byte clocks as reference clocks RT1 to RTn or pulse frame clocks can be used by the method Runtime differences of half a byte, corresponding to +/- 4 Clock periods or half a pulse frame be balanced. For this, the number of delays V can of course be adjusted accordingly.

Another variant of a clock delay device is shown in FIG. 5.

It consists of a chain connection of 2: 1 multiplexers and delay elements whose delay value is binomial increases so that, for example, the first delay element VE1 a delay of one, the second delay element VE2 of two, the third delay element VE3 of four and the delay element VE4 has a delay time of 8 Units.

According to the up / down counter Z outgoing logic level on the address lines A0 to A3, results then through a corresponding interaction of the individual delay elements a total delay time for the outgoing clock RT.

The structure of the 2: 1 multiplexer is shown by way of example in FIG. 5a. Alternatively, the 2: 1 multiplexers can also be implemented using AND / OR gates.

Another variant of an exemplary embodiment of a circuit arrangement according to the invention is shown in FIG. 6. Compared to the first exemplary embodiment - according to FIG. 2 - a clock T is fed directly to the target ASIC S, whereby the supply of the clock T1 from the source ASTC Q1 to the target ASIC S can be omitted. In this case, an additional runtime compensation between clock T and reference clock RT1 is provided. For this purpose, the source ASIC Q1 is preceded by a fixed delay TV1 by 8 V and a variable delay by 0 to 7 V and integrated accordingly in the ASIC.

Furthermore, the target ASIC S is provided with a further D flip-flop FF1 which compares the timing of the reference clock RT1 with respect to the clock T. Depending on the temporal position of the reference clock RT1 with respect to the clock T, a logical "0 signal" is output at the FFIA - as shown in FIG. 7 - if the reference clock RT1 is advanced and a logical "1 signal" if it lags . generated. Analogously to the method described in FIG. 2, it is also achieved in this case that the reference clock RT1 deviates from the positive clock edge of the clock T by a maximum of +/- one delay time V. Since the reference clocks RT2 to RTn are aligned in time with the reference clock RT1, it is ensured that the data signals of the n source ASICs Q1 to Qn in the target ASIC S or - as shown here - in the flip-flops FFD1 to FFDn are correct by means of the clock T. can be taken over.

If the clock delay devices TVx are integrated in the source ASICs Qx, it can be achieved by a simple switchover that the source ASIC Q1 can be constructed identically to the source ASICs Q2 to Qn. According to the first exemplary embodiment of FIG. 2, a fixed delay time of, for example, 8 V can be realized in the source ASIC Q1, in that the most significant address line of the up / down counter is constantly set to logic "1" and the three low-order address lines are set to logic "0".

Correspondingly, a fixed delay time of 8 V in addition to a variable delay time of 0 to 7 V can be realized for the source ASIC Q1 shown in FIG. 6, in that the most significant address line of the up / down link in the ASIC Q1 by means of a switch. Counter is constantly set to logic "1" and the three low-order address lines are controlled by the counter.

FIG. 7 shows clock situations at the inputs of the D flip-flop FF1 in FIG. 6, the incoming clock T having a higher frequency than the incoming reference clock RT1 and the period of the reference clock RT1 having an integral multiple of the period of the clock T. ,

It is understood that the above features of Invention not only in the specified combination, but also in other combinations or alone can be used without departing from the scope of the invention.

Overall, the invention describes one Circuit arrangement and a method for compensation of Runtime differences in the clock synchronization of several with Synchronous clocks working data sources, being from each data source clocked information about data transmission paths with any runtime are transferred to a data sink, whereby by measuring phase differences respectively Runtime differences and subsequent compensation of the Phase differences by interposing different sizes Time delays can be compensated for.

Claims (14)

1. A method for compensating for delay differences in the clock synchronization of a plurality of data sources (Q1-Qn) working with synchronous clocks (T), information from data sources (Q1-Qn) clocked by data sources (D1-Dn) with any delay to a data sink (S ) are transmitted, characterized in that runtime differences of the data transmission paths (D1-Dn) at the data sink are determined and individually compensated for by generating delays. 2. The method according to the preceding claim 1, characterized, that at least one individual delay on one Clock feed (T) takes place before the data source (Q1-Qn), whereby preferably the entire data source (Q) in their Clock behavior is adjusted. 3. The method according to any one of the preceding claims 1 up to 2, characterized, that at least one individual delay on the Data transmission path (D1-Dn) to the data sink (S) takes place. 4. The method according to any one of the preceding claims 1 to 3, characterized, that as data sink (S) and / or data source (Q1-Qn) ASICs be used. 5. The method according to any one of the preceding claims 1 to 4, characterized, that to delay a variety of selectable and delay elements connected in series (VE1-VEn) be used. 6. The method according to any one of the preceding claims 1 until 5, characterized, that to determine the necessary delay independent clock signal (T) is used. 7. The method according to any one of the preceding claims 1 until 5, characterized, that to determine the necessary delay of Reference clock (RT1) of a specific data source (Q1) is used. 8. Circuit arrangement with several clock-controlled Data sources (Q1-Qn) via data transmission paths (D1-Dn) information of any length clocked to a data sink (S) transfer, characterized, that at least one individually controlled delay element (TV1-TVn) and a phase detector (FF1-FFn) are provided, whereby a due to different terms Phase shift of the incoming data signals at the Data sink can be reduced. 9. Circuit arrangement according to the preceding claim 8th, characterized, that at least one delay element (TV1-TVn) the Clock input of the data source (Q1-Qn) is connected upstream. 10. Circuit arrangement according to one of the preceding Claims 8 to 9, characterized, that at least one delay element (TV1-TVn) in the Transmission path between data source (Q1-Qn) and data sink (S) is arranged. 11. Circuit arrangement according to one of the preceding Claims 8 to 10, characterized, that to determine the phase shift a D flip-flop (FF1-FFn) is provided that a reference clock signal (RT1-RTn) receives and controls an up / down counter (Z). 12. Circuit arrangement according to one of the preceding Claims 8 to 11, characterized, that the phase detectors (FF1-FFn) in one equivalent distance to the data sink (S) are arranged. 13. Circuit arrangement according to one of the preceding Claims 8 to 12, characterized, that at least one data transmission path (D1-Dn) one Data source (Q1-Qn) for data sink an accompanying clock (RT1-RTn) assigned. 14. Circuit arrangement according to one of the preceding Claims 8 to 13, characterized, that at least one data transmission path (D1-Dn) from one There is a large number of parallel data transmission lines.