DE10051467A1 - Semiconducting chip housing has wiring plane with at least one resistor and/or capacitor in form of board-on-chip ball grid array with wiring structure of one or more layers - Google Patents

Semiconducting chip housing has wiring plane with at least one resistor and/or capacitor in form of board-on-chip ball grid array with wiring structure of one or more layers

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Publication number
DE10051467A1
DE10051467A1 DE10051467A DE10051467A DE10051467A1 DE 10051467 A1 DE10051467 A1 DE 10051467A1 DE 10051467 A DE10051467 A DE 10051467A DE 10051467 A DE10051467 A DE 10051467A DE 10051467 A1 DE10051467 A1 DE 10051467A1
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Germany
Prior art keywords
semiconductor chip
capacitor
resistor
chip
wiring
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE10051467A
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German (de)
Inventor
Simon Muff
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Infineon Technologies AG
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Infineon Technologies AG
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Priority to DE10051467A priority Critical patent/DE10051467A1/en
Publication of DE10051467A1 publication Critical patent/DE10051467A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/647—Resistive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Abstract

The semiconducting chip housing has a wiring plane (2) with at least one resistor (R) and/or capacitor (C). The wiring plane is in the form of a board-on-chip ball grid array and contains a wiring structure of one or more layers. At least one capacitor in the wiring plane decouples an applied voltage.

Description

Die vorliegende Erfindung betrifft ein Halbleiterchipgehäuse, insbesondere in einem Chipmodul, speziell in einem SO-DIMM.The present invention relates to a semiconductor chip package, especially in a chip module, especially in an SO-DIMM.

Bei Speichermodulen zur Verwendung in unabhängig vom Netz­ strom betriebenen Geräten (so genannte mobile applications), insbesondere bei so genannten SO-DIMMs (Small-Outline Dual- Inline Memory Modules), benötigen die aktiven Einzelkomponen­ ten des Speichers aufgrund der steigenden Speicherdichte bzw. Speichergröße zunehmend mehr Platz. Dabei müssen zur Gewähr­ leistung der elektrischen Funktion, z. B. zur Entkopplung der Spannungsversorgung und zur Einrichtung der elektrischen Be­ triebsanschlüsse, je nach Busarchitektur, Kondensatoren und Widerstände als passive Komponenten auf der Trägerplatine (SO-DIMM-PCB) aufgebracht werden. Das führt zu Problemen bei der Platzierung dieser Komponenten auf der Trägerplatine auf­ grund des beschränkten Platzangebots.For memory modules for use in independent of the network current-operated devices (so-called mobile applications), especially with so-called SO-DIMMs (Small-Outline Dual- Inline Memory Modules), require the active individual components due to the increasing storage density or Memory size increasingly more space. Doing so must guarantee performance of the electrical function, e.g. B. for decoupling the Power supply and for setting up the electrical loading drive connections, depending on the bus architecture, capacitors and Resistors as passive components on the carrier board (SO-DIMM-PCB) can be applied. This leads to problems the placement of these components on the carrier board due to the limited space.

Durch eine Vergrößerung der Platinen bis hin zu den Obergren­ zen der Spezifikation bzw. der Vorgaben seitens der Kunden und durch die Begrenzung der Anzahl der auf einer Trägerpla­ tine aufzubringenden Komponenten lässt sich dieses Problem nur teilweise beheben. Es wird in jedem Fall die Speichergrö­ ße limitiert.By enlarging the boards up to the upper limit customer specifications and by limiting the number of people on a carrier Components to be applied to this problem only partially fix it. In any case, the memory size limited edition.

Aufgabe der vorliegenden Erfindung ist es, anzugeben, wie ei­ ne größere Speicherdichte bei Chipmodulen, insbesondere bei SO-DIMMs, erreicht werden kann.The object of the present invention is to specify how egg ne greater storage density for chip modules, especially for SO-DIMMs can be achieved.

Diese Aufgabe wird mit dem Halbleiterchipgehäuse mit den Merkmalen des Anspruches 1 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen. This task is accomplished with the semiconductor chip package Features of claim 1 solved. Refinements result themselves from the dependent claims.  

Das Trägersubstrat des Gehäuses eines Halbleiterchips wird gleichzeitig als Träger einer Umverdrahtung benutzt, wodurch die Anschlüsse des Halbleiterchips mit externen Anschlüssen des Gehäuses verbunden werden. Die dafür vorgesehene Verdrah­ tungsstruktur aus elektrischen Leiterbahnen auf dem Träger­ substrat des Gehäuses, die eine oder mehrere Ebenen von Lei­ tern umfassen kann, wird im folgenden als Umverdrahtungsebene bezeichnet. Diese Umverdrahtungsebene besitzt bei dem erfin­ dungsgemäßen Halbleiterchipgehäuse mindestens einen inte­ grierten Widerstand und/oder Kondensator. Bei bevorzugten Ausführungsformen sind darüber hinaus keine separaten passi­ ven Komponenten mehr erforderlich. Der Halbleiterchip ist in einer an sich bekannten Weise auf dem Trägersubstrat befes­ tigt. Elektrisch leitende Verbindungen zwischen den An­ schlusskontakten (bondpads) des Halbleiterchips und der Ver­ drahtungsstruktur der Umverdrahtungsebene sind beispielsweise durch Bonddrähte (bond wires) oder Beamleads (Tape Automated Bonding Technology) gebildet.The carrier substrate of the housing of a semiconductor chip is used simultaneously as a carrier of rewiring, whereby the connections of the semiconductor chip with external connections of the housing. The intended wiring tion structure of electrical conductor tracks on the carrier substrate of the case that has one or more levels of lei tern may be referred to below as the rewiring level designated. This rewiring level has the invent semiconductor chip package according to the invention at least one inte ized resistor and / or capacitor. With preferred Embodiments are also not separate passi ven components more required. The semiconductor chip is in in a manner known per se on the carrier substrate Untitled. Electrically conductive connections between the An final contacts (bond pads) of the semiconductor chip and the ver Wiring structure of the rewiring level are for example by means of bond wires or beam leads (tape automated Bonding Technology).

Ein Widerstand ist durch Einbringen eines als ohmscher Wider­ stand wirkenden Werkstoffs in entsprechender Dimensionierung in der Leiterbahn ausgebildet. Ein solcher Widerstand wird vorzugsweise mit dem an sich bekannten Verfahren des SIMOV (SIemens Mehrfach Oberflächen Verdrahtungs Technologie) her­ gestellt, das auch bei der Herstellung von Leiterbahnplatinen und dergleichen angewendet wird. Kondensatoren können durch einander gegenüberliegend angeordnete Leiterflächen gebildet sein, die die Kondensatorplatten bilden und vorzugsweise in verschiedenen Leiterebenen der Umverdrahtungsebene angeordnet sind.Resistance is by introducing one as an ohmic resistance effective material in appropriate dimensions trained in the trace. Such resistance will preferably with the known SIMOV method (SIemens multiple surface wiring technology) posed, also in the production of printed circuit boards and the like is applied. Capacitors can pass through oppositely arranged conductor surfaces are formed be, which form the capacitor plates and preferably in different conductor levels of the rewiring level arranged are.

Es folgt eine genauere Beschreibung eines Beispiels des er­ findungsgemäßen Halbleiterchipgehäuses anhand der Fig. 1 und 2.The following is a more detailed description of an example of the semiconductor chip package according to the invention with reference to FIGS. 1 and 2.

Die Fig. 1 zeigt einen etwas schematisierten Querschnitt ei­ ner Anordnung eines Halbleiterchips mit einem Gehäuse. Fig. 1 shows a somewhat schematic cross section egg ner arrangement of a semiconductor chip with a housing.

Die Fig. 2 zeigt die Anordnung von Fig. 1 in Aufsicht. Fig. 2 shows the arrangement of Fig. 1 in supervision.

In der Fig. 1 ist eine Anordnung eines Halbleiterchips 1 und eines Gehäuses als ein Beispiel einer erfindungsgemäßen Aus­ gestaltung des Halbleiterchipgehäuses dargestellt. Das Gehäu­ se umfasst eine dielektrische Trägerschicht 10 (Substrat, Ta­ pe) und eine Umverdrahtungsebene 2. Die Trägerschicht ist vorzugsweise ein Substrat aus einem Material, das auch bei der Herstellung von PCBs (printed circuit boards) verwendet wird. Eine derartige Trägerschicht bietet die Möglichkeit, mehrlagige Verdrahtungsstrukturen in der Umverdrahtungsebene zu realisieren. Ein solches Gehäuse wird z. B. beim so ge­ nannten Single-Component-Packaging wie dem Board-on-Chip- Ball-Grid-Array verwendet. Die in der Fig. 1 eingezeichnete Umverdrahtungsebene 2 besitzt eine Mehrzahl von Leiterbahnen 5, 6, 7, von denen hier nur ein paar als Beispiele einge­ zeichnet sind.In FIG. 1, an arrangement of a semiconductor chip 1 and a casing is provided as an example of the present invention from the semiconductor chip package design shown. The housing comprises a dielectric carrier layer 10 (substrate, Ta pe) and a redistribution layer 2 . The carrier layer is preferably a substrate made of a material that is also used in the production of PCBs (printed circuit boards). Such a carrier layer offers the possibility of realizing multi-layer wiring structures in the rewiring level. Such a housing is, for. B. used in so-called single-component packaging such as the board-on-chip ball grid array. The drawn in Fig. 1 redistribution layer 2 has a plurality of conductive tracks 5, 6, 7, of which here is only a few examples are as distinguished.

Die an dem Halbleiterchip 1 vorhandenen Anschlusskontaktflä­ chen 3 (pads) sind mittels Bonddrähten 4 mit den jeweiligen Leiterbahnen 6, 7 der Umverdrahtungsebene verbunden. Die ex­ ternen Anschlüsse der Leiterbahnen sind in diesem Beispiel eines Ball-Grid-Array durch die Leiterkugeln 16, 17 gebildet. Die Bonddrähte 4 sind, wie in der Fig. 1 angedeutet, in die Trägerschicht 10 eingebettet oder durch Aussparungen der Trä­ gerschicht geführt.The connection contact surfaces 3 (pads) on the semiconductor chip 1 are connected by means of bond wires 4 to the respective conductor tracks 6 , 7 of the rewiring level. The external connections of the conductor tracks are formed in this example of a ball grid array by the conductor balls 16 , 17 . As indicated in FIG. 1, the bond wires 4 are embedded in the carrier layer 10 or guided through recesses in the carrier layer.

In der Umverdrahtungsebene sind erfindungsgemäß mindestens ein Widerstand R und/oder ein Kondensator C integriert, wie das in dem Beispiel der Fig. 1 in einer möglichen Ausgestal­ tung, die aber grundsätzlich beliebig variiert werden kann, dargestellt ist. Der Kondensator C wird durch zwei struktu­ rierte Leiterbahnen 5, 6 gebildet, die in verschiedenen Lei­ terbahnebenen der Umverdrahtungsebene angeordnet sind. Einan­ der überlappende Leiterflächen dieser Leiterbahnen bilden die Kondensatorplatten des Kondensators C. Die Kapazität des Kon­ densators wird durch die Fläche der Kondensatorplatten und deren Abstand zueinander eingestellt. According to the invention, at least one resistor R and / or a capacitor C are integrated in the rewiring level, as shown in one possible embodiment in the example of FIG. 1, but which can in principle be varied as desired. The capacitor C is formed by two structured conductor tracks 5 , 6 , which are arranged in different Lei terbahnebenen the rewiring level. Einan at the overlapping conductor surfaces of these conductor tracks form the capacitor plates of the capacitor C. The capacitance of the capacitor is set by the area of the capacitor plates and their distance from one another.

In der anderen eingezeichneten Leiterbahn 7 ist ein ohmscher Widerstand R angebracht. Dieser Widerstand wird durch einen Werkstoff gebildet, der zwischen den einander gegenüberlie­ genden inneren Enden der hier unterbrochenen Leiterbahn ange­ bracht ist und eine so große elektrische Leitfähigkeit auf­ weist, dass durch eine passende Dimensionierung ein ohmscher Widerstand des vorgesehenen Widerstandswertes ausgebildet ist.An ohmic resistor R is attached in the other printed conductor 7 . This resistance is formed by a material which is brought between the mutually opposite inner ends of the interconnect interrupted here and has such a high electrical conductivity that an ohmic resistance of the intended resistance value is formed by suitable dimensioning.

In Fig. 2 ist die Anordnung gemäß Fig. 1 in einer Aufsicht gezeigt. Die Richtung des in der Fig. 1 dargestellten Quer­ schnitts ist markiert. Die Leiterbahn 5, in der diejenige Kondensatorplatte ausgebildet ist, die auf der von dem Halb­ leiterchip 1 abgewandten Seite angeordnet ist, ist mit einer Leiterkugel 15 versehen. Die übrigen Leiterbahnen 6, 7, die auch in Fig. 1 erkennbar sind, sind hier geradlinig ausge­ bildet. Die Form der Leiterbahnen ist aber nicht festgelegt, sondern kann an die jeweilige Ausführungsform des Chipmoduls angepasst sein.In FIG. 2, the arrangement according to Fig. 1 in a plan view. The direction of the cross section shown in Fig. 1 is marked. The conductor track 5 , in which the capacitor plate is formed, which is arranged on the side facing away from the semiconductor chip 1 , is provided with a conductor ball 15 . The remaining conductor tracks 6 , 7 , which can also be seen in Fig. 1, are formed here in a straight line. However, the shape of the conductor tracks is not fixed, but can be adapted to the particular embodiment of the chip module.

Der Widerstand R bzw. der Kondensator C dient in dieser An­ ordnung der Entkopplung einer Spannung, z. B. einer Signal­ spannung. Im Fall der Verwendung eines Kondensators werden die Anschlüsse (hier: Signal und Masse) an die betreffenden Leiterkugeln 15, 16 in der geeignet gewählten Polung ange­ legt. Im Fall der Verwendung eines Widerstandes wird bei­ spielsweise ein Anschluss der Spannung an die Leiterkugel 17 der betreffenden Leiterbahn 7 gelegt, die über den Widerstand R zu der betreffenden Anschlusskontaktfläche des Halbleiter­ chips 1 führt; der andere Anschluss der Spannung wird direkt an den Halbleiterchip 1 gelegt. Auch hier ist die Polung wählbar.The resistor R or the capacitor C is used in this order to decouple a voltage, for. B. a signal voltage. In the case of using a capacitor, the connections (here: signal and ground) to the relevant conductor balls 15 , 16 are placed in the appropriately selected polarity. In the case of using a resistor, for example, a connection of the voltage to the conductor ball 17 of the conductor track 7 in question, which leads via the resistor R to the relevant contact pad of the semiconductor chip 1 ; the other connection of the voltage is connected directly to the semiconductor chip 1 . The polarity can also be selected here.

In der Fig. 2 ist mit den strichpunktierten Linien eine al­ ternative Ausgestaltung eingezeichnet. Die Spannung wird hier an den Widerstand R angelegt, indem die Anschlüsse an zwei Leiterkugeln 17, 18 gelegt werden, die zugehörige Leiterbah­ nen 7, 8 kontaktieren (signal termination [to GND] an packa­ ge).In Fig. 2, an al alternative design is drawn with the dash-dotted lines. The voltage is applied here to the resistor R by connecting the connections to two conductor balls 17 , 18 , contacting the associated conductor tracks 7 , 8 (signal termination [to GND] to packa ge).

Die erfindungsgemäß in die Umverdrahtungsebene integrierten Widerstände und Kondensatoren können mit modernen Fertigungs­ technologien wie z. B. SIMOV einfach hergestellt werden. Da­ durch ergeben sich insbesondere die folgenden Vorteile: Die Toleranzen bei der Platzierung der Bauelemente, insbesondere in SMT-Montage (surface mounted technology) sind weitgehend entspannt; teilweise entfällt die Platzierung von Widerstän­ den und Kondensatoren vollständig. Wegen der mit den inte­ grierten passiven Komponenten erreichten Platzersparnis ist die Verwendung kleinerer Platinen möglich. Kapazitäten zur Entkopplung der Spannungsversorgung können sehr viel näher an den Off-Chip-Treibern angeordnet werden. Durch kürzere Cur­ rent-Return-Pfade ergibt sich ein verringerter Ground-Bounce bzw. weniger Simultaneous-Switching-Noise.The integrated in the rewiring level according to the invention Resistors and capacitors can be used with modern manufacturing technologies such as B. SIMOV can be easily manufactured. because This results in the following advantages in particular: The Tolerances in the placement of the components, in particular in SMT assembly (surface mounted technology) are largely relaxed; the placement of resistors is partially omitted the and capacitors completely. Because of the inte passive components achieved is space-saving the use of smaller boards is possible. Capacities for Decoupling the power supply can be much closer the off-chip drivers. With a shorter cur Rent-return paths result in a reduced ground bounce or less simultaneous switching noise.

Claims (7)

1. Halbleiterchipgehäuse mit Umverdrahtungsebene, dadurch gekennzeichnet, dass in der Umverdrahtungsebene (2) mindestens ein Widerstand (R) und/oder Kondensator (C) ausgebildet ist.1. Semiconductor chip housing with rewiring level, characterized in that at least one resistor (R) and / or capacitor (C) is formed in the rewiring level ( 2 ). 2. Halbleiterchipgehäuse nach Anspruch 1, bei dem die Umverdrahtungsebene (2) nach Art eines Board-on-Chip- Ball-Grid-Array ausgebildet ist.2. The semiconductor chip package according to claim 1, wherein the redistribution layer ( 2 ) is designed in the manner of a board-on-chip ball grid array. 3. Halbleiterchipgehäuse nach Anspruch 1 oder 2, bei dem eine mehrlagige Verdrahtungsstruktur in der Umverdrahtungs­ ebene vorhanden ist.3. A semiconductor chip package according to claim 1 or 2, in which a multilayer wiring structure in the rewiring level exists. 4. Halbleiterchipgehäuse nach einem der Ansprüche 1 bis 3, bei dem mindestens ein Kondensator (C) in der Umverdrahtungsebene zur Entkopplung einer angelegten elektrischen Spannung vorhanden ist.4. Semiconductor chip housing according to one of claims 1 to 3, in which at least one capacitor (C) in the rewiring level Decoupling of an applied electrical voltage is present is. 5. Halbleiterchipgehäuse nach einem der Ansprüche 1 bis 4, das für einen Halbleiterchip, der ein Speicherchip ist, vor­ gesehen ist.5. Semiconductor chip housing according to one of claims 1 to 4, that for a semiconductor chip that is a memory chip is seen. 6. Halbleiterchipgehäuse nach einem der Ansprüche 1 bis 5, das Bestandteil eines Chipmoduls ist.6. semiconductor chip package according to one of claims 1 to 5, is part of a chip module. 7. Halbleiterchipgehäuse nach Anspruch 6, bei dem das Chipmo­ dul ein SO-DIMM ist.7. The semiconductor chip package according to claim 6, wherein the Chipmo is an SO-DIMM.
DE10051467A 2000-10-17 2000-10-17 Semiconducting chip housing has wiring plane with at least one resistor and/or capacitor in form of board-on-chip ball grid array with wiring structure of one or more layers Ceased DE10051467A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE10051467A DE10051467A1 (en) 2000-10-17 2000-10-17 Semiconducting chip housing has wiring plane with at least one resistor and/or capacitor in form of board-on-chip ball grid array with wiring structure of one or more layers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10051467A DE10051467A1 (en) 2000-10-17 2000-10-17 Semiconducting chip housing has wiring plane with at least one resistor and/or capacitor in form of board-on-chip ball grid array with wiring structure of one or more layers

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DE10051467A1 true DE10051467A1 (en) 2002-05-02

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DE10051467A Ceased DE10051467A1 (en) 2000-10-17 2000-10-17 Semiconducting chip housing has wiring plane with at least one resistor and/or capacitor in form of board-on-chip ball grid array with wiring structure of one or more layers

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WO2003065448A1 (en) * 2002-01-29 2003-08-07 Siemens Aktiengesellschaft Chip-size package with an integrated passive component

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DE3626151A1 (en) * 1986-08-01 1988-02-04 Siemens Ag Voltage supply for an integrated semiconductor circuit
DE3915998A1 (en) * 1989-05-17 1990-11-29 Vdo Schindling Electronic component with integrated circuit - has voltage supply strip lines coupled each to capacitor electrode
US6052287A (en) * 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier

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DE3626151A1 (en) * 1986-08-01 1988-02-04 Siemens Ag Voltage supply for an integrated semiconductor circuit
DE3915998A1 (en) * 1989-05-17 1990-11-29 Vdo Schindling Electronic component with integrated circuit - has voltage supply strip lines coupled each to capacitor electrode
US6052287A (en) * 1997-12-09 2000-04-18 Sandia Corporation Silicon ball grid array chip carrier

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003065448A1 (en) * 2002-01-29 2003-08-07 Siemens Aktiengesellschaft Chip-size package with an integrated passive component
DE10203397A1 (en) * 2002-01-29 2003-08-21 Siemens Ag Chip size package with integrated passive component
DE10203397B4 (en) * 2002-01-29 2007-04-19 Siemens Ag Chip-size package with integrated passive component

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