DE10018358A1 - Halbleiter-Bauteil und dessen Herstellungsverfahren - Google Patents
Halbleiter-Bauteil und dessen HerstellungsverfahrenInfo
- Publication number
- DE10018358A1 DE10018358A1 DE2000118358 DE10018358A DE10018358A1 DE 10018358 A1 DE10018358 A1 DE 10018358A1 DE 2000118358 DE2000118358 DE 2000118358 DE 10018358 A DE10018358 A DE 10018358A DE 10018358 A1 DE10018358 A1 DE 10018358A1
- Authority
- DE
- Germany
- Prior art keywords
- layer
- semiconductor
- electrically conductive
- substrate
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
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Abstract
Description
- 1. einen Schritt, bei dem eine Leiterbahnelektrode auf einem ersten Halbleiter substrat angebracht wird;
- 2. einen Schritt des sequenziellen Abscheidens einer Isolierschicht und einer Masseschicht auf dem ersten Substrat und des Einbohrens von Durchgangslö chern für Anschluss an die Leiterbahnelektrode in die Isolierschicht und die Masseschicht;
- 3. einen Schritt des Herstellens einer Durchgangsloch-Leiterbahn in den Durchgangslöchern für elektrischen Anschluss an die Leiterbahnelektrode;
- 4. einen Schritt des Herstellens einer Isolierschicht zwischen der Durchgangs loch-Leiterbahn in dem Durchgangsloch in der Masseschicht und der Masseschicht;
- 5. einen Schritt des Glättens einer der Hauptflächen des ersten Substrats:
- 6. einen Schritt des vorab Herausführens einer Leiterbahnelektrode auf einem zweiten Halbleitersubstrat;
- 7. einen Schritt des sequenziellen Abscheidens einer Isolierschicht und einer Masseschicht auf dem zweiten Halbleitersubstrat und des Herstellens von Durchgangslöchern für Anschluss an die Leiterbahnelektrode in der Isolier schicht und der Masseschicht;
- 8. einen Schritt des Herstellens einer Durchgangsloch-Leiterbahn im Durch gangsloch für elektrischen Anschluss der Leiterbahnelektrode;
- 9. einen Schritt des Herstellens eines Isolators zwischen der Durchgangsloch- Leiterbahn innerhalb des Durchgangslochs in der Masseschicht und der Masse schicht;
- 10. einen Schritt des Glättens der Oberfläche des zweiten Halbleitersubstrats;
- 11. einen Schritt des Positionierens des ersten und des zweiten Halbleitersub strats in solcher Weise, dass die Durchgangsloch-Leiterbahnen und die Masse schichten dieser beiden Substrate einander zugewandt sind;
- 12. Ausüben einer Kompressionsbelastung von beiden Seiten der Substrate her; und
- 13. elektrisches und mechanisches Verbinden der Durchgangsloch-Leiterbah nen und der Masseschichten unter der Kompressionsbelastung.
- 1. einen Schritt, bei dem eine Leiterbahnelektrode auf einem ersten Halbleiter substrat angebracht wird;
- 2. einen Schritt des sequenziellen Abscheidens einer Isolierschicht und einer Masseschicht auf dem ersten Substrat und des Einbohrens von Durchgangslö chern für Anschluss an die Leiterbahnelektrode in die Isolierschicht und die Masseschicht;
- 3. einen Schritt des Herstellens einer Durchgangsloch-Leiterbahn in den Durchgangslöchern für elektrischen Anschluss an die Leiterbahnelektrode;
- 4. einen Schritt des Herstellens eines Isolators zwischen der Durchgangsloch- Leiterbahn im Durchgangsloch in der Masseschicht und der Masseschicht;
- 5. einen Schritt des Glättens der Hauptfläche des ersten Substrats;
- 6. einen Schritt, bei dem eine Leiterbahnelektrode auf einem zweiten Halbleiter substrat angebracht wird;
- 7. einen Schritt des Abscheidens einer Isolierschicht auf dem zweiten Halblei tersubstrat und des Herstellens eines Durchgangslochs für Anschluss an die Leiterbahnelektrode in der Isolierschicht;
- 8. einen Schritt des Herstellens einer Durchgangsloch-Leiterbahn im Durch gangsloch für elektrischen Anschluss an die Leiterbahnelektrode;
- 9. einen Schritt des Glättens der Hauptflächen des zweiten Substrats;
- 10. einen Schritt des Positionierens des ersten und des zweiten Halbleitersub strats in solcher Weise, dass die Durchgangsloch-Leiterbahnen in diesen beiden Substrate einander zugewandt sind und die Masseschicht des ersten Substrats der Isolierschicht des zweiten Substrats zugewandt ist;
- 11. Ausüben einer Kompressionsbelastung von beiden Seiten der Substrate her; und
- 12. elektrisches Verbinden der Durchgangsloch-Leiterbahnen miteinander und mechanisches Verbinden der Isolierschicht des ersten Substrats und der Isolier schicht des zweiten Substrats unter der Kompressionsbelastung miteinander.
- 1. einen Schritt des vorab Herausführens einer Leiterbahnelektrode auf einem ersten Halbleitersubstrat;
- 2. einen Schritt des sequenziellen Abscheidens einer Isolierschicht, einer Masseschicht und einer anderen Isolierschicht auf dem ersten Substrat sowie des Einbohrens von Durchgangslöchern für Anschluss an die Leiterbahnelektro de in die Isolierschicht, die Masseschicht und die andere Isolierschicht;
- 3. einen Schritt des Herstellens einer Durchgangsloch-Leiterbahn in den Durchgangslöchern für elektrischen Anschluss an die Leiterbahnelektrode;
- 4. einen Schritt, bei dem ein Isolator zwischen der Durchgangs-Leiterbahn in den Durchgangslöchern der Masseschicht und der Masseschicht ausgebildet wird;
- 5. einen Schritt des Glättens der Hauptfläche des ersten Substrats;
- 6. einen Schritt des vorab Herausführens einer Leiterbahnelektrode auf einem zweiten Halbleitersubstrat;
- 7. einen Schritt des sequenziellen Abscheidens einer Isolierschicht und einer Spannunsversorgungsschicht auf dem zweiten Halbleitersubstrat und des Her stellens von Durchgangslöchern für Anschluss an die Leiterbahnelektrode in der Isolierschicht und der Spannungsversorgungsschicht;
- 8. einen Schritt des Herstellens einer Durchgangslochleitschicht für den elek trischen Anschluss der Leiterbahnelektrode in dem Durchgangsloch;
- 9. einen Schritt des Herstellens eines Isolators zwischen der Durchgangsloch leitschicht der Spannungsversorgungsschicht und der Spannungsversorgungs schicht;
- 10. Glätten der Oberfläche des zweiten Halbleitersubstrats;
- 11. einen Schritt des Positionierens des ersten und zweiten Halbleitersubstrats in Ausrichtung miteinander in solcher Weise, dass die Durchgangsloch-Leiter bahnen im ersten und zweiten Halbleitersubstrat einander zugewandt sind und die Isolierschichten und die Stromversorgungsschichten der beiden Substrate einander zugewandt sind;
- 12. Ausüben einer Kompressionsbelastung von beiden Seiten der Substrate her: und
- 13. elektrisches Verbinden der Durchgangsloch-Leiterbahnen und mechani sches Verbinden der Isolierschichten und der Spannungsversorgungsschichten unter der Kompressionsbelastung.
- 1. einen Schritt des vorab Herausführens einer Leiterbahnelektrode und einer Masseelektrode auf einem ersten Halbleitersubstrat;
- 2. sequenzielles Abscheiden einer Isolierschicht und einer Masseschicht auf dem ersten Substrat und Herstellen eines Durchgangslochs für Anschluss an die Leiterbahnelektrode in der Isolierschicht;
- 3. Herstellen einer Durchgangsloch-Masseleiterbahn für elektrischen Anschluss an die Masseelektrode im Durchgangsloch;
- 4. Glätten der Oberflächen des ersten Substrats;
- 5. vorab Herausführen einer Masseelektrode auf einem zweiten Halbleitersub strat;
- 6. sequenzielles Abscheiden einer Isolierschicht und einer Masseschicht auf dem zweiten Substrat und Herstellen eines Durchgangslochs für Anschluss an die Masseelektrode in der Isolierschicht;
- 7. Herstellen einer Durchgangsloch-Masseleiterbahn für elektrischen Anschluss an die Masseelektrode im Durchgangsloch;
- 8. Glätten der Oberfläche des anderen Halbleitersubstrats;
- 9. Positionieren des ersten und des zweiten Halbleitersubstrats durch Ausrich tung miteinander in solcher Weise, dass die Masseschichten der beiden Sub strate einander zugewandt sind;
- 10. Ausüben einer Kompressionsbelastung von beiden Seiten der Substrate her; und
- 11. elektrisches und mechanisches Verbinden der Masseschichten unter der Kompressionsbelastung.
- 1. einen Schritt des vorab Herausführens einer Masseelektrode auf einem er sten Halbleitersubstrat;
- 2. einen Schritt des sequenziellen Abscheidens einer Isolierschicht und einer Masseschicht auf dem ersten Substrat und des Einbohrens eines Durchgangs lochs für Anschluss an die Masseelektrode in die Isolierschicht;
- 3. einen Schritt des Herstellens einer Durchgangsloch-Masseleiterbahn im Durchgangsloch für elektrischen Anschluss an die Masseelektrode;
- 4. einen Schritt des Glättens der Oberfläche des ersten Substrats;
- 5. einen Schritt des vorab Herausführens einer Masseelektrode auf einem zweiten Halbleitersubstrat;
- 6. einen Schritt des Herstellens einer Isolierschicht auf dem zweiten Halbleiter substrat und des Herstellens eines Durchgangslochs für Anschluss an die Mas seelektrode in der Isolierschicht;
- 7. einen Schritt des Herstellens einer Durchgangsloch-Masseleiterbahn für elektrischen Anschluss an die Masseelektrode im Durchgangsloch;
- 8. einen Schritt des Glättens der Oberfläche des zweiten Halbleitersubstrats;
- 9. Positionieren des ersten und des zweiten Substrats in solcher Weise, dass die Masseschichten Durchgangsloch-Masseleiterbahnen auf dem ersten und zweiten Substrat einander zugewandt sind;
- 10. Ausüben einer Kompressionsbelastung von beiden Seiten der Substrate her; und
- 11. elektrisches Verbinden der Masseschicht und der Durchgangsloch-Masse leiterbahn unter der Kompressionsbelastung sowie mechanisches Verbinden der Masseschicht des ersten Substrats und der Isolierschicht des zweiten Substrats.
- 1. einen Schritt des vorab Herausführens einer Masseelektrode auf einem er sten Halbleitersubstrat;
- 2. einen Schritt des sequenziellen Abscheidens einer Isolierschicht und einer Masseschicht auf dem ersten Substrat und des Einbohrens eines Durchgangs lochs für Anschluss an die Masseelektrode in die Isolierschicht;
- 3. einen Schritt des Herstellens einer Durchgangsloch-Masseleiterbahn im Durchgangsloch für elektrischen Anschluss an die Masseelektrode;
- 4. einen Schritt des Glättens des ersten Substrats;
- 5. einen Schritt des Abscheidens einer anderen Isolierschicht auf der Masseschicht;
- 6. Glätten der Oberfläche des ersten Substrats;
- 7. einen Schritt des Herausführen einer Stromversorgungselektrode auf einem zweiten Halbleitersubstrat;
- 8. Abscheiden einer Isolierschicht auf einem zweiten Substrat und Herstellen eines Durchgangslochs für Anschluss an eine Spannungsversorgungselektrode in der Isolierschicht;
- 9. einen Schritt des Herstellens einer Durchgangsloch-Stromversorgungsleiter bahn für elektrischen Anschluss an die Stromversorgungselektrode im Durch gangsloch;
- 10. einen Schritt des Glättens der Oberfläche des zweiten Substrats;
- 11. Abscheiden einer Spannungsversorgungsschicht für elektrischen Anschluss an die Durchgangsloch-Spannungsversorgungsleiterbahn auf dem zweiten Halb leitersubstrat;
- 12. Positionieren des ersten und des zweiten Halbleitersubstrats in solcher Ausrichtung zueinander, dass die Isolierschichten und die Spannungsver sorgungsschicht dieser beiden Substrate einander zugewandt sind;
- 13. Ausüben einer Kompressionsbelastung von beiden Seiten der Substrate und
- 14. mechanisches Verbinden der Isolierschicht und der Spannungsver sorgungsschicht unter der Kompressionsbelastung.
- 1. vorab Herausführen einer Leiterbahnelektrode, einer Masseelektrode und ei ner Spannungsversorgungselektrode auf einem ersten Halbleitersubstrat;
- 2. sequenzielles Abscheiden einer Isolierschicht, einer Masseschicht und einer anderen Isolierschicht auf dem ersten Substrat und Herstellen eines Durch gangslochs für Anschluss an die Spannungsversorgungselektrode in der Isolier schicht, der Masseschicht und der anderen Isolierschicht;
- 3. Herstellen einer Durchgangsloch-Stromversorgungsleiterbahn für elektri schen Anschluss an die Stromversorgungselektrode im Durchgangsloch;
- 4. einen Schritt des Herstellens einer Isolierschicht zwischen der Umfangswand des Durchgangslochs in der Isolierschicht, der Masseschicht und der anderen Isolierschicht und der Durchgangsloch-Stromversorgungsleitung;
- 5. einen Schritt des Glättens der Hauptfläche des ersten Substrats;
- 6. einen Schritt des Herausführens einer Spannungsversorgungselektrode auf einem zweiten Halbleitersubstrat;
- 7. sequenzielles Abscheiden einer Isolierschicht und einer Spannungsver sorgungsschicht auf dem zweiten Substrat und Herstellen eines Durch gangslochs für Anschluss an die Spannungsversorgungselektrode in der Isolier schicht und der Spannungsversorgungsschicht;
- 8. Herstellen einer Durchgangsloch-Spannungsversorgungsleiterbahn für elek trischen Anschluss an die Spannungsversorgungselektrode im Durchgangsloch;
- 9. einen Schritt des Glättens der Oberfläche des zweiten Halbleitersubstrats;
- 10. einen Schritt des Positionierens des ersten und des zweiten Halbleitersub strats in solcher Ausrichtung zueinander, dass die Durchgangsloch-Spannungs versorgungsleiterbahnen auf dem ersten und zweiten Halbleitersubstrat einan der zugewandt sind und die Isolierschicht und die Spannungsversorgungs schicht auf dem ersten und zweiten Halbleitersubstrat einander zugewandt sind;
- 11. einen Schritt des Ausübens einer Kompressionsbelastung von beiden Seiten der zwei Substrate her; und
- 12. einen Schritt des elektrischen Verbindens der Durchgangsloch-Spannungs versorgungsleiterbahnen und des mechanischen Verbindens der Isolierschicht und der Spannungsversorgungsschicht unter der Kompressionsbelastung.
- 1. ein Schritt des vorab Herausführens einer Masseelektrode auf dem ersten Halbleitersubstrat;
- 2. ein Schritt des Abscheidens einer Isolierschicht auf dem ersten Substrat und des Herstellens eines Durchgangslochs für Anschluss an die Masseelektrode in der Isolierschicht;
- 3. ein Schritt des Herstellens einer Leitschicht im Masse-Durchgangsloch, wel che die Masseelektrode im Durchgangsloch elektrisch kontaktiert;
- 4. ein Schritt des Herstellens einer Masseschicht für elektrischen Anschluss an die Durchgangsloch-Masseleiterbahn auf der Isolierschicht;
- 5. ein Schritt des Glättens einer der Oberflächen eines der zwei Substrate;
- 6. ein Schritt des vorab Herausführens einer Masseelektrode auf dem zweiten Halbleitersubstrat;
- 7. ein Schritt des Abscheidens einer Isolierschicht auf dem zweiten Substrat und des Herstellens eines Durchgangslochs für Anschluss an die Masseelektro de in der Isolierschicht;
- 8. Herstellen einer Durchgangsloch-Masseleiterbahn für elektrischen Anschluss an eine Masseelektrode im Durchgangsloch im zweiten Substrat und
- 9. Herstellen einer Masseschicht für elektrischen Anschluss an die Durch gangsloch-Masseleiterbahn auf der Isolierschicht.
- a) die Leiterbahnschicht und die Bauteilschicht sind als zwei gesonderte Schich ten angeordnet, um durch Abtrennen der Leiterbahnschicht verbesserte Aus beute zu erzielen;
- b) da die Bauteilschicht durch mehrere miteinander verbundene Schichten rea lisiert ist, ist eine Trennung analog/digital mit zugehöriger Beschleunigung rea lisiert;
- c) da zwei Hetero-Bauteilschichten abgeschieden werden, kann eine Trennung analog/digital mit sich ergebender hoher Betriebsgeschwindigkeit realisiert wer den;
- d) da optische Bauelemente auf ein Siliziumsubstrat gebondet werden können, kann ein optisches Bauteil auf einem elektronischen Substrat montiert werden;
- e) durch einen Bordvorgang für ein Hetero-Halbleitersubstrat können Verbund substrate und demgemäß ein Heteroepitaxiesubstrat realisiert werden.
Claims (11)
- - auf jedem Halbleitersubstrat eine Isolierschicht (7, 8) abgeschieden ist, mit ei ner Verbindungsleiterbahn (5, 6), die diese Isolierschicht für Anschluss an eine Leiterbahnschicht (3, 4) auf den Halbleiterelementen durchdringt;
- - eine elektrisch leitende Schicht (9, 10) aus einem elektrisch leitenden Material mit einer Öffnung, die durch Strukturieren in Übereinstimmung mit der Verbin dungsleiterbahn versehen ist, auf einer Grenzfläche mindestens einer der Halb leitersubstrate vorhanden ist; und
- - die Halbleitersubstrate miteinander verbunden sind, um die auf jedem Halblei tersubstrat hergestellten Verbindungsleiterbahnen miteinander zu verbinden.
- - auf einer Grenzfläche jedes des Paars von Halbleitersubstraten (1, 2), die mit einander verbunden sind, eine elektrisch leitende Schicht (9, 10) ausgebildet ist und
- - die diese elektrisch leitenden Schichten bildenden Metallmaterialien miteinan der verbunden werden.
- - auf einer Grenzfläche eines der Halbleitersubstrate (1, 2) des Paars, die mit einander zu verbinden sind, eine elektrisch leitende Schicht (9) vorhanden ist und
- - diese elektrisch leitende Schicht und die Isolierschicht (8) des gegenüberste henden Halbleitersubstrats (2) miteinander verbunden sind (Fig. 3).
- - Abscheiden einer Isolierschicht (7, 8) auf einem Halbleitersubstrat und Her stellen einer Verbindungsleiterbahn (5, 6), die mit einer Leiterbahnschicht (3, 4) für die Halbleiterelemente verbunden wird, in der Isolierschicht;
- - Herstellen einer elektrisch leitenden Schicht (9, 10) aus einem elektrisch lei tenden Material, mit einer Öffnung, die durch Strukturieren in Ausrichtung mit der Verbindungsleiterbahn hergestellt wird, auf einer Grenzfläche mindestens eines der mehreren Halbleitersubstrate;
- - Glätten der Grenzfläche jedes Halbleitersubstrats; und
- - Ausüben einer Kompressionsbelastung von beiden Seiten der aufeinanderge legten Halbleitersubstrate her, um diese miteinander zu verbinden und die in je dem Halbleitersubstrat erzeugten Verbindungsleiterbahnen miteinander zu verbinden.
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-
2000
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- 2000-04-12 KR KR20000019199A patent/KR100773615B1/ko active IP Right Grant
- 2000-04-13 DE DE2000118358 patent/DE10018358B4/de not_active Expired - Lifetime
- 2000-04-13 FR FR0004753A patent/FR2792458B1/fr not_active Expired - Fee Related
- 2000-04-13 US US09/548,916 patent/US6465892B1/en not_active Expired - Lifetime
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2001
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Cited By (4)
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WO2010054618A1 (de) * | 2008-11-14 | 2010-05-20 | Osram Opto Semiconductors Gmbh | Verbundsubstrat für einen halbleiterchip |
US8598705B2 (en) | 2008-11-14 | 2013-12-03 | Osram Opto Semiconductors Gmbh | Composite substrate for a semiconductor chip |
WO2015000527A1 (de) * | 2013-07-05 | 2015-01-08 | Ev Group E. Thallner Gmbh | Verfahren zum bonden von metallischen kontaktflächen unter lösen einer auf einer der kontaktflächen aufgebrachten opferschicht in mindestens einer der kontaktflächen |
US9640510B2 (en) | 2013-07-05 | 2017-05-02 | Ev Group E. Thallner Gmbh | Method for bonding metallic contact areas with solution of a sacrificial layer applied on one of the contact areas |
Also Published As
Publication number | Publication date |
---|---|
FR2792458A1 (fr) | 2000-10-20 |
DE10018358B4 (de) | 2008-05-21 |
KR20010006980A (ko) | 2001-01-26 |
US20020074670A1 (en) | 2002-06-20 |
KR100773615B1 (ko) | 2007-11-05 |
JP2000299379A (ja) | 2000-10-24 |
TW462125B (en) | 2001-11-01 |
JP3532788B2 (ja) | 2004-05-31 |
US6465892B1 (en) | 2002-10-15 |
FR2792458B1 (fr) | 2005-06-24 |
US6472293B2 (en) | 2002-10-29 |
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R081 | Change of applicant/patentee |
Owner name: ROHM CO. LTD., KYOTO-SHI, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; MITSUBISHI DENKI K.K., TOKYO, JP; NEC CORP., TOKYO, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Effective date: 20140915 Owner name: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; MITSUBISHI DENKI K.K., TOKYO, JP; NEC CORP., TOKYO, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Effective date: 20140915 Owner name: SANYO ELECTRIC CO., LTD., MORIGUCHI, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; MITSUBISHI DENKI K.K., TOKYO, JP; NEC CORP., TOKYO, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Effective date: 20140915 Owner name: NEC CORP., JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; MITSUBISHI DENKI K.K., TOKYO, JP; NEC CORP., TOKYO, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Effective date: 20140915 Owner name: SONY CORPORATION, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; MITSUBISHI DENKI K.K., TOKYO, JP; NEC CORP., TOKYO, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Effective date: 20140915 Owner name: RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; MITSUBISHI DENKI K.K., TOKYO, JP; NEC CORP., TOKYO, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Effective date: 20140915 Owner name: SHARP K.K., JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; MITSUBISHI DENKI K.K., TOKYO, JP; NEC CORP., TOKYO, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Effective date: 20140915 Owner name: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, JP Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR LIMITED, MITSUBISHI DENKI K.K., NEC CORP., ROHM CO. LTD., SANYO ELECTRIC CO., LTD., SHARP K.K., SONY CORPO, , JP Effective date: 20140915 Owner name: NEC CORP., JP Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR LIMITED, MITSUBISHI DENKI K.K., NEC CORP., ROHM CO. LTD., SANYO ELECTRIC CO., LTD., SHARP K.K., SONY CORPO, , JP Effective date: 20140915 Owner name: RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, JP Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR LIMITED, MITSUBISHI DENKI K.K., NEC CORP., ROHM CO. LTD., SANYO ELECTRIC CO., LTD., SHARP K.K., SONY CORPO, , JP Effective date: 20140915 Owner name: SHARP K.K., JP Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR LIMITED, MITSUBISHI DENKI K.K., NEC CORP., ROHM CO. LTD., SANYO ELECTRIC CO., LTD., SHARP K.K., SONY CORPO, , JP Effective date: 20140915 Owner name: ROHM CO. LTD., KYOTO-SHI, JP Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR LIMITED, MITSUBISHI DENKI K.K., NEC CORP., ROHM CO. LTD., SANYO ELECTRIC CO., LTD., SHARP K.K., SONY CORPO, , JP Effective date: 20140915 Owner name: SONY CORPORATION, JP Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR LIMITED, MITSUBISHI DENKI K.K., NEC CORP., ROHM CO. LTD., SANYO ELECTRIC CO., LTD., SHARP K.K., SONY CORPO, , JP Effective date: 20140915 Owner name: SANYO ELECTRIC CO., LTD., MORIGUCHI, JP Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR LIMITED, MITSUBISHI DENKI K.K., NEC CORP., ROHM CO. LTD., SANYO ELECTRIC CO., LTD., SHARP K.K., SONY CORPO, , JP Effective date: 20140915 Owner name: RENESAS ELECTRONICS CORPORATION, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; MITSUBISHI DENKI K.K., TOKYO, JP; NEC CORP., TOKYO, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Effective date: 20140915 |
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R082 | Change of representative |
Representative=s name: MUELLER HOFFMANN & PARTNER PATENTANWAELTE MBB, DE Effective date: 20140915 |
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R081 | Change of applicant/patentee |
Owner name: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: SANYO ELECTRIC CO., LTD., MORIGUCHI, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: ROHM CO. LTD., JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: SONY CORPORATION, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: SHARP K.K., JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: RENESAS ELECTRONICS CORPORATION, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: NEC CORP., JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: SONY CORPORATION, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: NEC CORP., JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: SHARP K.K., JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: ROHM CO. LTD., KYOTO-SHI, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: SANYO ELECTRIC CO., LTD., MORIGUCHI, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: RENESAS ELECTRONICS CORPORATION, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP Owner name: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, JP Free format text: FORMER OWNERS: FUJITSU SEMICONDUCTOR LIMITED, YOKOHAMA-SHI, KANAGAWA, JP; NEC CORP., TOKYO, JP; RENESAS ELECTRONICS CORPORATION, KAWASAKI-SHI, KANAGAWA, JP; ROHM CO. LTD., KYOTO-SHI, KYOTO, JP; SANYO ELECTRIC CO., LTD., MORIGUCHI, OSAKA, JP; SHARP K.K., OSAKA, JP; SONY CORPORATION, TOKIO/TOKYO, JP |
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R082 | Change of representative |
Representative=s name: MUELLER HOFFMANN & PARTNER PATENTANWAELTE MBB, DE |
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R071 | Expiry of right |