CN2751444Y - 具应变通道的互补式金氧半导体 - Google Patents

具应变通道的互补式金氧半导体 Download PDF

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CN2751444Y
CN2751444Y CNU2004200483776U CN200420048377U CN2751444Y CN 2751444 Y CN2751444 Y CN 2751444Y CN U2004200483776 U CNU2004200483776 U CN U2004200483776U CN 200420048377 U CN200420048377 U CN 200420048377U CN 2751444 Y CN2751444 Y CN 2751444Y
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杨育佳
柯志欣
李文钦
胡正明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本实用新型揭示一种具应变通道的互补式金氧半导体，主要包括：一半导体基底、设置于上述半导体基底内的多个沟槽隔离区、一氮化物衬垫层、一离子布植氮化物衬垫层、一N型通道晶体管以及一P型通道晶体管。其中，相邻两沟槽隔离区之间各定义出一主动区，主动区包括一N型主动区与一P型主动区。另外，氮化物衬垫层，顺应性设置于上述N型主动区两侧的上述沟槽隔离区与上述半导体基底之间。再者，离子布植氮化物衬垫层，顺应性设置于上述P型主动区两侧的沟槽隔离区与半导体基底之间。并且，N型通道晶体管，设置于N型主动区上方。以及，P型通道晶体管，设置于P型主动区上方。

Description

具应变通道的互补式金氧半导体
技术领域
本实用新型是有关于一种场效晶体管，且特别是有关于一种包括具有拉伸应变的N型通道晶体管(NMOS)与具有压缩应力的P型通道晶体管(PMOS)的互补式金氧半场效晶体管(CMOS)组件。
背景技术
随着栅极组件尺寸的缩小化，要使金氧半场效晶体管(MOSFET)组件能在低操作电压下，具有高趋动电流和高速的效能是相当困难的。因此，许多人在努力寻求改善金氧半场效晶体管组件的效能的方法。
利用应变引发的能带结构变型来增加载子的迁移率，以增加场效晶体管的趋动电流，可改善场效晶体管组件的效能，且此种方法已被应用于各种组件中。这些组件的硅信道是处于双轴拉伸应变的情况。
已有研究指出利用硅通道处于双轴拉伸应变的情况中来增加电子的迁移率(K.Ismail et al.，“Electron transport properties in Si/SiGeheterostructures：Measurements and device applications”，Appl.Phys.Lett.63，pp.660，1993.)，及利用硅锗通道处于双轴压缩应变的情况中来增加电洞的迁移率(D.K.Nayak et al.，“Enhancement-modequantum-well GeSi PMOS”，IEEE Elect.Dev.Lett.12，pp.154，1991.)。然而，结合具有双轴拉伸应变的硅通道的NMOSFETs(N型金氧半场效晶体管)及具有双轴压缩应变的硅锗通道的PMOSFETs(P型金氧半场效晶体管)的CMOS制程技术是难以达成的。在晶体管的制造上有利用厚的缓冲层或复杂多层结构等许多应变层制造方法(K.Ismail et al.，IBM，Jul.1996，Complementary metal-oxide semiconductor transistorlogic using strained Si/SiGe heterostructure layers，U.S.PatentNo.5534713.)，此些方法并不易于整合到传统的CMOS制程中。
再者，更有研究提出以覆盖一层应力膜于整个晶体管上方的方式，以提供适当的应力予晶体管的通道区(A.Shimizu et al.，“Localmechanical stress control(LMC)：A new technique for CMOSperformance enhancement”，pp.433-436 of the Digest of TechnicalPapers of the 2001 International Electron Device Meeting.)
然而，于通道区导入压缩应力有利于改善电动的迁移速率，却会对电子迁移率造成退化。因此，对N型通道晶体管(NMOS)而言，需要导入拉伸应力以提升电子迁移率，而对P型通道晶体管(PMOS)而言，需要导入压缩应力以提升电洞迁移率。但是在同一芯片上欲制作出同时具有拉伸应力信道区的N型信道晶体管(NMOS)与压缩应力信道区的P型信道晶体管(PMOS)的互补式金氧半导体(CMOS)，却有相当的困难。
有鉴于此，本实用新型提出一种可同时具拉伸应力通道区与压缩应力通道区的半导体基底，可适用于制作互补式金氧半导体。
发明内容
本实用新型的目的在于一种具应变信道的互补式金氧半导体，使N型信道晶体管的信道区具有拉伸应力，而P型信道晶体管的信道区具有压缩应力，整合两者于同一芯片，以提升组件的操作速度。
本实用新型的主要特征之一是在于N型通道晶体管两侧的浅沟槽隔离区内顺应性形成一氮化物衬垫层，用以阻挡后续填充于浅沟槽隔离区的氧化物扩散，以避免隔离氧化物体积膨胀，并且氮化物衬垫层本身可提供N型晶体管的半导体基底通道区形成一拉伸应力。另外，将P型通道晶体管两侧的浅沟槽隔离区内的氮化物衬垫层施以离子布植，以造成氮化物衬垫层内的缺陷形成，有利于后续填充于浅沟槽隔离区的氧化物扩散，以于P型晶体管的半导体基底通道区形成一压缩应力。
为获致上述的目的，本实用新型提出一种具应变通道的互补式金氧半导体，主要是包括：一半导体基底、设置于上述半导体基底内的多个沟槽隔离区、一氮化物衬垫层、一离子布植氮化物衬垫层、一N型通道晶体管以及一P型通道晶体管。其中，相邻两上述沟槽隔离区之间各定义出一主动区，上述主动区包括一N型主动区与一P型主动区。另外，上述氮化物衬垫层，顺应性设置于上述N型主动区两侧的上述沟槽隔离区与上述半导体基底之间。再者，上述离子布植氮化物衬垫层，顺应性设置于上述P型主动区两侧的上述沟槽隔离区与上述半导体基底之间。并且，上述N型通道晶体管，设置于上述N型主动区上方。以及，上述P型通道晶体管，设置于上述P型主动区上方。
如前所述，上述半导体基底包括：一硅基底、堆栈的一硅层与一硅锗层或堆栈的一第一硅基底、一埋入绝缘层与一第二硅基底。
如前所述，上述沟槽隔离区的厚度大体为2000-6000。
如前所述，上述沟槽隔离区是由一氧化物所构成。
如前所述，本实用新型的结构更包括：一氧化物衬垫层，顺应性设置于上述氮化物衬垫层与上述半导体基底之间。
如前所述，本实用新型的结构更包括：一氧化物衬垫层，顺应性设置于上述离子布植氮化物衬垫层与上述半导体基底之间。
如前所述，上述氮化物衬垫层是由氮化硅所构成，而上述离子布植氮化物衬垫层是由被施以离子布植的氮化硅所构成。
如前所述，上述离子布植氮化物衬垫层所被施加的离子包括：硅(Si)离子、氮(N)离子、氦(He)离子、氖(Ne)离子、氩(Ar)、氙(Xe)或锗离子。
根据本实用新型，上述N型主动区的上述半导体基底表层具有一拉伸应变通道区。上述拉伸应变通道区的拉伸应变量大体为0.1％-2％。
根据本实用新型，上述P型主动区的上述半导体基底表层具有一压缩应变通道区。上述压缩应变通道区的拉伸应变量大体为0.1％-2％。
如前所述，形成上述N型通道晶体管与上述P型通道晶体管之后更包括：分别形成一应力膜，覆盖于上述N型通道晶体管与上述P型通道晶体管表面。上述应力膜是由化学气相沉积法(chemical vapor deposition；CVD)所形成。
附图说明
图1是显示根据本实用新型的具应变通道的互补式金氧半导体的一较佳实施例的制程剖面图；
图2是显示根据本实用新型的具应变通道的互补式金氧半导体的另一较佳实施例的制程剖面图；
符号说明：
100、200、300-半导体基底
102、202、302-图案化罩幕层
104a、104b、204a、204b、304a、304b-沟槽隔离区
106、206、306-氧化物衬垫层
108、208、308-氮化物衬垫层
108a-离子布植氮化物衬垫层
112、212、312-隔离氧化物
117、217、317-N型通道晶体管
116、216、316-P型通道晶体管
S100-离子布植程序
114、214、314-栅极介电层
115、215、315-栅极层
118、218、318-间隙壁
122、120、220、222、320、322-应力膜
210、311-罩幕层
S100-形成氮化物衬垫层程序
具体实施方式
实施例1：
以下请参照图1，说明根据本实用新型的具应变通道的互补式金氧半导体的一较佳实施例。
其主要是包括：一半导体基底100、多个沟槽隔离区104a、104b、一氮化物衬垫层108、一离子布植氮化物衬垫层108a、一N型通道晶体管117以及一P型通道晶体管116。
其中，沟槽隔离区104a、104b设置于半导体基底100内，且相邻两沟槽隔离区104a、104b之间各定义出一主动区，而主动区包括一N型主动区(n-井)与一P型主动区(p-井)。沟槽隔离区104a、104b内填满隔离氧化物112。
另外，氮化物衬垫层108顺应性设置于N型主动区(n-井)两侧的沟槽隔离区104b与半导体基底100之间。氮化物衬垫层108的设置为本实用新型的特征之一。氮化物衬垫层108可用以阻挡后续填充于浅沟槽隔离区的氧化物112扩散，进而避免隔离氧化物112体积膨胀，并且氮化物衬垫层本身具有拉伸应力(intrinsic tensile stress)，导致对沟槽104b的侧壁施加一垂直压缩应力(vertical compressive stress)以及可提供N型晶体管117的半导体基底100通道区形成一拉伸应力。
再者，离子布植氮化物衬垫层108a顺应性设置于P型主动区(p-井)两侧的沟槽隔离区104a与半导体基底100之间。离子布植氮化物衬垫层108a内具有缺陷，有利于后续填充于浅沟槽隔离区的氧化物扩散，造成体积膨胀，以于P型晶体管116的半导体基底100通道区形成一压缩应力。
并且，N型通道晶体管117设置于N型主动区(n-井)上方。以及，P型通道晶体管116，设置于P型主动区(p-井)上方。如此一来，N型信道晶体管117下方的信道区具有一拉伸应力，可提升电子迁移率。P型信道晶体管116下方的信道区具有一压缩应力，可提升电洞迁移率。
实施例2：
以下请参照图2，说明根据本实用新型的具应变通道的互补式金氧半导体的一较佳实施例。
其主要是包括：一半导体基底200、多个沟槽隔离区204a、204b、一氮化物衬垫层208、一N型通道晶体管217以及一P型通道晶体管216。
其中，沟槽隔离区204a、204b设置于半导体基底200内，且相邻两沟槽隔离区204a、204b之间各定义出一主动区，而主动区包括一N型主动区(n-井)与一P型主动区(p-井)。沟槽隔离区204a、204b内填满隔离氧化物212。
另外，氮化物衬垫层208顺应性设置于N型主动区(n-井)两侧的沟槽隔离区204b与半导体基底200之间。氮化物衬垫层208的设置为本实用新型的特征之一。氮化物衬垫层208可用以阻挡后续填充于浅沟槽隔离区的氧化物212扩散，进而避免隔离氧化物212体积膨胀，并且氮化物衬垫层208本身具有拉伸应力(intrinsic tensile stress)，导致对沟槽204b的侧壁施加一垂直压缩应力(vertical compressive stress)以及可提供N型晶体管217的半导体基底200通道区形成一拉伸应力。
然而，沟槽204a内并无氮化物衬垫层，后续填充于浅沟槽隔离区的氧化物会发生扩散，造成体积膨胀，以于P型晶体管216的半导体基底200通道区形成一压缩应力。
并且，N型通道晶体管217设置于N型主动区(n-井)上方。以及，P型通道晶体管216，设置于P型主动区(p-井)上方。如此一来，N型信道晶体管217下方的信道区具有一拉伸应力，可提升电子迁移率。P型信道晶体管216下方的信道区具有一压缩应力，可提升电洞迁移率。
实用新型优点：
1.根据本实用新型的N型通道晶体管具有拉伸应力而P型通道晶体管具有压缩应力，因此可同时提升N型信道的电子迁移率以及P型通道的电洞迁移率，有效提升组件操作速度。
2.根据本实用新型的互补式金氧半晶体管(CMOS)，以简单的制成方式整合N型信道晶体管与P型信道晶体管于同一芯片，分别有适当可提升操作速度的应力。

Claims (13)

1.一种具应变通道的互补式金氧半导体，其特征在于所述互补式金氧半导体包括：
一半导体基底；
多个沟槽隔离区，设置于上述半导体基底内，使得相邻两上述沟槽隔离区之间各定义出一主动区，其中上述主动区包括一N型主动区与一P型主动区；
一氮化物衬垫层，顺应性设置于上述N型主动区两侧的上述沟槽隔离区与上述半导体基底之间；
一N型通道晶体管，设置于上述N型主动区上方；以及
一P型通道晶体管，设置于上述P型主动区上方。
2.根据权利要求1所述的具应变通道的互补式金氧半导体，其特征在于更包括：一氧化物衬垫层，顺应性设置于上述氮化物衬垫层与上述半导体基底之间。
3.根据权利要求1所述的具应变通道的互补式金氧半导体，其特征在于：上述N型主动区的上述半导体基底表层具有一拉伸应变通道区。
4.根据权利要求3所述的具应变通道的互补式金氧半导体，其特征在于：上述拉伸应变通道区的拉伸应变量为0.1％-2％。
5.根据权利要求1所述的具应变通道的互补式金氧半导体，其特征在于：上述P型主动区的上述半导体基底表层具有一压缩应变通道区。
6.根据权利要求5所述的具应变通道的互补式金氧半导体，其特征在于：上述拉伸应变通道区的拉伸应变量为0.1％-2％。
7.根据权利要求1所述的具应变通道的互补式金氧半导体，其特征在于，还包括：
一离子布植氮化物衬垫层，顺应性设置于上述P型主动区两侧的上述沟槽隔离区与上述半导体基底之间。
8.根据权利要求7所述的具应变通道的互补式金氧半导体，其特征在于更包括：一氧化物衬垫层，顺应性设置于上述氮化物衬垫层与上述半导体基底之间。
9.根据权利要求7所述的具应变通道的互补式金氧半导体，其特征在于更包括：一氧化物衬垫层，顺应性设置于上述离子布植氮化物衬垫层与上述半导体基底之间。
10.根据权利要求7所述的具应变通道的互补式金氧半导体，其特征在于：上述N型主动区的上述半导体基底表层具有一拉伸应变通道区。
11.根据权利要求7所述的具应变通道的互补式金氧半导体，其特征在于：上述拉伸应变通道区的拉伸应变量为0.1％-2％。
12.根据权利要求7所述的具应变通道的互补式金氧半导体，其特征在于：上述P型主动区的上述半导体基底表层具有一压缩应变通道区。
13.根据权利要求7所述的具应变通道的互补式金氧半导体，其特征在于：上述压缩应变通道区的拉伸应变量为0.1％-2％。
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Families Citing this family (145)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6657276B1 (en) * 2001-12-10 2003-12-02 Advanced Micro Devices, Inc. Shallow trench isolation (STI) region with high-K liner and method of formation
US20050285140A1 (en) * 2004-06-23 2005-12-29 Chih-Hsin Ko Isolation structure for strained channel transistors
US7081395B2 (en) * 2003-05-23 2006-07-25 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon strain engineering accomplished via use of specific shallow trench isolation fill materials
US6887798B2 (en) * 2003-05-30 2005-05-03 International Business Machines Corporation STI stress modification by nitrogen plasma treatment for improving performance in small width devices
US6905941B2 (en) * 2003-06-02 2005-06-14 International Business Machines Corporation Structure and method to fabricate ultra-thin Si channel devices
KR100517559B1 (ko) * 2003-06-27 2005-09-28 삼성전자주식회사 핀 전계효과 트랜지스터 및 그의 핀 형성방법
US7714384B2 (en) * 2003-09-15 2010-05-11 Seliskar John J Castellated gate MOSFET device capable of fully-depleted operation
US8008724B2 (en) * 2003-10-30 2011-08-30 International Business Machines Corporation Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers
JP4046069B2 (ja) * 2003-11-17 2008-02-13 ソニー株式会社 固体撮像素子及び固体撮像素子の製造方法
US7247534B2 (en) 2003-11-19 2007-07-24 International Business Machines Corporation Silicon device on Si:C-OI and SGOI and method of manufacture
US7737014B2 (en) * 2003-12-08 2010-06-15 International Business Machines Corporation Reduction of boron diffusivity in pFETs
JP4441488B2 (ja) * 2003-12-25 2010-03-31 富士通マイクロエレクトロニクス株式会社 半導体装置および半導体集積回路装置
US7285829B2 (en) * 2004-03-31 2007-10-23 Intel Corporation Semiconductor device having a laterally modulated gate workfunction and method of fabrication
US7101765B2 (en) * 2004-03-31 2006-09-05 Intel Corporation Enhancing strained device performance by use of multi narrow section layout
DE102004020834B4 (de) * 2004-04-28 2010-07-15 Qimonda Ag Herstellungsverfahren für eine Halbleiterstruktur
US7528051B2 (en) * 2004-05-14 2009-05-05 Applied Materials, Inc. Method of inducing stresses in the channel region of a transistor
DE102005005327A1 (de) * 2004-05-17 2005-12-15 Infineon Technologies Ag Feldefekttansistor, Transistoranordnung sowie Verfahren zur Herstellung eines halbleitenden einkristallinen Substrats und einer Transistoranordnung
US20050266632A1 (en) * 2004-05-26 2005-12-01 Yun-Hsiu Chen Integrated circuit with strained and non-strained transistors, and method of forming thereof
GB0411971D0 (en) * 2004-05-28 2004-06-30 Koninkl Philips Electronics Nv Semiconductor device and method for manufacture
JP4102334B2 (ja) * 2004-06-16 2008-06-18 株式会社東芝 半導体装置及びその製造方法
US7160782B2 (en) * 2004-06-17 2007-01-09 Texas Instruments Incorporated Method of manufacture for a trench isolation structure having an implanted buffer layer
JP4813778B2 (ja) * 2004-06-30 2011-11-09 富士通セミコンダクター株式会社 半導体装置
US7186622B2 (en) * 2004-07-15 2007-03-06 Infineon Technologies Ag Formation of active area using semiconductor growth process without STI integration
JP2006049413A (ja) * 2004-08-02 2006-02-16 Fujitsu Ltd 半導体装置及びその製造方法
US8158488B2 (en) * 2004-08-31 2012-04-17 Micron Technology, Inc. Method of increasing deposition rate of silicon dioxide on a catalyst
WO2006030505A1 (ja) * 2004-09-16 2006-03-23 Fujitsu Limited Ｍｏｓ型電界効果トランジスタ及びその製造方法
JP2008518476A (ja) * 2004-10-29 2008-05-29 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 異なるように歪ませた歪みチャネル領域を有する半導体領域を含む、半導体デバイスおよびその製造方法
DE102004053307B4 (de) * 2004-11-04 2010-01-07 Siltronic Ag Mehrschichtenstruktur umfassend ein Substrat und eine darauf heteroepitaktisch abgeschiedene Schicht aus Silicium und Germanium und ein Verfahren zu deren Herstellung
US7190036B2 (en) * 2004-12-03 2007-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor mobility improvement by adjusting stress in shallow trench isolation
JP2006165335A (ja) * 2004-12-08 2006-06-22 Toshiba Corp 半導体装置
US7494852B2 (en) * 2005-01-06 2009-02-24 International Business Machines Corporation Method for creating a Ge-rich semiconductor material for high-performance CMOS circuits
US7465972B2 (en) 2005-01-21 2008-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. High performance CMOS device design
US7701034B2 (en) * 2005-01-21 2010-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy patterns in integrated circuit fabrication
US7429775B1 (en) 2005-03-31 2008-09-30 Xilinx, Inc. Method of fabricating strain-silicon CMOS
US7238990B2 (en) * 2005-04-06 2007-07-03 Freescale Semiconductor, Inc. Interlayer dielectric under stress for an integrated circuit
US20060244074A1 (en) * 2005-04-29 2006-11-02 Chien-Hao Chen Hybrid-strained sidewall spacer for CMOS process
US7232730B2 (en) * 2005-04-29 2007-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a locally strained transistor
US7262484B2 (en) * 2005-05-09 2007-08-28 International Business Machines Corporation Structure and method for performance improvement in vertical bipolar transistors
KR100688547B1 (ko) * 2005-05-18 2007-03-02 삼성전자주식회사 Ｓｔｉ 구조를 가지는 반도체 소자 및 그 제조 방법
US7423283B1 (en) * 2005-06-07 2008-09-09 Xilinx, Inc. Strain-silicon CMOS using etch-stop layer and method of manufacture
US7037856B1 (en) * 2005-06-10 2006-05-02 Sharp Laboratories Of America, Inc. Method of fabricating a low-defect strained epitaxial germanium film on silicon
US7858458B2 (en) * 2005-06-14 2010-12-28 Micron Technology, Inc. CMOS fabrication
US7528028B2 (en) * 2005-06-17 2009-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Super anneal for process induced strain modulation
KR100688555B1 (ko) * 2005-06-30 2007-03-02 삼성전자주식회사 Ｍｏｓ트랜지스터를 구비하는 반도체 소자 및 그 제조 방법
US20070010073A1 (en) * 2005-07-06 2007-01-11 Chien-Hao Chen Method of forming a MOS device having a strained channel region
US7586158B2 (en) * 2005-07-07 2009-09-08 Infineon Technologies Ag Piezoelectric stress liner for bulk and SOI
JP4664760B2 (ja) * 2005-07-12 2011-04-06 株式会社東芝 半導体装置およびその製造方法
US7488670B2 (en) * 2005-07-13 2009-02-10 Infineon Technologies Ag Direct channel stress
US7442618B2 (en) * 2005-07-16 2008-10-28 Chartered Semiconductor Manufacturing, Ltd Method to engineer etch profiles in Si substrate for advanced semiconductor devices
US7358551B2 (en) * 2005-07-21 2008-04-15 International Business Machines Corporation Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions
US7655991B1 (en) 2005-09-08 2010-02-02 Xilinx, Inc. CMOS device with stressed sidewall spacers
TWI267926B (en) * 2005-09-23 2006-12-01 Ind Tech Res Inst A new method for high mobility enhancement strained channel CMOS with single workfunction metal-gate
US7202513B1 (en) 2005-09-29 2007-04-10 International Business Machines Corporation Stress engineering using dual pad nitride with selective SOI device architecture
US7582947B2 (en) * 2005-10-05 2009-09-01 Taiwan Semiconductor Manufacturing Company, Ltd. High performance device design
US7936006B1 (en) 2005-10-06 2011-05-03 Xilinx, Inc. Semiconductor device with backfilled isolation
US7575975B2 (en) * 2005-10-31 2009-08-18 Freescale Semiconductor, Inc. Method for forming a planar and vertical semiconductor structure having a strained semiconductor layer
US7615806B2 (en) 2005-10-31 2009-11-10 Freescale Semiconductor, Inc. Method for forming a semiconductor structure and structure thereof
JP2007141912A (ja) * 2005-11-15 2007-06-07 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
DE102005063129B4 (de) * 2005-12-30 2010-09-16 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Halbleiterbauelements mit Isolationsgraben mit reduzierter Seitenwandverspannung
DE102005063108A1 (de) * 2005-12-30 2007-07-12 Advanced Micro Devices, Inc., Sunnyvale Technik zur Herstellung eines Isolationsgrabens als eine Spannungsquelle für die Verformungsverfahrenstechnik
DE102005063130B4 (de) * 2005-12-30 2017-07-27 Advanced Micro Devices, Inc. Verfahren zum Bilden einer Grabenisolationsstruktur mit unterschiedlicher Verspannung
US7518193B2 (en) 2006-01-10 2009-04-14 International Business Machines Corporation SRAM array and analog FET with dual-strain layers comprising relaxed regions
JP2007189110A (ja) * 2006-01-13 2007-07-26 Sharp Corp 半導体装置及びその製造方法
US20070164365A1 (en) * 2006-01-17 2007-07-19 Chan Joseph Y Single stress liner for migration stability and speed
US7678630B2 (en) * 2006-02-15 2010-03-16 Infineon Technologies Ag Strained semiconductor device and method of making same
US7544584B2 (en) 2006-02-16 2009-06-09 Micron Technology, Inc. Localized compressive strained semiconductor
JP2007220892A (ja) * 2006-02-16 2007-08-30 Toshiba Corp 半導体装置及びその製造方法
US8017472B2 (en) * 2006-02-17 2011-09-13 Infineon Technologies Ag CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof
US20070200196A1 (en) * 2006-02-24 2007-08-30 Lattice Semiconductor Corporation Shallow trench isolation (STI) devices and processes
US7323392B2 (en) * 2006-03-28 2008-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance transistor with a highly stressed channel
US7566605B2 (en) * 2006-03-31 2009-07-28 Intel Corporation Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
US20070267715A1 (en) * 2006-05-18 2007-11-22 Sunil Mehta Shallow trench isolation (STI) with trench liner of increased thickness
US7416989B1 (en) 2006-06-30 2008-08-26 Novellus Systems, Inc. Adsorption based material removal process
US7462916B2 (en) * 2006-07-19 2008-12-09 International Business Machines Corporation Semiconductor devices having torsional stresses
US7485544B2 (en) * 2006-08-02 2009-02-03 Micron Technology, Inc. Strained semiconductor, devices and systems and methods of formation
US7968960B2 (en) * 2006-08-18 2011-06-28 Micron Technology, Inc. Methods of forming strained semiconductor channels
US20080044967A1 (en) * 2006-08-19 2008-02-21 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system having strained transistor
WO2008042144A2 (en) * 2006-09-29 2008-04-10 Advanced Micro Devices, Inc. A semiconductor device comprising isolation trenches inducing different types of strain
DE102006046377A1 (de) * 2006-09-29 2008-04-03 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit Isoliergräben, die unterschiedliche Arten an Verformung hervorrufen
US7524777B2 (en) * 2006-12-14 2009-04-28 Texas Instruments Incorporated Method for manufacturing an isolation structure using an energy beam treatment
US7471548B2 (en) 2006-12-15 2008-12-30 International Business Machines Corporation Structure of static random access memory with stress engineering for stability
US7727856B2 (en) * 2006-12-24 2010-06-01 Chartered Semiconductor Manufacturing, Ltd. Selective STI stress relaxation through ion implantation
US7521763B2 (en) * 2007-01-03 2009-04-21 International Business Machines Corporation Dual stress STI
US8558278B2 (en) * 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
CN101271866B (zh) * 2007-03-22 2010-05-19 中芯国际集成电路制造(上海)有限公司 用于mos晶体管的隔离结构及其形成方法
KR100842749B1 (ko) * 2007-03-27 2008-07-01 주식회사 하이닉스반도체 반도체소자의 트렌치 소자분리막 형성방법
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
US8110890B2 (en) * 2007-06-05 2012-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating semiconductor device isolation structure
US7795119B2 (en) * 2007-07-17 2010-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Flash anneal for a PAI, NiSi process
US8440539B2 (en) * 2007-07-31 2013-05-14 Freescale Semiconductor, Inc. Isolation trench processing for strain control
KR20090016984A (ko) * 2007-08-13 2009-02-18 삼성전자주식회사 트렌치 소자분리 영역을 갖는 반도체소자 및 그 제조방법
US7652335B2 (en) * 2007-10-17 2010-01-26 Toshiba America Electronics Components, Inc. Reversely tapered contact structure compatible with dual stress liner process
KR20090050899A (ko) * 2007-11-16 2009-05-20 주식회사 동부하이텍 반도체 소자의 제조 방법
KR20090056015A (ko) * 2007-11-29 2009-06-03 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
KR100929720B1 (ko) * 2007-12-03 2009-12-03 주식회사 동부하이텍 반도체 소자의 소자 분리막 형성 방법
US9412758B2 (en) * 2007-12-10 2016-08-09 Newport Fab, Llc Semiconductor on insulator (SOI) structure with more predictable junction capacitance and method for fabrication
US8187486B1 (en) 2007-12-13 2012-05-29 Novellus Systems, Inc. Modulating etch selectivity and etch rate of silicon nitride thin films
US20090166757A1 (en) * 2007-12-27 2009-07-02 International Business Machines Corporation Stress engineering for sram stability
KR101446331B1 (ko) * 2008-02-13 2014-10-02 삼성전자주식회사 반도체 소자의 제조 방법
US9368410B2 (en) * 2008-02-19 2016-06-14 Globalfoundries Inc. Semiconductor devices having tensile and/or compressive stress and methods of manufacturing
US7943961B2 (en) * 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
US7981763B1 (en) * 2008-08-15 2011-07-19 Novellus Systems, Inc. Atomic layer removal for high aspect ratio gapfill
US7808051B2 (en) * 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
US20100193879A1 (en) * 2009-02-05 2010-08-05 Ming-Han Liao Isolation Region Implant and Structure
JP2010283256A (ja) * 2009-06-08 2010-12-16 Toshiba Corp 半導体装置およびｎａｎｄ型フラッシュメモリの製造方法
CN101630660B (zh) * 2009-07-07 2013-01-23 北京大学 提高cmos晶体管抗辐照的方法、cmos晶体管及集成电路
US8218353B1 (en) 2009-09-16 2012-07-10 Altera Corporation Memory element circuitry with stressed transistors
US8138791B1 (en) 2010-01-27 2012-03-20 Altera Corporation Stressed transistors with reduced leakage
US8293602B2 (en) * 2010-11-19 2012-10-23 Micron Technology, Inc. Method of fabricating a finFET having cross-hair cells
US8609508B2 (en) * 2010-12-08 2013-12-17 Stmicroelectronics, Inc. Method of fabricating an integrated circuit having a strain inducing hollow trench isolation region
FR2972564B1 (fr) * 2011-03-08 2016-11-04 S O I Tec Silicon On Insulator Tech Procédé de traitement d'une structure de type semi-conducteur sur isolant
US8697522B2 (en) 2011-07-05 2014-04-15 International Business Machines Corporation Bulk finFET with uniform height and bottom isolation
US9318370B2 (en) 2011-08-04 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. High-k dielectric liners in shallow trench isolations
JP5917861B2 (ja) 2011-08-30 2016-05-18 株式会社Ｓｃｒｅｅｎホールディングス 基板処理方法
FR2981792A1 (fr) * 2011-10-25 2013-04-26 St Microelectronics Crolles 2 Procede de fabrication de transistors a grille isolee
FR2981793A1 (fr) 2011-10-25 2013-04-26 St Microelectronics Crolles 2 Procede de fabrication de transistors a grille isolee
JP5944149B2 (ja) * 2011-12-05 2016-07-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8680576B2 (en) * 2012-05-16 2014-03-25 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device and method of forming the same
US8685816B2 (en) * 2012-06-11 2014-04-01 Globalfoundries Inc. Methods of forming semiconductor devices by forming semiconductor channel region materials prior to forming isolation structures
US9006080B2 (en) * 2013-03-12 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Varied STI liners for isolation structures in image sensing devices
US8962430B2 (en) 2013-05-31 2015-02-24 Stmicroelectronics, Inc. Method for the formation of a protective dual liner for a shallow trench isolation structure
US9419134B2 (en) 2014-01-13 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Strain enhancement for FinFETs
US9306067B2 (en) 2014-08-05 2016-04-05 Taiwan Semiconductor Manufacturing Company, Ltd. Nonplanar device and strain-generating channel dielectric
US9941406B2 (en) 2014-08-05 2018-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with source/drain cladding
CN105448914B (zh) * 2014-08-28 2019-12-03 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US20160079034A1 (en) * 2014-09-12 2016-03-17 Applied Materials Inc. Flowable film properties tuning using implantation
US9209301B1 (en) * 2014-09-18 2015-12-08 Soitec Method for fabricating semiconductor layers including transistor channels having different strain states, and related semiconductor layers
US9431268B2 (en) 2015-01-05 2016-08-30 Lam Research Corporation Isotropic atomic layer etch for silicon and germanium oxides
US9425041B2 (en) 2015-01-06 2016-08-23 Lam Research Corporation Isotropic atomic layer etch for silicon oxides using no activation
KR102320820B1 (ko) * 2015-02-24 2021-11-02 삼성전자주식회사 집적회로 소자 및 그 제조 방법
US9577101B2 (en) * 2015-03-13 2017-02-21 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain regions for fin field effect transistors and methods of forming same
CN104716083B (zh) * 2015-03-20 2018-06-26 上海华力集成电路制造有限公司 形成浅槽隔离的方法
KR102460718B1 (ko) * 2015-05-28 2022-10-31 삼성전자주식회사 집적회로 소자
KR20170065271A (ko) * 2015-12-03 2017-06-13 삼성전자주식회사 반도체 소자 및 그 제조 방법
US9847418B1 (en) * 2016-07-26 2017-12-19 Globalfoundries Inc. Methods of forming fin cut regions by oxidizing fin portions
US10699963B2 (en) * 2017-08-31 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure with isolation feature
WO2019226341A1 (en) 2018-05-25 2019-11-28 Lam Research Corporation Thermal atomic layer etch with rapid temperature cycling
US10483154B1 (en) * 2018-06-22 2019-11-19 Globalfoundries Inc. Front-end-of-line device structure and method of forming such a front-end-of-line device structure
WO2020014065A1 (en) 2018-07-09 2020-01-16 Lam Research Corporation Electron excitation atomic layer etch
US11101218B2 (en) * 2018-08-24 2021-08-24 Micron Technology, Inc. Integrated assemblies having metal-containing regions coupled with semiconductor regions
US11088022B2 (en) * 2018-09-27 2021-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Different isolation liners for different type FinFETs and associated isolation feature fabrication
CN109616446A (zh) * 2018-12-10 2019-04-12 德淮半导体有限公司 半导体装置的制造方法
US20220319909A1 (en) * 2021-04-01 2022-10-06 Nanya Technology Corporation Method for manufacturing a semiconductor memory device
TWI782553B (zh) * 2021-05-31 2022-11-01 力晶積成電子製造股份有限公司 半導體元件
US20230200238A1 (en) * 2021-12-17 2023-06-22 Texas Instruments Incorporated Embedded thermoelectric cooler using thermally anisotropic mesas for power device heat generating source temperature reduction

Family Cites Families (92)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US621131A (en) * 1899-03-14 Polishing-wheel
US4069094A (en) 1976-12-30 1978-01-17 Rca Corporation Method of manufacturing apertured aluminum oxide substrates
JPS551103A (en) * 1978-06-06 1980-01-07 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor resistor
US4314289A (en) * 1979-12-07 1982-02-02 International Business Machines Corporation Biased pulsed recording systems and methods
US4497683A (en) 1982-05-03 1985-02-05 At&T Bell Laboratories Process for producing dielectrically isolated silicon devices
JPH0644590B2 (ja) * 1984-10-15 1994-06-08 日本電気株式会社 半導体装置
US4631803A (en) * 1985-02-14 1986-12-30 Texas Instruments Incorporated Method of fabricating defect free trench isolation devices
US4892614A (en) 1986-07-07 1990-01-09 Texas Instruments Incorporated Integrated circuit isolation process
JPH0640583B2 (ja) 1987-07-16 1994-05-25 株式会社東芝 半導体装置の製造方法
US4946799A (en) * 1988-07-08 1990-08-07 Texas Instruments, Incorporated Process for making high performance silicon-on-insulator transistor with body node to source node connection
JPH02273956A (ja) * 1989-04-15 1990-11-08 Fujitsu Ltd 半導体装置及びその製造方法
JPH0394479A (ja) 1989-06-30 1991-04-19 Hitachi Ltd 感光性を有する半導体装置
US5222234A (en) * 1989-12-28 1993-06-22 International Business Machines Corp. Combining search criteria to form a single search and saving search results for additional searches in a document interchange system
US5155571A (en) 1990-08-06 1992-10-13 The Regents Of The University Of California Complementary field effect transistors having strained superlattice structure
JP3019430B2 (ja) 1991-01-21 2000-03-13 ソニー株式会社 半導体集積回路装置
US5338960A (en) 1992-08-05 1994-08-16 Harris Corporation Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures
US5461250A (en) * 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
US5273915A (en) 1992-10-05 1993-12-28 Motorola, Inc. Method for fabricating bipolar junction and MOS transistors on SOI
EP0655785B1 (en) 1993-11-30 2001-10-17 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device and its manufacturing method
JPH0846139A (ja) 1994-05-06 1996-02-16 Texas Instr Inc <Ti> ポリシリコン抵抗器とその作成法
US5534713A (en) 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5479033A (en) 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
US5447884A (en) * 1994-06-29 1995-09-05 International Business Machines Corporation Shallow trench isolation with thin nitride liner
US6433382B1 (en) 1995-04-06 2002-08-13 Motorola, Inc. Split-gate vertically oriented EEPROM device and process
US5629544A (en) * 1995-04-25 1997-05-13 International Business Machines Corporation Semiconductor diode with silicide films and trench isolation
US5708288A (en) 1995-11-02 1998-01-13 Motorola, Inc. Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method
TW335558B (en) 1996-09-03 1998-07-01 Ibm High temperature superconductivity in strained SiSiGe
US5789807A (en) 1996-10-15 1998-08-04 International Business Machines Corporation On-chip power distribution for improved decoupling
US5811857A (en) * 1996-10-22 1998-09-22 International Business Machines Corporation Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications
US5763315A (en) * 1997-01-28 1998-06-09 International Business Machines Corporation Shallow trench isolation with oxide-nitride/oxynitride liner
US5714777A (en) * 1997-02-19 1998-02-03 International Business Machines Corporation Si/SiGe vertical junction field effect transistor
JP4053647B2 (ja) 1997-02-27 2008-02-27 株式会社東芝 半導体記憶装置及びその製造方法
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
DE19720008A1 (de) 1997-05-13 1998-11-19 Siemens Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
JP3535527B2 (ja) * 1997-06-24 2004-06-07 マサチューセッツ インスティテュート オブ テクノロジー 傾斜ＧｅＳｉ層と平坦化を用いたゲルマニウム・オン・シリコンの貫通転位の制御
US6221709B1 (en) 1997-06-30 2001-04-24 Stmicroelectronics, Inc. Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor
EP0923116A1 (en) * 1997-12-12 1999-06-16 STMicroelectronics S.r.l. Process for manufacturing integrated multi-crystal silicon resistors in MOS technology and integrated MOS device comprising multi-crystal silicon resistors
US6100153A (en) 1998-01-20 2000-08-08 International Business Machines Corporation Reliable diffusion resistor and diffusion capacitor
JP3265569B2 (ja) * 1998-04-15 2002-03-11 日本電気株式会社 半導体装置及びその製造方法
US6558998B2 (en) * 1998-06-15 2003-05-06 Marc Belleville SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit
JP3403076B2 (ja) 1998-06-30 2003-05-06 株式会社東芝 半導体装置及びその製造方法
US6008095A (en) * 1998-08-07 1999-12-28 Advanced Micro Devices, Inc. Process for formation of isolation trenches with high-K gate dielectrics
US6387739B1 (en) * 1998-08-07 2002-05-14 International Business Machines Corporation Method and improved SOI body contact structure for transistors
US6015993A (en) * 1998-08-31 2000-01-18 International Business Machines Corporation Semiconductor diode with depleted polysilicon gate structure and method
JP2000132990A (ja) 1998-10-27 2000-05-12 Fujitsu Ltd 冗長判定回路、半導体記憶装置及び冗長判定方法
US6258664B1 (en) * 1999-02-16 2001-07-10 Micron Technology, Inc. Methods of forming silicon-comprising materials having roughened outer surfaces, and methods of forming capacitor constructions
US6358791B1 (en) * 1999-06-04 2002-03-19 International Business Machines Corporation Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby
US6362082B1 (en) 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6339232B1 (en) 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
US7391087B2 (en) * 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
US6255175B1 (en) 2000-01-07 2001-07-03 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with minimized parasitic Miller capacitance
TW503439B (en) * 2000-01-21 2002-09-21 United Microelectronics Corp Combination structure of passive element and logic circuit on silicon on insulator wafer
US6475838B1 (en) * 2000-03-14 2002-11-05 International Business Machines Corporation Methods for forming decoupling capacitors
US6281059B1 (en) 2000-05-11 2001-08-28 Worldwide Semiconductor Manufacturing Corp. Method of doing ESD protective device ion implant without additional photo mask
DE10025264A1 (de) 2000-05-22 2001-11-29 Max Planck Gesellschaft Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung
JP2001338988A (ja) 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
WO2001093338A1 (en) * 2000-05-26 2001-12-06 Amberwave Systems Corporation Buried channel strained silicon fet using an ion implanted doped layer
JP3843708B2 (ja) * 2000-07-14 2006-11-08 日本電気株式会社 半導体装置およびその製造方法ならびに薄膜コンデンサ
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
FR2812764B1 (fr) * 2000-08-02 2003-01-24 St Microelectronics Sa Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu
JP2002076287A (ja) * 2000-08-28 2002-03-15 Nec Kansai Ltd 半導体装置およびその製造方法
JP4044276B2 (ja) 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
JP2004523103A (ja) 2000-12-04 2004-07-29 アンバーウェーブ システムズ コーポレイション 歪みシリコン表面チャネルｍｏｓｆｅｔを用いるｃｍｏｓインバータ回路
US6414355B1 (en) * 2001-01-26 2002-07-02 Advanced Micro Devices, Inc. Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness
US6894324B2 (en) * 2001-02-15 2005-05-17 United Microelectronics Corp. Silicon-on-insulator diodes and ESD protection circuits
US6518610B2 (en) 2001-02-20 2003-02-11 Micron Technology, Inc. Rhodium-rich oxygen barriers
US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6593181B2 (en) * 2001-04-20 2003-07-15 International Business Machines Corporation Tailored insulator properties for devices
US6586311B2 (en) 2001-04-25 2003-07-01 Advanced Micro Devices, Inc. Salicide block for silicon-on-insulator (SOI) applications
JP2002329861A (ja) 2001-05-01 2002-11-15 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6952040B2 (en) * 2001-06-29 2005-10-04 Intel Corporation Transistor structure and method of fabrication
US6576526B2 (en) 2001-07-09 2003-06-10 Chartered Semiconductor Manufacturing Ltd. Darc layer for MIM process integration
WO2003017336A2 (en) 2001-08-13 2003-02-27 Amberwave Systems Corporation Dram trench capacitor and method of making the same
US6521952B1 (en) 2001-10-22 2003-02-18 United Microelectronics Corp. Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
JP4173658B2 (ja) * 2001-11-26 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US6657276B1 (en) * 2001-12-10 2003-12-02 Advanced Micro Devices, Inc. Shallow trench isolation (STI) region with high-K liner and method of formation
US6600170B1 (en) 2001-12-17 2003-07-29 Advanced Micro Devices, Inc. CMOS with strained silicon channel NMOS and silicon germanium channel PMOS
US6784101B1 (en) 2002-05-16 2004-08-31 Advanced Micro Devices Inc Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
WO2003105204A2 (en) * 2002-06-07 2003-12-18 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US6812103B2 (en) 2002-06-20 2004-11-02 Micron Technology, Inc. Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects
US6686247B1 (en) 2002-08-22 2004-02-03 Intel Corporation Self-aligned contacts to gates
JP4030383B2 (ja) 2002-08-26 2008-01-09 株式会社ルネサステクノロジ 半導体装置およびその製造方法
US6573172B1 (en) 2002-09-16 2003-06-03 Advanced Micro Devices, Inc. Methods for improving carrier mobility of PMOS and NMOS devices
US6720619B1 (en) 2002-12-13 2004-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices
US6919233B2 (en) 2002-12-31 2005-07-19 Texas Instruments Incorporated MIM capacitors and methods for fabricating same
US6921913B2 (en) 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US6794764B1 (en) 2003-03-05 2004-09-21 Advanced Micro Devices, Inc. Charge-trapping memory arrays resistant to damage from contact hole information
US6762448B1 (en) 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US6891192B2 (en) 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US6872610B1 (en) 2003-11-18 2005-03-29 Texas Instruments Incorporated Method for preventing polysilicon mushrooming during selective epitaxial processing

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