CN2751439Y - 隔离沟槽的结构 - Google Patents
隔离沟槽的结构 Download PDFInfo
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- CN2751439Y CN2751439Y CNU2004200772526U CN200420077252U CN2751439Y CN 2751439 Y CN2751439 Y CN 2751439Y CN U2004200772526 U CNU2004200772526 U CN U2004200772526U CN 200420077252 U CN200420077252 U CN 200420077252U CN 2751439 Y CN2751439 Y CN 2751439Y
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
一种半导体沟槽隔离结构含有一基底以及一沟槽形成其中。此沟槽中内衬有一含氮(nitrogen－containing)内衬层并以一介电材料填入其中。该含氮内衬层较佳与邻接沟槽的有源区上的组件(例如晶体管)接触。
Description
技术领域
本实用新型是有关于一种半导体组件，且特别有关于一种以含氮内衬层的隔离结构。
背景技术
对于集成电路，尤其是线宽0.25微米以下的集成电路，对作为与有源区隔绝的隔离技术而言，一般皆使用浅沟槽隔离(STI)制程。一现有的浅沟槽隔离结构如图1所示，其中一晶片100含有一基底110，其上有一隔离沟槽112形成于该基底110，该基底110一般是一硅基底。该隔离沟槽112一般是填入一介电材料，例如一氧化硅或其它氧化物，而将相邻的二个有源区116隔离之。
在形成隔离沟槽的过程中，隔离沟槽的侧壁114是可能因后续的制程步骤而发生氧化(oxidation)，其结果造成隔离沟槽硅基底的体积膨胀，因而引发相邻的二个有源区116上产生压缩应力(compressive stress)。造成压缩应力的原因为在一局限的空间内产生了体积膨胀。
为解决上述问题，许多于沟槽隔离结构中形成氮化物内衬层的方法已被提出。一般而言，这些方法是利用一氮化物内衬层以阻止或降低沟槽因后续充填介电材料，产生氧化并引发应力。例如美国专利号5447884Fahey et al已描述了一浅隔离沟槽使用一薄氮化物内衬层；美国专利号6461937Kim et al亦描述了形成一氮化硅层于沟槽隔离结构以解除应力；美国专利号6251746Hong et al叙述了于沟槽隔离区形成消除应力的氮化层；以及美国专利号6461937，6251746叙述了沉积氮化层于一典型的升温加热所形成的氧化硅层上。
当氮化物内衬层阻止了后续沟槽侧壁的氧化，其结果是降低了压缩应力。然而，一般形成的氮化物内衬层带有内应力；而且，由于此内应力而导致有源区于脆弱处形成缺陷(defects)甚或裂缝(cracks)，该脆弱处例如隔离沟槽顶部的一尖角处(sharp corners)。
此外，形成一氧化物内衬层于氮化物内衬层下面，以降低氮化物内衬层对于有源区的影响的诸多方法亦被提出，但使用了上述的氧化物内衬层却会有引发高热预算(thermal budget)的问题。
因此，业者需要一种隔离沟槽的改良方法，来阻止或降低此隔离沟槽侧壁的氧化效应。
发明内容
本实用新型的目的在于解决隔离沟槽的侧壁因后续的制程步骤而发生氧化(oxidat ion)，造成隔离沟槽硅基底的体积膨胀，引发相邻的二个有源区产生压缩应力(compressive stress)的问题。
本实用新型的另一目的在于解决因现有的氮化物内衬层本身带有内应力，而导致有源区易于脆弱处形成缺陷(defects)甚或裂缝(cracks)的问题。
为达上述目的，本实用新型提供一含氮内衬层的隔离沟槽结构，藉由一含氮内衬层及一介电材料填入该沟槽，以使该含氮内衬层以接触或近接(close proximity)的方式于该邻接隔离沟槽的有源区上形成，辅以在隔离沟槽顶部及底部处提供一圆角(round corner)以解决隔离沟槽的尖角处(sharpcorners)由于应力而形成一脆弱点。
附图说明
图1为一现有的隔离沟槽剖面图。
图2a～图2m为用于本实用新型的第一实施例中，形成隔离沟槽制程的一系列剖面图。
图3a～图3g为用于本实用新型的第二实施例中，形成隔离沟槽制程的一系列剖面图。
图4a～图4d为用于本实用新型的第三实施例中，形成隔离沟槽制程的一系列剖面图。
符号说明：
晶片～100、200、300、400；基底～110、210、310、410；隔离沟渠～112；隔离沟渠的侧壁～114；有源区～116；硬掩膜层～212层；掩膜层～312层；氧化层～214；氧化硅层～414；氮化层～216；掩膜图案～218；暴露的基底表面～219；隔离沟渠～220、314、412；含氮内衬层～222、316、416；沟渠填充材料～224、318、418；栅极电极～226、320、420；栅极介电层～228、322、422；源极～230、324、424；漏极～232、326、426；圆角径度～R；内层介电层(ILD)～234、328、428；金属联机～236、330、430。
具体实施方式
为让本实用新型的上述和其它目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合所附图式，作详细说明如下：
第一实施例：
首先，请参阅图2a，提供一晶片200具有一基底210，其上形成一硬掩膜212。该基底210可以是一硅或玻璃基底，较佳为硅基底。
该硬掩膜212较佳形成方式，由下而上是由一氧化层214及一氮化层216所组成。该氧化层214较佳为例如一二氧化硅层(SiO2)以例如氧化加热法(thermal oxidation)或化学气相沉积法(CVD)形成，该CVD法是藉由一四乙氧基硅烷(TEOS)及O2当先驱物质(precursor)以进行沉积。而沉积于该氧化层214上的氮化层216较佳为一氮化硅层(Si3N4)，该氮化硅层(Si3N4)是以例如化学气相沉积法(CVD)，利用硅烷(silane)及氨气当作先驱物质以进行沉积，沉积温度介于约550℃至900℃之间。一图案掩膜218，例如一光阻层掩膜，是以微影的方式形成于该硬掩膜212层上，用以定义欲去除的硬掩膜部分。
接下来，请参阅图2b，以该光阻层图案为掩膜，将未覆盖光阻层的硬掩膜212层部分蚀刻去除，而形成一暴露的基底表面219，以备后续的隔离沟槽制程。该蚀刻制程较佳为例如一非等向性干蚀刻，亦可以是一湿式等向性蚀刻制程。之后再将该图案掩膜218去除。
请参阅图2c，以硬掩膜212层作为一蚀刻掩膜，蚀刻该基底210以形成一沟槽，该沟槽的较佳深度约介于2000至6000埃之间，但其深度不在此限，可依不同的应用而变换深浅度。
之后，请参阅图2d，以一回缩制程(pull back)将一部分硬掩膜层212，包含氮化硅层(Si3N4)以及二氧化硅层(SiO2)蚀刻去除，而形成硬掩膜212层由隔离沟槽220边缘往后缩(retreat)些，该后缩量较佳为介于约10至50nm之间，但其后缩量不在此限，可依不同集成电路的设计而增减。此回缩制程(pullback)可例如为一湿式等向性蚀刻制程，于介于约100℃至180℃之间的温度，30至2000秒之间的蚀刻时间以热磷酸将氮化层216(Si3N4)蚀刻去除；之后再以另一种等向性湿蚀刻法，以例如稀释的氢氟酸于约介于10℃至40℃之间，约2至200秒间的蚀刻时间将氧化层214(SiO2)蚀刻去除。上述该回缩制程(pull back)亦可变换为先以非等向性干蚀刻方式进行，例如藉以一氟化学气体来蚀刻氮化层216，接着以一等向性湿蚀刻法，例如以稀释的氢氟酸于约10℃至40℃之间，约2至200秒间的蚀刻时间将氧化层214(SiO2)蚀刻去除。
后续，请参阅图2e，将该隔离沟槽施行一圆角化制程(corner roundingprocess)，较佳为一退火制程，其温度约介于700℃至1000℃之间，以促使沟槽尖角处的硅原子产生迁移(si1icon atom migration)。该退火制程可藉由置于一例如含氢、氮、氦、氖、氩、氙，及其组合气体所组成的族群的环境下，以约1至1000Torr之间的压力施行；该退火环境较佳为一含氢，于约1至1000Torr间的压力以及约700至950℃间的退火温度。一般而言，一高温低压的环境较可促使硅原子产生迁移而形成圆角(round corners)。俟圆角化制程一完成，圆角径度(如图2e示的“R”)较佳为介于约5至50nm之间。
接着，请参阅图2f，于隔离沟槽220及硬掩膜212层上形成一含氮内衬层222(nitrogen-containing liner)，较佳的形成方式为例如一熟知的化学气相沉积法(CVD)技艺。该含氮内衬层222例如为一氮化硅层、一氮氧化硅层(SiOxNy)或一氮掺杂(nitrogen-doped)的氧化硅材料，该含氮内衬层的氮原子百分比约为百分之5至百分之60间。
请参阅图2g，该含氮内衬层222的厚度(TN)较佳为介于约0.5至20nm之间，但并不在此限，其厚度可依照制程所需变薄或加厚。该含氮内衬层222较佳为含约-1至+2GPa间的内应力(intrinsic stress)，其中负值表示一压缩应力(compressive stress)，正值表示一伸张应力(tensile stress)。含氮内衬层222较佳为一具高伸张应力的顺应性沉积氮化层。
依照本实施例，该含氮内衬层222的内应力对于有源区的硅晶格(siliconlattice)的影响是可藉由一含氮内衬层222直接接触该沟槽侧壁而更加扩大。该含氮内衬层222并可避免沟槽侧壁于后续制程步骤的氧化。如上所述，因为该含氮内衬层222为一具高伸张应力的顺应性沉积氮化层，其施加了一显著的反向应力于该有源区的硅晶格上，而压制了因氧化而造成隔离沟槽硅基底的体积膨胀，引发相邻的二个有源区产生压缩应力的问题。此外，利用本实施例，亦避免了脆弱区的发生而不会产生潜在性例如裂隙或差排(dislocation)等缺陷。尖角处即是脆弱区的一例，其中应力会集中在该脆弱区而使该处产生缺陷。因此，较佳的方式为先形成圆角处于该沟槽的上部及底部，然后再形成含氮内衬层222。
后续，请参阅图2h，沉积一沟槽填充材料224填入该沟槽，该沟槽填充材料224为一介电材料，较佳为例如一氧化硅。该沟槽填充材料亦可以是一沟槽填充组合材料，例如以CVD法沉积的氧化硅及以CVD法沉积的多晶硅的组合材料。沉积之后，该沟槽填充材料可以藉由一于约800℃的氢氧燃烧氧化热退火(pyrogenic oxidation anneal)方式或现有的1000℃热退火制程以使该沟槽填充材料更致密化。
之后，施行一平坦化步骤于该沟槽填充材料表面，以使该沟槽填充材料的表面平坦之。该平坦化步骤例如是一现有的化学机械研磨(CMP)制程，该沟槽填充材料可因研磨而停留在含氮内衬层222或氮化硅层216的表面。
接下来，请参阅图2i，以一蚀刻制程将氮化硅层216上的含氮内衬层222及氮化硅层216去除，该蚀刻法例如先以一热磷酸，之后再以一稀释氢氟酸的等向性湿式蚀刻法。
之后，于图2j及图2k所示，再以一蚀刻制程将二氧化硅层214去除，该去除二氧化硅层214的方式较佳为以稀释的氢氟酸等向性湿式蚀刻法。
请参阅图21，于有源区上形成一晶体管。该晶体管包含一栅极电极226，一栅极介电层228，一源极230及一漏极232。当完成该晶体管后，沉积一内层介电层(ILD)234于该晶体管上。该有一平坦表面的内层介电层(ILD)234是包括一氧化硅层，以例如CVD法沉积形成。之后，形成一金属联机236于该平坦的内层介电层(ILD)234上。该金属联机236包含高导电金属例如铝、铜及钨。
之后，通常形成一接触插塞(contact plug)(未显示)，是至少与一源极230、漏极232与栅极电极226与金属联机236之间连接。例如可藉由沉积钨金属层并经回蚀(etch back)或化学机械研磨(CMP)制程以形成一钨金属接触插塞。
第二实施例：
首先，请参阅图3a，提供一晶片300具有一基底310，其上形成一掩膜312图案。该基底310例如是一硅或玻璃基底，但较佳为一硅基底。该掩膜312可包括一般的掩膜材料，例如二氧化硅，氮化硅，一氮化硅于一二氧化硅上的迭层、或光阻层，较佳为一光阻层。
接着，请参阅图3b，蚀刻该硅基底以形成一沟槽314，较佳为例如一非等向性干蚀刻方式，较佳的沟槽蚀刻深度约2000至6000埃。
后续，请参阅图3c，将该掩膜312去除以暴露出该有源区。去除该掩膜312可例如先以一热磷酸，之后再以一稀释氢氟酸的等向性湿式蚀刻法施行。
然后，请参阅图3d，如前述第一实施例所述(请参阅图2e)，将该隔离沟槽上部及底部的尖角施行一圆角化制程(corner rounding process)。
接着，于图3e中，将一含氮内衬层316及一沟槽填充材料318先后填入该沟槽。该含氮内衬层316例如是一氮化硅层、一氮氧化硅层(Si3N4)或一氮掺杂(nitrogen-doped)的氧化硅材料，该含氮内衬层的氮原子百分比较佳约介于百分之5至百分之60之间。形成方式为例如一化学气相沉积法(CVD)法、热氧化法(thermal oxidation)加上氮化(nitridation)法、或一氮化法。氮化法是藉由将沟槽暴露于一含氮的环境中，例如一含氮电浆(nitrogen-containing plasma)以引进氮原子而进行氮化制程。
请参阅图3f，藉由一高选择比的平坦化制程，一部分的沟槽填充材料318被去除而停留在有源区上的含氮内衬层表面。该高选择比的平坦化制程例如一CMP制程，其藉由一包括氧化铈(CeO2)的研磨浆(slurry)以施行研磨。之后，该有源区上的含氮内衬层藉由一蚀刻制程而去除，该蚀刻制程例如为一含氟酸溶液的等向性湿蚀刻制程，或为一产生电浆蚀刻的非等向性干蚀刻制程。
后续，请参阅图3g，于有源区上形成一晶体管。该晶体管包含一栅极电极320，一栅极介电层322，一源极324及一漏极326。当完成该晶体管后，沉积一内层介电层(ILD)328于该晶体管上。该有一平坦表面的内层介电层(ILD)328是包括一氧化硅层，以例如CVD法沉积形成。之后，形成一金属联机330于该平坦的内层介电层(ILD)328上。该金属联机330包含高导电金属例如铝、铜及钨。
第三实施例：
首先，请参阅图4a，提供一晶片400具有一基底410，其中形成一沟槽412。该形成沟槽的制程请参考如图3a至图3c所示。该基底410例如是一硅或玻璃基底，但较佳为一硅基底。此外，该沟槽412边角(corner)较佳是一圆角，例如图3d所示，或亦可为一非圆角，即使初始的材料即为圆角，最好之后仍进一步圆角化。之后，依序沉积一二氧化硅内衬层414、一含氮内衬层416及一沟渠填充材料418于该沟槽410上。形成一二氧化物内衬层414于氮化物内衬层416下面，其用意在于降低氮化物内衬层的内应力对于有源区的影响。形成该二氧化硅内衬层414可藉由例如一湿式或干式氧化法于约500℃至1000℃间的温度范围。之后，形成一含氮内衬层416于该二氧化硅内衬层414上，可藉由例如一CVD法或氮化法(nitridation)。当施行氮化法时，氮气将会被引入下面的氧化硅层。之后，再沉积沟槽填充材料418。
接着，请参阅图4b，施行一高选择比的平坦化制程以去除一部分的含氮内衬层416及沟槽填充材料418，而停留在该有源区上的含氮内衬层416上。该高选择比的平坦化制程例如一CMP制程，其藉由一包括氧化铈(CeO2)的研磨浆(s1urry)以施行研磨。之后，该有源区上的含氮内衬层藉由一蚀刻制程而去除，该蚀刻制程例如为一含氟酸溶液的等向性湿蚀刻制程，或为一电浆蚀刻的非等向性干蚀刻制程。
后续，请参阅图4c，部分覆盖住有源区上的二氧化硅内衬层414是藉由一蚀刻制程予以去除，例如一稀释的氢氟酸等向性湿式蚀刻法。
然后，请参阅图4d，于有源区上形成一晶体管。该晶体管包含一栅极电极420，一栅极介电层422，一源极424及一漏极426。当完成该晶体管后，沉积一内层介电层(ILD)428于该晶体管上。该有一平坦表面的内层介电层(ILD)428是包括一氧化硅层，以例如CVD法沉积形成。之后，形成一金属联机430于该平坦的内层介电层(ILD)428上。该金属联机430是包含高导电金属例如铝、铜及钨。
虽然本实用新型已以较佳实施例揭露如上，然其并非用以限定本实用新型，任何熟习此技艺者，在不脱离本实用新型的精神和范围内，当可作些许的更动与润饰，因此本实用新型的保护范围当视所附的权利要求范围所界定者为准。
Claims (13)
1.一种隔离沟槽的结构，其特征在于，包括：
一基底其上含有侧壁表面的一沟槽，该沟槽至少含有一上部及一底部的圆角处；
一含氮内衬层与上述沟槽中至少一上部及一底部的圆角处形成接触；以及
一沟槽填充材料于该沟槽内。
2.根据权利要求1所述的隔离沟槽的结构，其特征在于，该圆角的圆弧径度范围是介于5～50nm之间。
3.根据权利要求1所述的隔离沟槽的结构，其特征在于，该沟槽的深度范围为介于2000～6000埃之间。
4.根据权利要求1所述的隔离沟槽的结构，其特征在于，该含氮内衬层的厚度是介于5～200埃之间。
5.根据权利要求1所述的隔离沟槽的结构，其特征在于，该沟槽填充材料包括氧化硅或多晶硅。
6.根据权利要求1所述的隔离沟槽的结构，其特征在于，该含氮内衬层包括氮化硅层或氮氧化硅层。
7.根据权利要求1所述的隔离沟槽的结构，其特征在于，该含氮内衬层的氮含量范围为介于百分之5～60之间。
8.一种隔离沟槽的结构，其特征在于，包括：
一半导体基底其上含有侧壁表面的一沟槽；
一含氮内衬层与上述沟槽侧壁表面形成接触；
一沟渠填充材料于该沟槽内；
一半导体基底中的一有源区，该有源区上至少形成一晶体管组件；
一内层介电层于该半导体基底上；
一金属联机于该内层介电层上；以及
一导电接触插塞连接该金属联机与有源区。
9.根据权利要求8所述的隔离沟槽的结构，其特征在于，该沟槽的深度范围为介于2000～6000埃之间。
10.根据权利要求8所述的隔离沟槽的结构，其特征在于，该含氮内衬层的厚度是介于5～200埃之间。
11.根据权利要求8所述的隔离沟槽的结构，其特征在于，该沟槽填充材料包括氧化硅或多晶硅。
12.根据权利要求8所述的隔离沟槽的结构，其特征在于，该含氮内衬层包括氮化硅层或氮氧化硅层。
13.根据权利要求8所述的隔离沟槽的结构，其特征在于，该含氮内衬层的氮含量范围为介于百分之5～60之间。
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2003
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- 2004-02-19 SG SG200400779A patent/SG120145A1/en unknown
- 2004-02-24 TW TW093104556A patent/TWI239050B/zh not_active IP Right Cessation
- 2004-08-12 CN CN200410055181.4A patent/CN1591817A/zh active Pending
- 2004-08-12 CN CNU2004200772526U patent/CN2751439Y/zh not_active Expired - Lifetime
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- 2005-06-07 US US11/146,661 patent/US20050224907A1/en not_active Abandoned
Also Published As
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|---|---|
| TWI239050B (en) | 2005-09-01 |
| TW200507098A (en) | 2005-02-16 |
| US6974755B2 (en) | 2005-12-13 |
| CN1591817A (zh) | 2005-03-09 |
| US20050224907A1 (en) | 2005-10-13 |
| SG120145A1 (en) | 2006-03-28 |
| US20050035426A1 (en) | 2005-02-17 |
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