CN2751438Y - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN2751438Y
CN2751438Y CNU2004201122169U CN200420112216U CN2751438Y CN 2751438 Y CN2751438 Y CN 2751438Y CN U2004201122169 U CNU2004201122169 U CN U2004201122169U CN 200420112216 U CN200420112216 U CN 200420112216U CN 2751438 Y CN2751438 Y CN 2751438Y
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groove
layer
epitaxial loayer
ground floor
semiconductor device
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葛崇祜
李文钦
胡正明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种半导体装置，包括：一基底、一第一外延层、一第二外延层、一第三外延层、一第一沟槽与一第二沟槽。该第一外延层位于该基底上且与该基底晶格不相称。该第二外延层位于该第一外延层上且与该第一外延层晶格不相称。该第三外延层位于该第二外延层上且与该第二外延层晶格不相称，因此，该第三层可为应变硅。该第一沟槽延伸过该第一外延层。该第二沟槽延伸过该第三外延层且至少部分延伸过该第二外延层，至少部分该第二沟槽与至少部分该第一沟槽对准，以及该第二沟槽至少部分填入一绝缘材料。

Description

半导体装置
技术领域
本实用新型是有关于一种半导体装置的制造，且特别有关于一种应变硅结构。
背景技术
互补式金属氧化物半导体(Complementary Metal-Oxide-Semiconductor，简称CMOS)技术是目前用在制造超大规模集成电路(Ultra-Large ScaleIntegrated，简称ULSI)主要的半导体技术。在过去数十年中，金属氧化物半导体场效晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，简称MOSFET)的尺寸缩小，使速度效能、电路密度与每单位半导体芯片的功能成本提供了重大的改善。当CMOS组件成比例缩小到100nm以下范围时，面临到重大挑战。一个可额外改善CMOS晶体管效能的方法，就是利用应变引起带结构变形与迁移率增加以增加晶体管组件电流。在二维拉伸应力下，硅的电子与电洞迁移率提高可达成。提高电子与电洞迁移分别改善了N沟道与P沟道的驱动电流，在应变硅中，电子可经更小的电阻且流动快了70％，此可使芯片无须进一步藉晶体管尺寸缩小就快了35％。
如图1A所示，晶体管应变硅层的制造有许多设计，如利用缓冲层或复合多层结构于块体硅基底20上，应变硅基底技术常利用微米级厚度的硅锗(silicon germanium，SiGe)变形缓冲层22，一无应变硅锗层24覆盖变形缓冲层22，该无应变硅锗层24具有比硅较大的自然晶格常数，由于无应变结晶硅与无应变结晶硅锗具有不同的晶格常数，故为晶格不相称，因为硅薄层26的晶格被迫与无应变硅锗层24的晶格对齐，硅薄层26处于二维拉伸应力下磊晶地成长于无应变硅锗层24上，如图1B与图1C所示。再次参阅图1A，一晶体管28形成于硅层26上，此晶体管28包括一源极30、一漏极32与一栅极34，晶体管制造于应变硅层26上可增进电效能，又如图1A所示，晶体管28通常被一隔离区36所包围住(如浅沟隔离(Shallow Trench Isolation，简称STI)、硅的区域氧化(Local Oxidation of Silicon，简称LOCOS)、场氧化物(Field Oxide，简称FOX))。
变形硅锗缓冲层22与其下的硅基底20的晶格不相称，可能会造成分散的、三维的差排网状结构，促使穿越差排38的应变缓和滑移，产生在变形缓冲区22上的差排可能传送到晶片表面，造成缺陷密度至每平方公分104-105个缺陷的程度，如此高的缺陷密度可能使利用此基底来生产集成电路产生重大障碍，也会使变形区下方的差排产生交叉排线表面的粗糙，此表面粗糙会是一个重大的问题，它会使主动区的沟道迁移率下降，因此，需要一个方法来降低应变是基底结构的缺陷密度。
发明内容
上述的问题与需要可藉由本实用新型的实施例解决。本实用新型的目的在于降低应变是基底结构的缺陷密度，根据本实用新型的目的，提供一种半导体装置，包括一基底、依第一外延层、一第二外延层、一第三外延层、一第一沟槽与一第二沟槽。该第一外延层形成于该基底上，此第一层与此基底晶格不相称；该第二外延层形成于该第一层上，且此第二层与第一层晶格不相称；该第三外延层形成于该第二层上，且此第三层与第二层晶格不相称；该第一沟槽延伸过第一层；该第二沟槽延伸过第三层且至少部分穿过第二层；至少部分第二沟槽与至少部分第一沟槽对准，且第二沟槽至少部分填入一绝缘材料。
籍由本实用新型，可解决现有生产集成电路产生的重大障碍，也会使变形区下方的差排产生交叉排线表面的粗糙度降低，解决使主动区的沟道迁移率下降的问题，有效降低应变是基底结构的缺陷密度。
附图说明
图1A为一剖面图，用以说明习知形成于应变硅基底上的晶体管；
图1B与图1C说明在二维张力下形成一硅层的方法；
图2-图7说明本实用新型实施例1的形成步骤；以及
图8-图11说明本实用新型实施例2的形成步骤。
符号说明：
20、42～基底           22～变形缓冲层
24～无应变硅锗层       26～硅层
28～晶体管             30～源极
32～漏极               34～栅极
36～隔离区             40～第一层
44～第一沟槽          46～第一层与基底的界面
48～第一层的上表面    50～第二层
52～第二层材质填入第一沟槽中的部分
54～第二层的悬壁      56～第二层的上表面
60～第三层
62～第三层材质填入第一沟槽中的部分
64～第二沟槽          68～绝缘材料
72～第一层与第二层的界面
具体实施方式
为使本实用新型的上述和其它目的、特征和优点能更明显易懂，下文特举出较佳实施例，并配合所附图式，作详细说明如下：
图2-图11显示本实用新型两个实施例的流程步骤。本实用新型实施例提供一种降低缺陷密度来改善应变硅结构的方法，如与先前设计比较(请参阅图1A)，在本实用新型的实施例中，达成降成缺陷密度的主要机制之一就是为晶粒界面提供自由表面，使排差经由这些自由表面移除；藉由在远离沟道区处(晶体管将要存在的地方)策略性地设置这些自由表面，可使差排被移离沟道区(及朝向或至自由表面)，下列所述的两个实施例将说明本实用新型实施例如何提供此自由表面且降低沟道区的缺陷密度。
图2-图7显示一本实用新型实施例1的流程步骤，首先于图2中，第一晶格不相称外延层40形成在基底42上，在此例中，基底42为硅(即硅晶片)且第一层40为SiGe缓冲层，第一层40较佳为与基底42晶格不相称。
接下来如图3所示，第一沟槽44形成在第一层40中，在图3里，显示了第一沟槽44的两个部分，此第一沟槽44的平面可依主动区的布局而改变，而第一沟槽44的深度与宽度也可依需要做改变，在此例中(图3)，第一沟槽44延伸过第一层40且进入第一基底42中，较佳为第一沟槽44延伸过第一层40与基底42的界面46；在其它实施例中(未显示)，第一沟槽44可以只部分延伸过第一层40或延伸过第一层且未延伸到基底42。
在形成第一沟槽44后，第一层40可经退火处理，此退火温度比形成第一层40的沉积温度还要高约100℃，退火处理第一层40可移除在第一层40结晶结构的排差或缺陷，且/或可造成第一层40内部排差移到或向一自由表面(即第一沟槽44)；第一层40的上表面48可被平坦化(在形成第一沟槽44前或后)，而后于其上再形成第二层50(随后讨论)，此平坦化可利用任何合适的平坦化制程，如化学机械研磨(CMP)，若第一层40经退火处理，较佳在退火之后再行一平坦化，此平坦化也可在退火之前进行；在其它实施例中，第一层40的退火与/或第一层40的平坦化可不进行。
如图4所示，形成第二晶格不相称外延层50于第一层40上，此第二层50为一无应变的SiGe层；如图4所示，第二层50的材质可部分填入第一沟槽44中(请参阅图4中的52部分)；另外，第一沟槽44可先填入或部分填入其它材质(即绝缘材质)(未显示)，然后再于第一层40上形成第二层50；在此例中，虽然第一沟槽44在形成第二层50后依留有开口(请参阅图4)，且延伸向上过第二层50，但第一沟槽依44可能被第二层50所封闭，此情况端视任何于第一沟槽44中的第二层材料悬壁54的形成与第一沟槽44的宽度，在此情形下，第一沟槽44保留其开口较佳但非必须。
如同第一层40，第二层50可经退火处理，此退火温度可比形成第二层50的沉积温度还要高约100℃，退火处理第二层50可移除在第二层50结晶结构的排差或缺陷，且/或可造成第二层50内部排差移到或向一自由表面(即第一沟槽44)；第二层的上表面56在形成第三层60前(随后描述)可被平坦化；若第二层50经退火处理，最好在退火之后再行一平坦化，此平坦化也可在退火之前进行；在其它实施例中，第二层50的退火与/或第二层50的平坦化可不进行。
如图5所示，第三晶格不相称外延层60形成于第二层50上，第三层60由于受第二层50与第三层60的晶格不相称的影响，故为应变(处于二维张力)型态，在此例中，第三层60为处于二维张力下的应变硅(即请参阅第1C图)；如图5所示，第三层60的材料可部分填入第一沟槽44中(请参阅图5的62部分)，在此例中(请参阅图5)，虽然在形成第三层60后，但第一沟槽44依然留有开口，第一沟槽44依然可能被第三层60的形成所封闭，此情况端视任何于第一沟槽44中的第三层材料60悬壁的形成与第一沟槽44的宽度。
此第一与第二层40与50的厚度可分别约为2-3μm，而第三层60需够薄，如其厚度约为200埃，如此才不会于其中产生差排，若第三层60太厚，会因第二与三层50与60相异的晶格常数所造成的应力而产生裂缝或差排。如上所述，第一与第二层40与50可为SiGe层，在此例中，第二层50较佳具有比第一层40较高的锗浓度，以在彼此间形成一晶格不相称区，如第一层40可为变形SiGe层。第一(40)、第二(50)与第三(60)层可不相同且各可由任何材料或材料组成/化合物所形成，例如(但不限于)：硅、锗、碳、半导体化合物与其组成。
虽然第一与第二层40与50各为单层，但其一或两者也可为复合层(即由多层来组成一层)，例如，第一层40可包括一变形组成层与一单一组成层；类似地，如第二层50包括一变形组成层与一单一组成层。基底42在本实施例中为一硅晶片，另外也可为一硅位于绝缘体上(SOI)结构(未显示)，或硅基底42包括一覆盖硅层的绝缘层(未显示)。熟习此技艺的人士应可了解本实用新型的实施例亦可应用许多其它可能材料或/与层组成。
在形成第一层40、第二层50与第三层60层时，可利用任何外延层形成过程/技术(或其组成)，如包括(但不限于)：化学气相沉积(CVD)、MOCVD、HCVD、原子层沉积、应变硅分子束磊晶(SS-MBE)与上述的组合。
在图6中，第二沟槽64形成于第三与第二层60与50中，至少部分第二沟槽64与至少部分第一沟槽44对准(平行对准)，如图6所示，换句话说，第二沟槽64位于第一沟槽44上，然而，当第二沟槽64与第一沟槽44对准时，第二沟槽64并不需与第一沟槽44的中心一致；较佳为第二沟槽64与第一沟槽44对准且具有一深度，使第二沟槽64与第一沟槽44的开口连接。第二层的材质(即在第一沟槽44中的第二层50的悬壁部分54)是否会封闭住第二沟槽64底部的第一沟槽44，决于第二沟槽64在第二层50中的深度，如在一较佳的实施例中，第二沟槽64具有一约300埃的深度。
如图6所示的实施例，第二沟槽64延伸过第三层64且部分延伸过第二层50；在其它实施例里(未显示)，第二沟槽64可延伸过第二层50但未到第一层40；在另一实施例中(未显示)，第二沟槽64可延伸过第二层50且到第一层40，第二沟槽64的宽度最好比第一沟槽宽；在其它实施例中(未显示)，如第二沟槽64部分或全部的宽度可小于或等于第一沟槽44部分或全部的宽度，较佳为第二沟槽64的宽度与一般所使用的浅沟隔离(即请参阅图1A的STI 36)相等。
在图7中，第二沟槽64与部分未填满的第一沟槽44被填入一绝缘材料68，因此，被填满的第二沟槽64为一主动区的隔离区，也如图7所示，晶体管28形成，且部分晶体管28形成于第三层60上(即在此例中的应变硅层中)。
第一沟槽44提供一自由表面给差排，此可使缺陷移离晶体管28的沟道区，以消除或减少沟道区中的缺陷数目，如沟道区中的差排会产生漏电。第一沟槽44位于浅沟隔离(STI)区下方(即第二沟槽64)，使差排与/或缺陷移向浅沟隔离区下或中，由于浅沟隔离区中或下的缺陷一般并不会构成问题，且因它远离沟道区且一般并不会影响形成在主动区中组件的效能；再者，第一沟槽44越过第一与第二层40与50的接口72，此接口72的相对应力可降低或减少沟道区下的差排。
图8～图11显示本实用新型实施例2的流程步骤，图8～图11显示的实施例2与图2～图7所显示的实施例1类似，除第一沟槽44是在第二层50之后再形成(之前是在第二层50之前形成)外。首先在图8中，第一晶格不相称外延层40(即SiGe层)形成于基底42(即硅晶片)上，第二晶格不相称外延层50(即具有比第一层40高的Ge浓度的无应变的SiGe层)形成于第一层40上，第一层40可在第二层50于其上形成前经退火且/或平坦化处理(即
实施例1所述)。
如图9所示，第一沟槽44形成在第二与第一层50与40中；如图9所示的实施例，第一沟槽44较佳延伸过第二层50、第一层40且延伸到基底42中；在其它实施例中(未显示)，第一沟槽44可延伸过第二层50且到第一层40中(但未到基底42中)；在此例中，第一沟槽44可延伸部分或整个第一层40。第二层50可在第三层60于其上形成前经退火且/或平坦化处理(即如实施例1所述)。
在图10中，一第三晶格不相称外延层60(即硅)形成在第二层50上，第三层60因第二层50与第三层60间的晶格不相称故为应变型态，第三层材料62可部分填入第一沟槽中，如图10所示。在图11中，一第二沟槽64与第一沟槽44对准形成(如实施例1所述)，且第二沟槽64被填入一绝缘材质68而形成一绝缘区，此绝缘材料68也可填入第一沟槽44中其余开口处，如图11所示。第二沟槽64可延伸进部分或整个第二层50；在其它实施例中(未显示)，第二沟槽64可延伸、部分延伸到与/或完全延伸过第一层40。如同图7，图11说明一晶体管28利用一应变硅结构。
在本实用新型的其它实施例中(未显示)，即如在实施例1与/或实施例2的多样化与/或额外步骤中，一沟槽可在第一层40形成于基底42上前形成在基底42中，当第一层形成时，此沟槽是否填入第一层40的材质取决于此于基底42的沟槽的深与宽，此位于基底42的沟槽最好够深且/或够宽，在第一层形成后，此沟槽就可延伸过第一层40(不管第一层材料的悬壁或填入)，第二层50也是，如图4。此揭露的好处在于熟习此技艺的人士可了解在本实用新型的实施例中，有许多其它可能材料或/与层组成。
虽然本实用新型已以较佳实施例揭露如上，然其并非用以限定本实用新型，任何熟习此技艺者，在不脱离本实用新型的精神和范围内，当可作些许的更动与润饰，因此本实用新型的保护范围当视所附的权利要求范围所界定者为准。

Claims (11)

1.一种半导体装置，其特征在于，包括：
一基底；
一第一外延层位于上述基底上，该第一外延层相对于上述基底晶格不相称；
一第二外延层位于上述第一外延层上，该第二外延层相对于上述第一外延层晶格不相称；
一第三外延层位于上述第二外延层上，该第三外延层相对于上述第二外延层晶格不相称；
一第一沟槽延伸过上述第一外延层；以及
一第二沟槽延伸过上述第三外延层且至少部分延伸过上述第二外延层，至少部分该第二沟槽与至少部分上述第一沟槽对准，以及该第二沟槽至少部分填入一绝缘材料。
2.根据权利要求1所述的半导体装置，其特征在于，部分该第一沟槽延伸过至少部分该第二沟槽。
3.根据权利要求1所述的半导体装置，其特征在于，部分该第一沟槽延伸到该基底。
4.根据权利要求1所述的半导体装置，其特征在于，该第一沟槽至少部分填入该绝缘材料。
5.根据权利要求1所述的半导体装置，其特征在于，该第一沟槽至少部分填入该第二外延层的材料。
6.根据权利要求1所述的半导体装置，其特征在于，该第一沟槽至少部分填入该第三外延层的材料。
7.根据权利要求1所述的半导体装置，其特征在于，该基底为硅。
8.根据权利要求1所述的半导体装置，其特征在于，该第一外延层包括硅锗。
9.根据权利要求1所述的半导体装置，其特征在于，该第二外延层包括无应变的硅锗。
10.根据权利要求1所述的半导体装置，其特征在于，该第三外延层为应变硅。
11.根据权利要求1所述的半导体装置，其特征在于，尚包括：
一晶体管形成于该第二沟槽邻近处且至少部分位于该第三外延层中。
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US20050194658A1 (en) 2005-09-08
US20050093018A1 (en) 2005-05-05
US6902965B2 (en) 2005-06-07

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