CN2741189Y - 电容器 - Google Patents

电容器 Download PDF

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Publication number
CN2741189Y
CN2741189Y CN200420084320.1U CN200420084320U CN2741189Y CN 2741189 Y CN2741189 Y CN 2741189Y CN 200420084320 U CN200420084320 U CN 200420084320U CN 2741189 Y CN2741189 Y CN 2741189Y
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capacitor
capacitor according
bottom electrode
silicide
dielectric layer
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杨育佳
胡正明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805—Capacitors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/65—Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/905—Plural dram cells share common contact or common trench
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/908—Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

本实用新型是关于一种电容器，其结构包括：一绝缘层，覆盖于一基材上；一半导体层，覆盖于绝缘层上；一下电极，形成于部分的半导体层内；一电容介电层，覆盖于下电极上，其中电容介电层包含具有介电常数大于5的高介电常数介电材料；以及一上电极，覆盖于电容介电层上。

Description

电容器
技术领域
本实用新型是有关于一种半导体组件，且特别是有关于一种效能改善的电容器。
背景技术
于半导体集成电路芯片中，电源供应线路是用来供应电流以对集成电路中的主动及被动组件进行充/放电。例如，当时脉(clock)转换时，数字型CMOS电路将吸引电流。而于电路操作时，电源供应线路需供应相对高密度的瞬间电流，可能会导致于电源供应线路处的电压噪声(voltage noise)。当瞬间电流的扰动时间较短时或寄生电感/寄生电阻极大时，电源供应线路的电压将会有所扰动。
于当今电路应用技术中，集成电路的操作频率可为数百个百万赫兹至数个十亿赫兹。于如此的电路中的时脉讯号上升时间极短，所以电源供应线路中的电压扰动将非常大。于驱动电路的电源供应线路内此不期望的电压扰动将于内部讯号导致噪声并劣化了噪声限度。噪声限度的劣化将降低线路的可靠度，甚至将导致线路故障。
为降低电源供应线路内的电压扰动幅度，通常于不同电源供应线路间的端处或于电源供应线路与接地线路间的端处采用有滤波或去耦合电容器。于当需要预防电压供应的瞬间降低时，去耦合电容可作为电荷储存器的用以额外供应电流至电路处。
图1中显示了含有去耦合电容器的一电路图。电容器C1为安插于电源供应线路VDD及接地线路GND间的一去耦合电容器。于大部分芯片中采用不只一条电源供应线路，其可能具有接合于外部电路以用于输出电路的一不同电源供应线路OVDD。电容器C2则为安插于输出电源供应线路OVDD以及接地线路GND间的去耦合电容。电容器C3则为安插于电源供应线路VDD以及输出电压供应线路OVDD间的去耦合电容。上述去耦合电容通常尽可能设置于邻近瞬间电流源区或电流汲区的位置。
去耦合电容器通常应用于采用块状(bulk)基材或绝缘层上有硅层(silicon-on-insulator)基材的集成电路中。然而，去耦合电容器的角色于绝缘层上有硅层基材上的应用将较重要于其于块状基材上的应用。其理由在于，于块状基材上所制备的集成化芯片可因存在于经掺杂井区与块状基材间的固有空乏电容而自然地去耦合化电源供应电位以及接地电位。相较于块状基材，绝缘层上有硅层的芯片具有极少的芯片上电源供应线路与接地线路间的去耦合电容。
美国第6,558,998号专利中揭露了一种形成于绝缘层上有硅层基材上的去耦合电容。当电容器需形成于较大区域内或形成有有较大电容值时，此去耦合电容需共构于基材之内。如此，基材需视不同电路设计而加以定做。
发明内容
有鉴于此，本实用新型的主要目的就是揭露了一种具有高电容密度的电容器，其可作为去耦合电容之用而应用于集成电路芯片以适度降低其内电源供应线路内的电压扰动幅度。
为达上述目的，本实用新型提供了一种电容器，其结构包括：
一绝缘层，覆盖于一基材上；一半导体层，覆盖于绝缘层上；一下电极，形成于部分的半导体层内；一电容介电层，覆盖于下电极上，其中电容介电层包含具有介电常数大于5的高介电常数介电材料；以及一上电极，覆盖于电容介电层上。
由于本实用新型的电容器采用具有较高电容率的电容介电层，故所形成的电容器可具有较佳的电容密度，无论是作为集成电路芯片内的去耦合电容以降低其内电压扰动幅度用或仅作为一般用途的电容器，皆可较使用一般传统介电材料的电容器表现出较佳的组件表现。
附图说明
图1是显示习知去耦合电容的等效电路；
图2是显示本实用新型的一实施例中的剖面情形；
图3是显示本实用新型实施例中的电容器的俯视情形；
图4a以及图4b是显示本实用新型实施例中的电容器的剖面情形；
图5a以及图5b是显示本实用新型实施例中的电容器的剖面情形；
图6a～图6f是显示本实用新型实施例中的电容器于不同制程阶段中的剖面情形。
符号说明：
VDD～电源供应线路；
OVDD～输出电源供应线路；
C1、C2、C 3～电容器； GND～接地线路；
102～去耦合电容器；   104～半导体层；
106～绝缘层；         108～基材；
110～下电极；         112～电容介电层；
114～上电极；         116～晶体管；
118～源极区；         120～漏极区；
122～栅介电层；       124～栅电极；
126～主动区；         128～隔离区；
130、131～接触结构、接触插栓；
132～间隔物；         134、136～掺杂区；
138～层间介电层；     140～金属导线；
142～金属层间介电层； 144～蚀刻停止层；
148～掩膜层；         W～去耦合电容的宽度；
L～去耦合电容的长度。
具体实施方式
为了让本实用新型的上述和其它目的、特征、和优点能更明显易懂，下文特举一较佳实施例，并配合所附图示，作详细说明如下：
本实用新型实施例的剖面情形如图2所示。于本实施例中，去耦合电容器102是形成于一绝缘层上有半导体层(semiconductor on insulator)基材，例如为绝缘层上有硅层的基材，其包括位于绝缘层106上的半导体层，而绝缘层106则覆盖于基材108上。在此，基材108较佳为硅基材。去耦合电容器102则包括下电极110、覆盖于下电极110上的电容介电层112以及覆盖于电容介电层112上的上电极114。
下电极110较佳地形成于半导体层104内，例如为一硅层内。下电极110可经轻度掺杂且电性连结于高度掺杂区域(请参照图4b，在此并未图示)。另外，下电极110可为一高度掺杂区。于不同情形下，下电极110可掺杂有如砷或磷离子的N型掺质或掺杂如硼离子的P型掺质。
电容介电层112较佳地为一高电容率(即高介电常数)介电材料。藉由具有高介电常数介电材料的使用，电容介电层112的电容密度(εoεr/tphys)可明显地高于采用传统二氧化硅电容介电层的电容器，其中εo为自由空间的电容率，εr为相对电容率以及tphys为电容介电层的实际厚度(physical thickness)。当去耦合电容器102的尺寸维持与于下电极110及上电极112的长宽乘积相同时，使用高介电常数电容介电层将可改善整体电容值且因此减低于去耦合时于电源供应线路中的电压扰动。
上述高介电常数介电材料较佳具有大于5的相对电容率，相对电容率更佳地可大于10甚至20。上述高介电常数介电材料可择自于由氧化铝、氧化铪、氧化锆、氮氧化铪、硅酸铪、硅酸锆、氧化镧及其组合所组成族群中。上述高介电常数介电材料较佳地为氧化铪。
电容介电层112的氧化硅等效厚度(EOT，equivalent silicon oxidethichness)较佳地少于100埃，更佳地少于50埃，甚至少于10埃。电容介电层112的实际厚度可少于100埃，较佳地少于50埃，甚至少于10埃。
上电极114可由如多晶硅、多晶硅锗、金属、金属氮化物、金属硅化物或金属氧化物或上述材料的组合等导电材料所组成。如钼、钨、钛、钽、铂及铪等金属材料可形成于一部分的上电极上。金属氮化物则可能包括如氮化钼、氮化钨、氮化钛、氮化钽等材质，但不局限于上述材质。金属硅化物则可能包括如硅化镍、硅化钴、硅化钨、硅化钛、硅化钽、硅化铂、硅化铒等材质，但不局限于上述材质。金属氧化物则可能包括如化钌、氧化铟锡等材质，但不局限于上述材质。
如图2所示，去耦合电容器可以晶体管116的主动组件型式形成于邻近的主动区内。晶体管116包括于如硅层的半导体层104内的源极区118及漏极区120、栅介电层122以与栅电极124。栅介电层112较佳地与电容介电层112形成于同一膜层中，而栅电极124较佳地与上电极114形成于同一膜层中。事实上，如下文中所讨论，晶体管116及去耦合电容器102较佳地为同时形成。
图2中亦图示了一第三主动区126。其内无显示有任何组件的存在，但实际上仍可于其内形成有如晶体管或二极管、电阻等其它组件。于实际情形中，半导体芯片上通常形成有多种不同类型的组件。而于某些情况中，于单一主动区内将会形成有复数个组件或仅形成有单一组件。
在此，主动区126藉由隔离区128与含有电容器102以及含有晶体管116的两主动区所隔绝。于本实施例中，其是以浅沟槽隔离(STI)方式达成。此时，介于上述主动区间的沟槽中填入有如氧化硅的绝缘物。其内所填入的绝缘物较佳地为化学气相沉积法所形成的氧化硅。于此浅沟槽隔离结构的边界上亦可形成有氧化衬层，但于此不加以显示以简化图示。此氧化衬层可含或不含氮原子。此外，亦可采用如台地隔离法(mesa isolation)的其它隔离技术。如此，于主动区内形成组件时，上述沟槽内将留空而无填充。
图3是显示本实施例的电容器102的俯视情形。电容器102具有一宽W以及一长L。宽W的尺寸较佳地可大于5微米，且更较佳地大于10微米。长L的尺寸则较佳地可大于1微米，且更较佳地大于5微米。电容器102的详细结构可分别参照图4a、图4b所显示的沿其A～A’线段及沿其B～B’线段内的剖面情形。而接触结构130的剖面情形则请参照图5a、图5b。
如图4a所示的沿A～A’线段剖面情形中，上电极114横向地延伸并覆盖于隔离区128上。于图4a中所图示的上电极114具有一厚度t，其厚度较佳地介于200～2000埃。电容器102的结构中可于上电极114侧边上附加地形成有间隔物132。通常，间隔物132是于晶体管116(详见图2)的制备时所形成。然而，间隔物132并非必要的结构。
如图4b所示的沿B～B’线段剖面情形中，下电极112可电性连结于邻近的掺杂区134以及136。其中可能不只包含有一掺杂区134(及136)。当下电极110未经高度掺杂(heavily doped)时，于下电极110中可能形成有一反转层(inversion layer)。此反转层可藉由邻近掺杂区内所供应的移动载子而形成，以及当上电极114与下电极110间存在有实质上偏压时产生。此实质偏压可为介于VDD以及GND的电位、介于OVDD以及GND的电位或介于OVDD以及VDD间的电位。
下电极110可掺杂形成相同于接触区134及136的同种导电性。如此，掺杂于如硅层的一半导体层104内的掺质有相同于掺杂于下电极110以及掺杂区134及136内的导电性(N型或P型)的掺质。
此外，下电极110亦可掺杂有不同导电性。于此情形下，反转区将形成于下电极与掺杂区134及136之间。举例来说，掺杂区134及136物理性地掺杂有如磷或/及砷的N型掺质而下电极110物理性地掺杂有如硼的P型掺质。当上电极114连结于一够高电压时，于下电极110内便会形成N型掺杂的一反转区。于如此的方式中，下电极110连结于掺杂有特定电性(在此例如为N型)的掺杂区134及/或136而下电极110则于操作中掺杂有已知导电性。于本说明书中，“操作中掺杂”的意思为当芯片于可操作时所具有的掺杂程度。此定义适用于只有晶体管开启而非芯片开启时的掺杂程度。
于图5a及图5b(统称为图5)中则显示了依据本实用新型实施例中的连结于下电极110及上电极114的接触结构130及131。图5a显示了沿图3内A～A’线段的剖面情形而5b图显示了沿图3内B～B’线段的剖面情形。
于图5图示中包括了一层间介电层138。此层间介电层138可为如二氧化硅的化学气相沉积而成的介电材料。层间介电层138的材质亦可为应用于内联机技术中的低介电常数介电材料。藉由低介电常数介电材料的使用而覆盖于电容器102上，可防止于上电极114与金属导线140间邻近于上电极114处的寄生电容形成。
低介电常数138的相对电容率较佳地少于3.5，更佳地少于3.0。举例来说，低介电常数介电材料可为如苯并环丁烯(BCB)、SILK、FLARE等有机材料。或者，低介电常数介电材料可采用如MSQ、HSQ、SiOF等无机介电材料。在此则不以上述材料而限定可使用的低介电常数介电材料的种类。
如图5所示，于上电极114以及间隔物132上可更覆盖有一蚀刻停止层144。蚀刻停止层144的材质较佳地为氮化硅，亦可使用其它可与层间介电层138显现出不同蚀刻速率的材料。蚀刻停止层144可具有介于-2～+2Gpa的应力，其中负值表示压缩应力(compressives tress)而正值表示拉伸应力(tensile stress)。
如图5a所示，上电极114藉由接触结构131电性耦合于金属导线140。而如图5b所示，下电极110藉由接触结构130电性耦合于位于半导体层104内的掺杂区134(136)。此些接触结构的材质可为如钨的导电材料且其内可更包含有如钛或氮化钛等阻障层(未显示)。
于金属导线140及层间介电层138上更覆盖有一金属层间介电层142。金属层间介电层142可为非前述材料的材料所构成。金属层间介电层142的材质可相同层间介电层138的材质。接触结构亦可穿过金属层间介电层142以连结金属层140，但在此未显示此情形。
电容器102可藉由隔离沟槽的使用而应用于绝缘层上有半导体层的技术中，或者其可能藉由台地隔离法的使用而应用于绝缘层上有半导体层的技术中。在此，台地隔离法是指于晶体管或电容器形成前，于隔离沟槽内无介电材料的填入。于采用台地隔离法的半导体芯片中，形成于主动区之间的沟槽于主动组件形成前并无介电材料的填入。
接着，以下将藉由图6a～图6f以说明本实用新型的电容器制作方法。如前所述，可同时形成一电容器，如图2内所示的电容器116，以作为晶体管之用。
请参照图6a，首先提供一含有基材108、绝缘层106以及半导体层104的绝缘层上有半导体层基材。藉由具有主动图案的掩膜148的使用以于半导体层104内定义出沟槽150。半导体层104较佳地具有不大于1000埃的厚度。绝缘层106的厚度则较佳地不大于1200埃。掩膜层148较佳地为氮化硅层，更佳地为形成于氧化硅层上的氮化硅层。
沟填用介电材料是藉由化学气相沉积法而沉积以填入沟槽150，接着藉由化学机械研磨程序以平坦化之。然后，于移除掩膜层148后形成如图6b的剖面情形。此时，下电极110可为经高度掺杂或无任何掺杂的情形。此时，当采用高掺杂剂量的离子布值步骤以于主动区内掺杂半导体层104时将可形成一经高度掺杂的下电极110。上述经高度掺杂的主动区或下电极110可具有高于1019/每平方公分的掺杂浓度。
如图6c所示，接着形成电容介电层112。电容介电层112的实际厚度较佳地大于5埃，更佳地大于20埃，甚至大于40埃。电容介电层112与半导体芯片(请参照图2，在此未显示)上不同区域内的电容器的栅介电层可同时形成。亦可无需额外的制程步骤，而经由于半导体芯片上不同区域内的电容器栅介电层的形成同时形成高介电常数的电容介电层。
高介电常数介电材料可采用前述材质。前述的高介电常数介电材料可藉由化学气相沉积法、溅镀法或其它已知形成高介电常数介电材料的方法所形成。而于高介电常数的电容介电层112形成前，可更于下电极110上形成一中间层(未图示)。此中间层可为一氧化硅层或一氮氧化硅层。于此中间层形成前，主动区可额外地经由一含氢或一含氮的气体环境而处理之。
接着，沉积上电极114材料于电容介电层112上。上电极114的材料可为如前述的传统多晶硅、多晶硅锗、金属、金属硅化物或金属氮化物等材料。上电极材料可藉由如化学气相沉积的传统技术所形成。上电极材料亦可藉由首先沉积硅与金属并接着经由回火以形成金属硅化栅电极材料。上电极材料接着经由微影技术以图案化之，并藉由电浆蚀刻程序以形成栅电极。
上电极114材料的沉积可与形成于半导体芯片不同区域内晶体管的栅电极材料的沉积于同一制程步骤内完成，且接着上电极的蚀刻可类似晶体管的栅电极蚀刻而一并完成。所形成的上电极114如图6d所示。电容介电层112至少保留于为上电极114所覆盖的部分电容器中。
于邻近下电极的区域中可能导入适当的掺杂以形成与下电极110的电性接触。例如图4b及图5b(以及垂直于图6d平面的上方及下方内)内所示的掺杂区134及136。掺杂区134及136的掺杂是于形成晶体管(图2的116)的源极区以及漏极区时同步完成。举例来说，如图6d内所示的掺杂步骤亦可用于形成源/漏极区内的轻度掺杂区。
如图6e所示，间隔物132可额外地形成于上电极114的侧边上。接着可更经由另一布值程序以掺杂主动区内未为上电极114及间隔件132所覆盖的区域(如图4b内的区域134及136)。上述步骤可藉由芯片上形成晶体管的高度掺杂源极区/漏极区时同步地完成。
而于上电极114及间隔物132上可形成有一蚀刻停止层144。层间介电层138可更形成于电容器上，而接触结构131(及图5b内的接触结构130)可藉由蚀刻层间介电层142直到接触到下电极110及上电极114而形成。然后采用如钨的导电材料以填入于上述接触结构内以使上/下电极与金属导线(如图5b内的金属导线140)形成接触。
如此，本实用新型教导了一种具有较佳电容密度的电容器，本实用新型的电容器是形成于一绝缘层上有半导体层的基材且其是使用高电容率的介电材料作为其电容介电层，因此本实用新型的电容器可具有较高的电容密度。
此外，虽然本实用新型实施例中的电容器是以一去耦合电容器加以解说，本实用新型的制造方法亦可应用于制备其它用途的电容器，而不在此加以限定仅用于形成去耦合电容器。举例来说，上述电容器亦可为一耦合电容器。再者，本实用新型的制造方法亦可应用于其它含有元素态半导体材料、合金半导体材料以及化合物半导体材料的基材，以于其上制备出本实用新型的具有高电容密度的电容器。
虽然本实用新型已以较佳实施例揭露如上，然其并非用以限定本实用新型，任何熟习此技艺者，在不脱离本实用新型的精神和范围内，当可作些许的更动与润饰，因此本实用新型的保护范围当视所附的权利要求范围所界定者为准。

Claims (20)

1.一种电容器，其特征在于，包括：
一绝缘层，覆盖于一基材上；
一半导体层，覆盖于该绝缘层上；
一下电极，形成于部分的该半导体层内；
一电容介电层，覆盖于该下电极上，其中该电容介电层包含具有介电常数大于5的高介电常数介电材料；以及
一上电极，覆盖于该电容介电层上。
2.根据权利要求1所述的电容器，其特征在于，该电容器为去耦合电容器。
3.根据权利要求1所述的电容器，其特征在于，该上电极包括择自由钼、钨、钛、钽、铂、铪、氮化钼、氮化钨、氮化钛、氮化钽、硅化镍、硅化钴、硅化钨、硅化钛、硅化钽、硅化铂、硅化铒及其组合所组成族群。
4.根据权利要求1所述的电容器，其特征在于，该上电极包括择自由氧化钌、氧化铟锡及其组合所组成族群。
5.根据权利要求1所述的电容器，其特征在于，该高介电常数介电材料包括择自由氧化铪、氧化铝、氮氧化铪、氧化锆、氮氧化铪、硅酸铪、硅酸锆、氧化镧及其组合所组成族群。
6.根据权利要求1所述的电容器，其特征在于，该高介电常数介电材料的介电常数大于10。
7.根据权利要求1所述的电容器，其特征在于，该电容介电层的实际厚度少于100埃。
8.根据权利要求1所述的电容器，其特征在于，该电容器的宽度大于5微米。
9.根据权利要求1所述的电容器，其特征在于，该电容器的长度大于1微米。
10.根据权利要求1所述的电容器，其特征在于，该下电极掺杂区掺杂有第一导电性，而该下电极掺杂有第二导电性并耦合于可产生具有第一导电性的反转区的一电源供应线路。
11.根据权利要求1所述的电容器，其特征在于，该下电极以及该下电极掺杂区掺杂有第一导电性。
12.一种电容器，其特征在于，包括：
含有表面硅层的一半导体基材；
一平坦的下电极，形成于部分的该表面硅层内；
一电容介电层，覆盖于该下电极上，其中该电容介电层包含具有介电常数大于5的高介电常数介电材料；以及
一平坦的上电极，覆盖于该电容介电层上，其中该上电极电性耦合于一第一参考电压线路而该下电极电性耦合于一第二参考电压电路。
13.根据权利要求12所述的电容器，其特征在于，该半导体基材，其中该上电极包含择自由钼、钨、钛、钽、铂、铪、氮化钼、氮化钨、氮化钛、氮化钽、硅化镍、硅化钴、硅化钨、硅化钛、硅化钽、硅化铂、硅化铒及其组合所组成族群。
14.根据权利要求12所述的电容器，其特征在于，该高介电常数介电材料包括择自由氧化铪、氧化铝、氮氧化铪、氧化锆、氮氧化铪、硅酸铪、硅酸锆、氧化镧及其组合所组成族群。
15.根据权利要求12所述的电容器，其特征在于，该高介电常数介电材料的介电常数大于10。
16.根据权利要求12所述的电容器，其特征在于，该电容介电层的实际厚度少于100埃。
17.根据权利要求12所述的电容器，其特征在于，该电容器的宽度大于5微米。
18.根据权利要求12所述的电容器，其特征在于，该电容器的长度大于1微米。
19.根据权利要求12所述的电容器，其特征在于，该下电极掺杂有第一导电性而该电容器更包括掺杂有第二导电性的邻近掺杂区。
20.根据权利要求12所述的电容器，其特征在于，该下电极掺杂有第一导电性，而该电容器更包括具有第一导电性的邻近掺杂区。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1320656C (zh) * 2003-07-25 2007-06-06 台湾积体电路制造股份有限公司 电容器及其制造方法
CN107710362A (zh) * 2015-07-23 2018-02-16 株式会社村田制作所 电容器及其制造方法

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003017336A2 (en) * 2001-08-13 2003-02-27 Amberwave Systems Corporation Dram trench capacitor and method of making the same
KR101159070B1 (ko) * 2003-03-11 2012-06-25 삼성전자주식회사 고유전율 산화막 형성방법, 이 방법으로 형성된 유전막이구비된 커패시터 및 그 제조방법
US7119404B2 (en) * 2004-05-19 2006-10-10 Taiwan Semiconductor Manufacturing Co. Ltd. High performance strained channel MOSFETs by coupled stress effects
JP2006059939A (ja) * 2004-08-19 2006-03-02 Fujitsu Ltd Ｍｉｓキャパシタおよびｍｉｓキャパシタ作成方法
KR100590592B1 (ko) * 2004-08-20 2006-06-19 삼성전자주식회사 누설 전류를 감소시킨 유전체층을 포함하는 캐패시터 및그 제조 방법
KR100618869B1 (ko) * 2004-10-22 2006-09-13 삼성전자주식회사 커패시터를 포함하는 반도체 소자 및 그 제조방법
KR100680958B1 (ko) * 2005-02-23 2007-02-09 주식회사 하이닉스반도체 피모스 트랜지스터의 제조방법
JP5130621B2 (ja) * 2005-11-24 2013-01-30 ソニー株式会社 半導体基板の製造方法
CN1983550A (zh) * 2005-12-14 2007-06-20 中芯国际集成电路制造(上海)有限公司 提高可靠性和成品率的消除铜位错的方法
KR100771865B1 (ko) * 2006-01-18 2007-11-01 삼성전자주식회사 스토리지 캐패시터와 고내압 캐패시터를 구비하는 반도체소자의 제조방법 및 그를 사용하여 제조된 반도체 소자
US7473946B2 (en) * 2006-02-22 2009-01-06 International Business Machines Corporation CMOS structure and method including multiple crystallographic planes
US20070246776A1 (en) * 2006-04-20 2007-10-25 Synopsys, Inc. Stress engineering for cap layer induced stress
US7375948B2 (en) * 2006-06-12 2008-05-20 Teledyne Licensing, Llc Variable charge packet integrated circuit capacitor
KR20080018685A (ko) * 2006-08-25 2008-02-28 삼성전자주식회사 반도체 배선 구조, 커패시터를 포함하는 반도체 소자 및 그제조방법
US7880267B2 (en) * 2006-08-28 2011-02-01 Micron Technology, Inc. Buried decoupling capacitors, devices and systems including same, and methods of fabrication
US7943518B2 (en) * 2006-09-21 2011-05-17 Panasonic Corporation Semiconductor chip, semiconductor mounting module, mobile communication device, and process for producing semiconductor chip
US8558278B2 (en) 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
US7943961B2 (en) 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
US7754559B2 (en) * 2008-03-19 2010-07-13 Tower Semiconductor Ltd. Method for fabricating capacitor structures using the first contact metal
US8017474B2 (en) 2008-06-05 2011-09-13 Freescale Semiconductor, Inc. Process of forming an electronic device including a resistor-capacitor filter
US7998832B2 (en) 2008-08-27 2011-08-16 Advanced Micro Devices, Inc. Semiconductor device with isolation trench liner, and related fabrication methods
US8436408B2 (en) * 2008-09-17 2013-05-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with decoupling capacitor design
US7808051B2 (en) 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
WO2010132707A1 (en) * 2009-05-14 2010-11-18 Orbusneich Medical, Inc. Self-expanding stent with polygon transition zone
US8617949B2 (en) 2009-11-13 2013-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor and method for making same
US8604531B2 (en) 2010-10-15 2013-12-10 Taiwan Semiconductor Manufacturing Company Method and apparatus for improving capacitor capacitance and compatibility
US8659121B2 (en) 2011-07-21 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof
US8735986B2 (en) 2011-12-06 2014-05-27 International Business Machines Corporation Forming structures on resistive substrates
US8896096B2 (en) 2012-07-19 2014-11-25 Taiwan Semiconductor Manufacturing Company, Ltd. Process-compatible decoupling capacitor and method for making the same
US9583556B2 (en) 2012-07-19 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Process-compatible decoupling capacitor and method for making the same
US9231197B2 (en) 2012-11-12 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Logic compatible RRAM structure and process
US8742390B1 (en) 2012-11-12 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Logic compatible RRAM structure and process
US9431604B2 (en) 2012-12-14 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Resistive random access memory (RRAM) and method of making
US9023699B2 (en) 2012-12-20 2015-05-05 Taiwan Semiconductor Manufacturing Company, Ltd. Resistive random access memory (RRAM) structure and method of making the RRAM structure
FR3000602B1 (fr) * 2012-12-28 2016-06-24 Commissariat A L Energie Atomique Et Aux Energies Alternatives Procede de gravure d'un materiau dielectrique poreux
US9331277B2 (en) 2013-01-21 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. One transistor and one resistive random access memory (RRAM) structure with spacer
US8908415B2 (en) 2013-03-01 2014-12-09 Taiwan Semiconductor Manufacturing Company, Ltd. Resistive memory reset
US9424917B2 (en) 2013-03-07 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method for operating RRAM memory
US8952347B2 (en) 2013-03-08 2015-02-10 Taiwan Semiconductor Manfacturing Company, Ltd. Resistive memory cell array with top electrode bit line
US9478638B2 (en) 2013-03-12 2016-10-25 Taiwan Semiconductor Manufacturing Company, Ltd. Resistive switching random access memory with asymmetric source and drain
US9231205B2 (en) 2013-03-13 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Low form voltage resistive random access memory (RRAM)
US9466660B2 (en) * 2013-10-16 2016-10-11 Micron Technology, Inc. Semiconductor structures including molybdenum nitride, molybdenum oxynitride or molybdenum-based alloy material, and method of making such structures
CN104752154A (zh) * 2013-12-27 2015-07-01 中芯国际集成电路制造(上海)有限公司 电容器的制作方法
FR3021457B1 (fr) * 2014-05-21 2017-10-13 St Microelectronics Rousset Composant, par exemple transistor nmos, a region active a contraintes en compression relachees, et condensateur de decouplage associe
US9224470B1 (en) 2014-08-05 2015-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit and method of programming memory circuit
CN106680333A (zh) * 2017-02-13 2017-05-17 广州奥松电子有限公司 一种湿敏电容及其制造方法
CN108878446A (zh) * 2018-06-26 2018-11-23 深圳市华星光电技术有限公司 柔性显示面板及显示装置
US11101218B2 (en) * 2018-08-24 2021-08-24 Micron Technology, Inc. Integrated assemblies having metal-containing regions coupled with semiconductor regions
CN113964195B (zh) * 2021-09-18 2022-11-08 珠海妙存科技有限公司 去耦合电容电路结构

Family Cites Families (137)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US153549A (en) * 1874-07-28 Improvement in automatic gas lighters and extinguishers
US300091A (en) * 1884-06-10 Fire-escape
US4069094A (en) 1976-12-30 1978-01-17 Rca Corporation Method of manufacturing apertured aluminum oxide substrates
JPS551103A (en) * 1978-06-06 1980-01-07 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor resistor
US4497683A (en) 1982-05-03 1985-02-05 At&T Bell Laboratories Process for producing dielectrically isolated silicon devices
US4631803A (en) * 1985-02-14 1986-12-30 Texas Instruments Incorporated Method of fabricating defect free trench isolation devices
US4892614A (en) 1986-07-07 1990-01-09 Texas Instruments Incorporated Integrated circuit isolation process
US4831803A (en) * 1986-10-23 1989-05-23 Nicola Leonardis Foundation form work
JPH0640583B2 (ja) 1987-07-16 1994-05-25 株式会社東芝 半導体装置の製造方法
US4946799A (en) * 1988-07-08 1990-08-07 Texas Instruments, Incorporated Process for making high performance silicon-on-insulator transistor with body node to source node connection
JPH0394479A (ja) 1989-06-30 1991-04-19 Hitachi Ltd 感光性を有する半導体装置
US5155571A (en) 1990-08-06 1992-10-13 The Regents Of The University Of California Complementary field effect transistors having strained superlattice structure
JP3019430B2 (ja) * 1991-01-21 2000-03-13 ソニー株式会社 半導体集積回路装置
US5525828A (en) 1991-10-31 1996-06-11 International Business Machines Corporation High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields
US5338960A (en) 1992-08-05 1994-08-16 Harris Corporation Formation of dual polarity source/drain extensions in lateral complementary channel MOS architectures
US5461250A (en) * 1992-08-10 1995-10-24 International Business Machines Corporation SiGe thin film or SOI MOSFET and method for making the same
US5273915A (en) 1992-10-05 1993-12-28 Motorola, Inc. Method for fabricating bipolar junction and MOS transistors on SOI
US5596529A (en) 1993-11-30 1997-01-21 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
JPH0846139A (ja) 1994-05-06 1996-02-16 Texas Instr Inc <Ti> ポリシリコン抵抗器とその作成法
US5534713A (en) * 1994-05-20 1996-07-09 International Business Machines Corporation Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers
US5479033A (en) 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
US5447884A (en) * 1994-06-29 1995-09-05 International Business Machines Corporation Shallow trench isolation with thin nitride liner
US6433382B1 (en) 1995-04-06 2002-08-13 Motorola, Inc. Split-gate vertically oriented EEPROM device and process
US5629544A (en) * 1995-04-25 1997-05-13 International Business Machines Corporation Semiconductor diode with silicide films and trench isolation
US6103699A (en) * 1996-06-07 2000-08-15 Immunotech Developments Inc. Peptide, a method for its preparation and a pharmaceutical composition containing the peptide
US5955766A (en) 1995-06-12 1999-09-21 Kabushiki Kaisha Toshiba Diode with controlled breakdown
US5865917A (en) * 1995-08-09 1999-02-02 Loewe; Richard Thomas Deformation-based tire inflation device
US5708288A (en) 1995-11-02 1998-01-13 Motorola, Inc. Thin film silicon on insulator semiconductor integrated circuit with electrostatic damage protection and method
TW335558B (en) 1996-09-03 1998-07-01 Ibm High temperature superconductivity in strained SiSiGe
US6399970B2 (en) 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US5789807A (en) * 1996-10-15 1998-08-04 International Business Machines Corporation On-chip power distribution for improved decoupling
US5811857A (en) * 1996-10-22 1998-09-22 International Business Machines Corporation Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications
US5763315A (en) * 1997-01-28 1998-06-09 International Business Machines Corporation Shallow trench isolation with oxide-nitride/oxynitride liner
US5714777A (en) * 1997-02-19 1998-02-03 International Business Machines Corporation Si/SiGe vertical junction field effect transistor
JP4053647B2 (ja) 1997-02-27 2008-02-27 株式会社東芝 半導体記憶装置及びその製造方法
US5906951A (en) * 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
DE19720008A1 (de) 1997-05-13 1998-11-19 Siemens Ag Integrierte CMOS-Schaltungsanordnung und Verfahren zu deren Herstellung
US6027988A (en) 1997-05-28 2000-02-22 The Regents Of The University Of California Method of separating films from bulk substrates by plasma immersion ion implantation
US5894152A (en) 1997-06-18 1999-04-13 International Business Machines Corporation SOI/bulk hybrid substrate and method of forming the same
KR100400808B1 (ko) * 1997-06-24 2003-10-08 매사츄세츠 인스티튜트 오브 테크놀러지 그레이드된 ＧｅＳｉ층 및 평탄화를 사용한 Ｓｉ상의 Ｇｅ의 쓰레딩 전위 밀도 제어
US6096591A (en) 1997-06-30 2000-08-01 Advanced Micro Devices, Inc. Method of making an IGFET and a protected resistor with reduced processing steps
US6221709B1 (en) 1997-06-30 2001-04-24 Stmicroelectronics, Inc. Method of fabricating a CMOS integrated circuit device with LDD N-channel transistor and non-LDD P-channel transistor
US6103599A (en) 1997-07-25 2000-08-15 Silicon Genesis Corporation Planarizing technique for multilayered substrates
US5843816A (en) * 1997-07-28 1998-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated self-aligned butt contact process flow and structure for six transistor full complementary metal oxide semiconductor static random access memory cell
US6495900B1 (en) 1997-11-12 2002-12-17 Micron Technology, Inc. Insulator for electrical structure
EP0923116A1 (en) * 1997-12-12 1999-06-16 STMicroelectronics S.r.l. Process for manufacturing integrated multi-crystal silicon resistors in MOS technology and integrated MOS device comprising multi-crystal silicon resistors
US6100153A (en) 1998-01-20 2000-08-08 International Business Machines Corporation Reliable diffusion resistor and diffusion capacitor
US5972722A (en) 1998-04-14 1999-10-26 Texas Instruments Incorporated Adhesion promoting sacrificial etch stop layer in advanced capacitor structures
JP3265569B2 (ja) * 1998-04-15 2002-03-11 日本電気株式会社 半導体装置及びその製造方法
GB9808561D0 (en) * 1998-04-23 1998-06-24 Lucas Ind Plc Security arrangement
US6558998B2 (en) * 1998-06-15 2003-05-06 Marc Belleville SOI type integrated circuit with a decoupling capacity and process for embodiment of such a circuit
JP3403076B2 (ja) 1998-06-30 2003-05-06 株式会社東芝 半導体装置及びその製造方法
US6100204A (en) 1998-07-28 2000-08-08 Advanced Micro Devices, Inc. Method of making ultra thin gate oxide using aluminum oxide
US6008095A (en) * 1998-08-07 1999-12-28 Advanced Micro Devices, Inc. Process for formation of isolation trenches with high-K gate dielectrics
US6387739B1 (en) * 1998-08-07 2002-05-14 International Business Machines Corporation Method and improved SOI body contact structure for transistors
KR100277743B1 (ko) * 1998-08-14 2001-01-15 권영두 공작기계의 자동공구 교환장치
US6015993A (en) * 1998-08-31 2000-01-18 International Business Machines Corporation Semiconductor diode with depleted polysilicon gate structure and method
JP2000132990A (ja) 1998-10-27 2000-05-12 Fujitsu Ltd 冗長判定回路、半導体記憶装置及び冗長判定方法
US5965917A (en) 1999-01-04 1999-10-12 Advanced Micro Devices, Inc. Structure and method of formation of body contacts in SOI MOSFETS to elimate floating body effects
US6258664B1 (en) * 1999-02-16 2001-07-10 Micron Technology, Inc. Methods of forming silicon-comprising materials having roughened outer surfaces, and methods of forming capacitor constructions
TW403969B (en) 1999-04-09 2000-09-01 United Microelectronics Corp Method for manufacturing metal oxide semiconductor
US6358791B1 (en) * 1999-06-04 2002-03-19 International Business Machines Corporation Method for increasing a very-large-scale-integrated (VLSI) capacitor size on bulk silicon and silicon-on-insulator (SOI) wafers and structure formed thereby
US6362082B1 (en) 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6737710B2 (en) 1999-06-30 2004-05-18 Intel Corporation Transistor structure having silicide source/drain extensions
US6339232B1 (en) 1999-09-20 2002-01-15 Kabushika Kaisha Toshiba Semiconductor device
US6303479B1 (en) 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
US7391087B2 (en) * 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
US6541343B1 (en) 1999-12-30 2003-04-01 Intel Corporation Methods of making field effect transistor structure with partially isolated source/drain junctions
US6255175B1 (en) 2000-01-07 2001-07-03 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with minimized parasitic Miller capacitance
TW503439B (en) * 2000-01-21 2002-09-21 United Microelectronics Corp Combination structure of passive element and logic circuit on silicon on insulator wafer
US6475838B1 (en) * 2000-03-14 2002-11-05 International Business Machines Corporation Methods for forming decoupling capacitors
JP3504212B2 (ja) 2000-04-04 2004-03-08 シャープ株式会社 Ｓｏｉ構造の半導体装置
US6420218B1 (en) 2000-04-24 2002-07-16 Advanced Micro Devices, Inc. Ultra-thin-body SOI MOS transistors having recessed source and drain regions
US6281059B1 (en) 2000-05-11 2001-08-28 Worldwide Semiconductor Manufacturing Corp. Method of doing ESD protective device ion implant without additional photo mask
DE10025264A1 (de) 2000-05-22 2001-11-29 Max Planck Gesellschaft Feldeffekt-Transistor auf der Basis von eingebetteten Clusterstrukturen und Verfahren zu seiner Herstellung
JP2001338988A (ja) 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
US6555839B2 (en) * 2000-05-26 2003-04-29 Amberwave Systems Corporation Buried channel strained silicon FET using a supply layer created through ion implantation
JP3843708B2 (ja) * 2000-07-14 2006-11-08 日本電気株式会社 半導体装置およびその製造方法ならびに薄膜コンデンサ
JP2002043576A (ja) 2000-07-24 2002-02-08 Univ Tohoku 半導体装置
US6429061B1 (en) 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
FR2812764B1 (fr) * 2000-08-02 2003-01-24 St Microelectronics Sa Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu
JP2002076287A (ja) 2000-08-28 2002-03-15 Nec Kansai Ltd 半導体装置およびその製造方法
JP4044276B2 (ja) 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6413802B1 (en) * 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
WO2002047168A2 (en) 2000-12-04 2002-06-13 Amberwave Systems Corporation Cmos inverter circuits utilizing strained silicon surface channel mosfets
US6414355B1 (en) * 2001-01-26 2002-07-02 Advanced Micro Devices, Inc. Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness
US6894324B2 (en) * 2001-02-15 2005-05-17 United Microelectronics Corp. Silicon-on-insulator diodes and ESD protection circuits
US6518610B2 (en) * 2001-02-20 2003-02-11 Micron Technology, Inc. Rhodium-rich oxygen barriers
US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6867101B1 (en) 2001-04-04 2005-03-15 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having a nitride/high-k/nitride gate dielectric stack by atomic layer deposition (ALD) and a device thereby formed
US6593181B2 (en) 2001-04-20 2003-07-15 International Business Machines Corporation Tailored insulator properties for devices
US6586311B2 (en) 2001-04-25 2003-07-01 Advanced Micro Devices, Inc. Salicide block for silicon-on-insulator (SOI) applications
JP2002329861A (ja) 2001-05-01 2002-11-15 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6489684B1 (en) 2001-05-14 2002-12-03 Taiwan Semiconductor Manufacturing Company Reduction of electromigration in dual damascene connector
US6718673B2 (en) 2001-06-29 2004-04-13 Raypress Corporation Clean release magnet and the manufacturing method thereof
US6952040B2 (en) * 2001-06-29 2005-10-04 Intel Corporation Transistor structure and method of fabrication
US6576526B2 (en) * 2001-07-09 2003-06-10 Chartered Semiconductor Manufacturing Ltd. Darc layer for MIM process integration
WO2003017336A2 (en) 2001-08-13 2003-02-27 Amberwave Systems Corporation Dram trench capacitor and method of making the same
US6700771B2 (en) * 2001-08-30 2004-03-02 Micron Technology, Inc. Decoupling capacitor for high frequency noise immunity
US6690082B2 (en) 2001-09-28 2004-02-10 Agere Systems Inc. High dopant concentration diffused resistor and method of manufacture therefor
US6821847B2 (en) * 2001-10-02 2004-11-23 Mosel Vitelic, Inc. Nonvolatile memory structures and fabrication methods
US6521952B1 (en) 2001-10-22 2003-02-18 United Microelectronics Corp. Method of forming a silicon controlled rectifier devices in SOI CMOS process for on-chip ESD protection
US6555883B1 (en) 2001-10-29 2003-04-29 Power Integrations, Inc. Lateral power MOSFET for high switching speeds
US6621131B2 (en) 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
JP4173658B2 (ja) 2001-11-26 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US6657259B2 (en) 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6657276B1 (en) 2001-12-10 2003-12-02 Advanced Micro Devices, Inc. Shallow trench isolation (STI) region with high-K liner and method of formation
US6600170B1 (en) 2001-12-17 2003-07-29 Advanced Micro Devices, Inc. CMOS with strained silicon channel NMOS and silicon germanium channel PMOS
FI119215B (fi) 2002-01-31 2008-08-29 Imbera Electronics Oy Menetelmä komponentin upottamiseksi alustaan ja elektroniikkamoduuli
JP2003282726A (ja) 2002-03-27 2003-10-03 Nec Electronics Corp 半導体装置及びその製造方法
US6784101B1 (en) 2002-05-16 2004-08-31 Advanced Micro Devices Inc Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation
JP4136452B2 (ja) * 2002-05-23 2008-08-20 株式会社ルネサステクノロジ 半導体装置及びその製造方法
WO2003105204A2 (en) * 2002-06-07 2003-12-18 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
US6812103B2 (en) 2002-06-20 2004-11-02 Micron Technology, Inc. Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects
US6617643B1 (en) 2002-06-28 2003-09-09 Mcnc Low power tunneling metal-oxide-semiconductor (MOS) device
US6740535B2 (en) 2002-07-29 2004-05-25 International Business Machines Corporation Enhanced T-gate structure for modulation doped field effect transistors
US6686247B1 (en) 2002-08-22 2004-02-03 Intel Corporation Self-aligned contacts to gates
US6969618B2 (en) 2002-08-23 2005-11-29 Micron Technology, Inc. SOI device having increased reliability and reduced free floating body effects
JP4030383B2 (ja) 2002-08-26 2008-01-09 株式会社ルネサステクノロジ 半導体装置およびその製造方法
DE10240423B4 (de) * 2002-09-02 2007-02-22 Advanced Micro Devices, Inc., Sunnyvale Halbleiterelement mit einem Feldeffekttransistor und einem passiven Kondensator mit reduziertem Leckstrom und einer verbesserten Kapazität pro Einheitsfläche und Verfahren zu dessen Herstellung
US6573172B1 (en) 2002-09-16 2003-06-03 Advanced Micro Devices, Inc. Methods for improving carrier mobility of PMOS and NMOS devices
US6730573B1 (en) 2002-11-01 2004-05-04 Chartered Semiconductor Manufacturing Ltd. MIM and metal resistor formation at CU beol using only one extra mask
US6720619B1 (en) 2002-12-13 2004-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices
US6919233B2 (en) * 2002-12-31 2005-07-19 Texas Instruments Incorporated MIM capacitors and methods for fabricating same
US6924181B2 (en) 2003-02-13 2005-08-02 Taiwan Semiconductor Manufacturing Co., Ltd Strained silicon layer semiconductor product employing strained insulator layer
US6921913B2 (en) 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US6794764B1 (en) * 2003-03-05 2004-09-21 Advanced Micro Devices, Inc. Charge-trapping memory arrays resistant to damage from contact hole information
US6845034B2 (en) 2003-03-11 2005-01-18 Micron Technology, Inc. Electronic systems, constructions for detecting properties of objects, and assemblies for identifying persons
US6762448B1 (en) 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US7045849B2 (en) 2003-05-21 2006-05-16 Sandisk Corporation Use of voids between elements in semiconductor structures for isolation
US20040266116A1 (en) 2003-06-26 2004-12-30 Rj Mears, Llc Methods of fabricating semiconductor structures having improved conductivity effective mass
US20040262683A1 (en) 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6936881B2 (en) * 2003-07-25 2005-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor that includes high permittivity capacitor dielectric
US6891192B2 (en) 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US6872610B1 (en) 2003-11-18 2005-03-29 Texas Instruments Incorporated Method for preventing polysilicon mushrooming during selective epitaxial processing
US7224068B2 (en) 2004-04-06 2007-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Stable metal structure with tungsten plug
US7115974B2 (en) 2004-04-27 2006-10-03 Taiwan Semiconductor Manfacturing Company, Ltd. Silicon oxycarbide and silicon carbonitride based materials for MOS devices

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1320656C (zh) * 2003-07-25 2007-06-06 台湾积体电路制造股份有限公司 电容器及其制造方法
CN107710362A (zh) * 2015-07-23 2018-02-16 株式会社村田制作所 电容器及其制造方法
CN107710362B (zh) * 2015-07-23 2019-10-18 株式会社村田制作所 电容器

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