CN2726123Y - 半导体组件 - Google Patents

半导体组件 Download PDF

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CN2726123Y
CN2726123Y CNU2004200496032U CN200420049603U CN2726123Y CN 2726123 Y CN2726123 Y CN 2726123Y CN U2004200496032 U CNU2004200496032 U CN U2004200496032U CN 200420049603 U CN200420049603 U CN 200420049603U CN 2726123 Y CN2726123 Y CN 2726123Y
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transistor
heavily stressed
semiconductor subassembly
subassembly according
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柯志欣
杨育佳
李文钦
胡正明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

本实用新型是关于一种半导体组件，此半导体组件的结构包括：一栅极介电层，覆盖于一通道区上；一源极区及一汲极区，位于该通道区的对称侧，其中通道区包含有第一半导体材料而源极区及汲极区包含有第二半导体材料；一闸电极，覆盖于栅极介电层上；以及一第一间隔物及一第二间隔物，形成于闸电极两侧上，其中此些间隔物各包含有邻近于该通道区的一空隙(void)。

Description

半导体组件
技术领域
本实用新型是有关于一种半导体组件，且特别是有关于一种应变通道互补型场效应晶体管(strained channel complementary field-effecttransistor)。
背景技术
近十几年来，随着金氧半场效晶体管(metal-oxide-semiconductorfield effect transistor，MOSFET)尺寸的缩小，包括栅极长度与栅极氧化层厚度的缩小，已使得持续改善速度效能、密度与每单位IC(integratedcircuits)成本成为可能。
为了更进一步提升晶体管的效能，可利用在晶体管通道的应变(strain)来改善载子迁移率，以达到提升晶体管效能的目的，进而使组件比例缩小。以下介绍几个使通道区应变的现有方法。
常见方法之一为，如1992年12月于加州旧金山所举行的InternationalElectron Devices Meeting所发表刊物中第1000-1002页处，由J.Welser等人于标题为“NMOS and PMOS transistors fabricated in strainedsilicon/relaxed silicon-germanium structures”的论文中所述，将一松散锗化硅(relaxed SiGe)缓冲层提供于通道区的下方，如图1a所示。如图1a所示，包含有形成且突出于一松散锗化硅层112的应变硅层110的一半导体组件100，其是位于一衰减锗化硅(degraded SiGe)缓冲层114。此衰减硅锗化硅(degraded SiGe)缓冲层114则形成于一硅基底116上。
于图1b中，松散锗化硅层112具有相较于松散硅材料的一较大晶格常数，因此磊晶成长于松散锗化硅层112上的应变硅层110其晶格将横向地延伸。其结果如图1b及图1c所示。因此，形成于应变硅层110上的晶体管108将具有处于二维上拉伸张力(biaxial tensile stress)。于此法中，松散锗化硅层112可视为施加应变于通道区120内的一应力区。此时，此应力区是设置于通道区120的下方。
采用位于二维拉伸张力的硅通道的晶体管中，整个晶体管中电子与电洞迁移率有显著的提升。于前述方法中，应变硅层是于晶体管形成前就已应变，因此，需特别注意后续CMOS的高温制程所可能产生的应变松散(strainrelaxation)。此外，由于锗化硅缓冲层的厚度是以微米的等级在成长，所以此法非常昂贵。再者，松散锗化硅缓冲层中存在许多差排(dislocation)现象，有些还会增生到应变硅层中，而产生高缺陷密度，使晶体管效能受到负面影响。因此，上述方法具有成本上及材料特性上限制。
于其它方法中，通道区是于晶体管形成后应变。在此方法中，一高应力薄膜132形成于位于硅基底136上的一晶体管结构130上，如图2所示。此高应力薄膜132(或应力区)对通道区134产生重大影响，使得通道区134晶格间隙(lattice spacing)改变且产生应变。此时，应力区132位于整个晶体管结构上方，详细的描述请参考A.Shimizu et al.，“Local mechanicalstress control (LMC)：a new technique for CMOS performanceenhancement”，pp.433-436 of the Digest of Technical Papers of the2001 International Electron Device Meeting。
上述高应力薄膜所产生的应变于本质上被认为是与源极至汲极方向(source-to-drain direction)平行的一维方向(uniaxial)。然而，于源极至汲极方向上的一维拉伸张力应变减低了电洞迁移率，而一维的压缩应力减低了电子迁移率。亦可采用如锗的离子植入以选择性地减轻上述应变，使电洞或电子迁移率不致降低，然而由于n通道与p通道晶体管很靠近，所以上述植入的施行亦为困难。
发明内容
有鉴于习知技术中于晶体管中导入应变的方法，藉由一应力区以导入应变可使得具有第一导电性的晶体管受益但却导致具有第二导电性的晶体管的表现劣化。藉由本实用新型的较佳实施例所提供的制造n通道及p通道场效应晶体管的方法可达到解决或减少上述问题或其它问题，并达到分别最佳化其表现的目的。
于第一实施例中，本实用新型提供了一晶体管结构以去除于此晶体管通道区的一应力区的影响。如此的结构极适合用于当应力区降低了其载子迁移率时。本实用新型亦提供了一种整合方法用以最适化n通道及p通道场效应晶体管的通道区内应变。
依据本实用新型的一较佳实施例的一种晶体管，其包括：一栅极介电层，覆盖于一通道区上；一源极区及一汲极区，位于该通道区的对称侧，其中通道区包含有第一半导体材料而源极区及汲极区包含有第二半导体材料；一闸电极，覆盖于栅极介电层上；以及一第一间隔物及一第二间隔物，形成于闸电极两侧上，其中此些间隔物各包含有邻近于该通道区的一空隙(void)。
依据本实用新型的一较佳实施例的一种晶体管组件，其包括：一半导体基底；一第一晶体管，形成于半导体基底内，其中第一晶体管具有由第一半导体材料所构成的一第一通道区以及对称地设置于邻近第一通道区的一第一源极区及一第一汲极区，而第一源极区及第一汲极区包含与第一半导体材料晶格不对称的一第二半导体材料；以及一第二晶体管形成于半导体基底内且具有异于第一晶体管的一导电性(conductivity type)，其中该第二晶体管具有由第二半导体材料所构成的第二通道区，该第二晶体管亦具有对称地设置于邻近第二通道区的一第二源极区及一第二汲极区，而第二源极区及第二汲极区包含与异于第二半导体材料的一材料。
附图说明
图1a显示具有作为应力区的一松散锗化硅层以使磊晶硅层上方产生应变的一习知应变硅(strained-Si)晶体管；
图1b及图1c显示于Si/SiGe异质结构间的原始应变；
图2显示采用一高应力薄膜作为应力区以导入应变于通道区的另一方式。
图3a～图3g显示第一实施例的制程流程。
图4a～图4d显示第二实施例的制程流程。
符号说明：
100～半导体组件；              108、130～晶体管；
110～应变硅层；                112～松散锗化硅层；
114～衰减锗化硅缓冲层；        116、136～硅基底；
120、134～通道区；             132～高应力薄膜。
200～p通道晶体管；             201～n通道晶体管；
202～硅基底；
204a、204b、204c～隔离区；
206～栅极介电层；              208～闸电极；
210～源极延伸区；              212～汲极延伸区；
214、216～间隔物；             218～介电罩幕；
220、240～凹陷；               222、226～底切；
224、225～源/汲极区；          228、238～高应力膜层；
230、232～空隙；               234～空隙的长度；
236～通道区；                 242～第一半导体材料；
244～第二半导体材料。
具体实施方式
为了让本实用新型的上述和其它目的、特征、和优点能更明显易懂，下文特举一较佳实施例，并配合所附图示，作详细说明如下：
以下将详细讨论较佳实施例的制作与使用。然而，本实用新型不仅提供了多种于广泛领域可实施的发明概念，于特定实施例中所讨论的制作与使用为更充分说明本实用新型的制作与使用而非限制本实用新型的领域。
本实用新型的较佳实施例是有关于半导体组件的领域，且特别地有关于具有分别最佳化表现的经应变n通道及p通道场效应晶体管。
于较佳实施例中，n通道及p通道晶体管可藉由操纵于其通道区中的应变量及应变本质以最佳化其表现。比方说，于n通道晶体管通道的源极至汲极方向中最好导入拉伸应力以得到较佳表现，而于p通道晶体管通道的源极至汲极方向中最好导入压缩应力以得到较佳表现。
于一实施例中，可采用具有拉伸应力的一高应力膜层以导入拉伸应力至晶体管的通道区。可是，于源极至汲极方向的拉伸应力于改善了n通道晶体管的迁移率但降低了p通道晶体管的迁移率。依据本实用新型的较佳实施例中，当高应力膜层的效应减低了于通道区中载子的迁移率时，可采用如空隙的一应力减低区以减低于通道区上高应力膜层的效应。
举例来说，具有拉伸应力的高应力膜层可于源极至汲极方向产生拉伸应变而降低了p通道晶体管中的电洞迁移率。可于p通道晶体管的间隔物区内形成一空隙以降低此高应力膜层的影响。所空出的表面表现出无应力的边界状态且因此表现出极低应力的区域。此空出表面或为此空出表面所围绕区域即为一空隙区。藉由于高应力膜层及此p通道晶体管的通道区间设置空隙，将可减低拉伸应力对于p通道晶体管的负面影响。因此，藉由设置空隙于所选择通道区内如所选择晶体管的间隔物内的空洞处，可降低所选择通道区的此高应力膜层的应力。较大的空隙可造成较多降低效用而因此降低应力规模。举例来说，于p通道晶体管间隔物内的空隙可大于n通道晶体管的间隔物内的空隙。
第一实施例
图3a～图3g中图示了第一实施例中分别最适化于一半导体芯片中晶体管的通道区应变的方法。于此较佳实施例中，起始材料为硅基底，亦可使用含有如砷化镓的化合物半导体材料或如锗化硅的合金半导体材料。此起始材料亦可为如绝缘层上有硅基材的一绝缘层上有半导体层(SOI)基底。此外，此起始材料亦可为包含由磊晶成长而成的一半导体层且/或为如一三重井区结构的为于半导体层内经掺杂的一区域。
图3a显示了使用起始材料为一硅基底块202的较佳实施例。隔离区204a、204b及204c(以下统称为204)则形成于基底202内。此些隔离区204较佳地为熟悉此技艺者所熟知的浅沟槽隔离物。此外，为熟悉此技艺者所理解，亦可采用其它如场氧化层(藉由局部的硅氧化所形成)的其它隔离结构。
图3a中显示有两主动区，分别为介于隔离区204a及204b间及隔离区204b及204c间的第一主动区及第二主动区。举例来说，可于此些主动区其中之一内形成一n通道晶体管，而于另一主动区内则可形成一p通道晶体管。且如习知技术所知，于含有上述n通道晶体管的基底202部分将掺杂有p型掺质而含有上述p通道晶体管的基底202部分则将掺杂有n型掺质。此些经掺杂部将可由习知的一个或多个井区使用而形成。
于半导体区202上的表面则形成有一栅极介电层206。此栅极介电层206可包含二氧化硅、氮氧化硅及氮化硅，或为上述材质的组合。此外，栅极介电层206亦可为由具有相对介电常数大于5的材质所形成，其材质例如为氧化铝、氧化铪、氧化锆、氮氧化铪、氧化镧或为此些材质的组合。
接着沉积一闸电极材料。此闸电极材料较佳地含有如钽、钛、钼、钨、铂、铝、铪、镧的金属、含有如钛的硅化物、钴的硅化物、镍的硅化物、铊的硅化物的金属硅化物、经掺杂的多晶硅或多晶硅锗或任何其它的导电材质。上述材质亦可结合地使用。上述任何导体皆可搭配前述的栅极介电材料使用。例如，可先沉积一非晶硅并接着再结晶化此非晶硅以形成多晶硅。
接着依序实施一微影步骤及一蚀刻步骤以形成如图3a中的堆栈栅极。此堆栈栅极含有闸电极208及其下的栅极介电层206。于较佳实施例中，闸电极208的材质为多晶硅而栅极介电层206的材质为氮氧化硅。闸电极厚度通常约介于500～2000埃，较佳地少于1500埃。而栅极介电层206的等效氧化硅厚度则通常介于3～50埃，较佳地少于20埃。
源极延伸区及汲极延伸区210、212则由离子植入方式所形成。于较佳实施例中，则形成具有不同导电类型通道区的两晶体管200及201。例如，当n通道组件被遮蔽时，p通道延伸区210(或212)可藉由植入如硼的掺质以形成。同上，当p通道组件被遮蔽时，n通道延伸区210(或212)可由植入如砷或磷的掺质而形成。
请参照图3b，于闸电极208的侧边上形成有间隔物214/216。于一例子中，间隔物可如二氧化硅或氮化硅由化学气相沉积法所沉积而成的介电材质所构成，并由对此介电材质的非等向性蚀刻而形成简单的间隔物。于图3b中所示，间隔物为一复合间隔物，其包含有介电衬层214以及间隔物主体216。此介电衬层214可由如氧化硅的介电衬层材质的沉积所形成，而如氮化硅的间隔物主体216则可由采用反应性离子蚀刻的一非等向性蚀刻而形成。于另一实施例中，介电衬层214可为氧化物而介电衬层可为氮化物。
依据较佳实施例，于第一主动区内(于隔离区204a及204b间的半导体区202)形成具有第一导电类型的晶体管200，其源极区及汲极区内形成有晶格不相称区。请参照图3c，其可藉由于包含有晶体管201的第二主动区(于隔离区204b及204c间的半导体区202)内形成一介电罩幕218所形成，而露出具有第一导电类型的晶体管200。
如图3c所示，于此第一导电类型晶体管的源极区及汲极区中蚀刻形成凹陷区220。形成凹陷区220的蚀刻可为干式电浆蚀刻程序。于较佳实施例中，当基底202为硅基底时，此电浆干蚀刻程序可采用含氟的化学品。值得注意的，于形成凹陷区220的蚀刻时，复合间隔物的介电衬层214亦可能轻微地被蚀刻而形成底切区222。
请参照图3d，接着施行一选择性磊晶程序以形成此于具有第一导电种类晶体管的源极区及汲极区224。此磊晶成长而成的材质224较佳地为与基底202材质具有不同自然晶格常数的一半导体材料。在此，当第一导电类型为p型时，此晶格不相称材质224较佳地为锗化硅。而当第一导电类型为n型时，此晶格不相称材质224较佳地为碳化硅或碳硅锗(Si1-x-yGexCy)合金，其中碳的穆尔分率y大于锗的穆尔分率的十分之一。于第一导电类型晶体管的源极区及汲极区224高度可能高于第二导电类型晶体管的源极汲极区的高度。
值得注意的，形成介电罩幕218、蚀刻凹陷区220以及磊晶成长晶格不对称材料224的制程步骤可于形成间隔物214、216于闸电极208的侧边上前先被执行。
如图3e所示，接着移除介电罩幕218。当介电罩幕材质为氧化硅时，其可由使用经稀释的氢氟酸溶液达成。于移除介电罩幕218过程中可能于晶体管201的介电衬层214中产生底切226。由于经过两次类似的上述制程，底切222可能大于底切226。
于遮蔽PMOS晶体管202时，可由离子植入方式形成NMOS晶体管201的源极区及汲极区。于较佳实施例中，所使用的掺质可为砷、磷或其组合。其源极区及汲极区225则如图3f中所示。
如图3f所示，于晶体管200及201上形成一高应力薄膜228。此高应力薄膜228可为氮化硅或其它高应力的材料。其应力可为压缩或拉伸应力且其约为0.1～4GPa。此高应力薄膜228的形成方法较佳地为化学气相沉积法，如一低压化学气相沉积法(LPCVD)或一电浆加强型化学气相沉积法(PECVD)或其它习知方法。
由于底切222及226分别形成于晶体管的间隔物内，故空隙230及232则亦形成于间隔物内。其为自然形成且带来额外的效益。值得注意的，于高应力薄膜228的形成过程中，极可能完全地于填入此些底切内而使得最终结构中无空隙的形成。另一方面，本实用新型教导了于一应变通道晶体管中自然形成空隙的方法以有效去除位于具有某一导电类型晶体管上高应力薄膜的负面影响。
于较佳实施例中，当此第一导电类型为p型而第二导电类型为n型时，于空隙230及232分别具有横向的伸展并可视作为上述空隙的长度。例如为于图3f中所示n通道晶体管201的空隙232的长度234。于此空隙区的空隙尺寸如剖面图内的第一空隙。当于剖面图中的第一空隙的尺寸大于相同图示中的第二空隙，具有较大尺寸或较大长度的空隙可较具有较小尺寸或较小长度的空隙具有较高的应力减低效应。
于较佳实施例中，空隙230及232的尺寸可由量测间隔物214、216的宽度得知。比方说，空隙232可能具有超过间隔物宽度的5％的一长度234。而于另一实施例中，空隙232则可能具有超过间隔物214、216的至少10％的宽度。
当于n通道及p通道晶体管201及200上为单一高拉伸应力膜层228所覆盖时，各晶体管的通道区236将感受到一拉伸应变，而n通道晶体管201将可获得较佳的迁移率改善，但此时p通道晶体管200的迁移率反而劣化。而依据较佳实施例，可导入空隙230于p通道通道区236的空缺处以消除高拉伸张力薄膜228的负面效应。而依据另一较佳实施例，p通道晶体管200的通道区236可具有较邻近于n通道晶体管201的通道区236内空隙232为大的空隙230。
于另一实施例中，如图3g所示，于p通道晶体管200上可为一高压缩应力膜层238所覆盖而n通道晶体管可为一高拉伸应力膜层228所覆盖时。此时压缩应力依源极至汲极方向作用于p通道晶体管200的通道区236中并改善其内的电洞迁移率，而拉伸应力则依源极至汲极方向作用于n通道晶体管201的通道区236中并改善其内的电子迁移率。
如图3g中所示的结构可由先形成图3f中的结构并接着形成一罩幕层(未显示)覆盖于n通道晶体管的高拉伸应力膜层228。此覆盖于p通道晶体管的高应力膜层可接着形成于p通道晶体管上。比方说，此膜层可完全地覆盖于整个组件上且然后由蚀刻以定义出所期望的图案。
第二实施例
本实用新型的另一方法实施例将由图4a～图4d加以说明，而于先前图3a～图3g中所讨论的项目在此不再重复。两种不同导电类型的晶体管200及201分别形成于不同的主动区内，且由一蚀刻步骤以蚀刻个别晶体管的源极区及汲极区。此蚀刻可采如干式电浆蚀刻的蚀刻步骤。所形成的结构则如图4a中所示，于晶体管200及201中分别显示有凹陷220及240。
请参照图4b，于源极区及汲极区内的凹陷220及240内分别磊晶地成长出晶格不对称区242及244。于p通道晶体管及n通道晶体管200及201内则可使用不同的晶格不相称材料。可由首先形成一罩幕(未显示)覆盖于n通道晶体管上且施行一第一磊晶以选择性成长出一第一半导体材料242于p通道晶体管的源极区及汲极区内。
于此罩幕移除后，接着形成一第二罩幕(未显示)以覆盖于p通道晶体管200。接着施行一第二磊晶程序以选择性地于n通道晶体管201的源极区及汲极区内成长第二半导体材料244。于图4b中则显示了其最终结构。
于较佳实施例中，第一半导体材料242可为锗化硅而第二半导体材料244可为碳化硅或硅锗碳(Si1-x-yGexCy)合金，其中碳的穆尔分率y大于锗的穆尔分率的十分之一。由于基底202的材料较佳地为硅，具有较大晶格常数的锗化硅材料的第一半导体材料的出现将导致p通道晶体管200的通道区236处于压缩应变。类似地，具有较小晶格常数的碳化硅材料的第二半导体材料的出现亦将导致n通道晶体管201的通道区236处于拉伸应变。
晶体管200及201的间隔物214、216可为复合间隔物，而其介电衬层214暴露于蚀刻步骤时可自然地于其内形成底切。当介电衬层214为氧化硅时，上述蚀刻将可为一氢氟酸蚀刻，此时的结构如图4c中所示。
接着形成高应力薄膜228(或238)于如图4d中晶体管200及201上。虽未显示，但可如前述图3g中所图标，于n通道晶体管及p通道晶体管上可形成有不同的膜层。于另一实施例中，此高应力薄膜可仅形成于晶体管200(或201)其中之一上。

Claims (23)

1.一种半导体组件，其特征在于包括：
一栅极介电层，覆盖于一通道区上；
一源极区及一汲极区，位于该通道区的对称侧，其中该通道区包含有第一半导体材料而该源极区及汲极区包含有第二半导体材料；
一闸电极，覆盖于该栅极介电层上；以及
一第一间隔物及一第二间隔物，形成于该闸电极两侧上，其中所述的间隔物各包含有邻近于该通道区的一空隙。
2.根据权利要求1所述的半导体组件，其特征在于：更包括一高应力膜层，覆盖于该闸电极与所述的间隔物上。
3.根据权利要求2所述的半导体组件，其特征在于：该空隙减低了该高应力膜层对于该通道区的影响。
4.根据权利要求2所述的半导体组件，其特征在于：该高应力膜层具有介于0.5～4Gpa的应力。
5.根据权利要求1所述的半导体组件，其特征在于：各间隔物包含一氧化衬层及一间隔物主体。
6.根据权利要求5所述的半导体组件，其特征在于：该空隙是设置于该间隔物的氧化衬层内。
7.根据权利要求1所述的半导体组件，其特征在于：更包括该高应力膜层，覆盖于该闸电极与所述的间隔物上，其中该高应力膜层具有拉伸应力。
8.根据权利要求1所述的半导体组件，其特征在于：更包括该高应力膜层，覆盖于该闸电极与所述的间隔物上，其中该高应力膜层具有压缩应力。
9.一种半导体组件，包括：
一半导体基底；
一第一晶体管，形成于该半导体基底内，其中该第一晶体管具有由第一半导体材料所构成的一第一通道区以及对称地设置于邻近该第一通道区的一第一源极区及一第一汲极区，而该第一源极区及第一汲极区包含与该第一半导体材料晶格不对称的一第二半导体材料；以及
一第二晶体管形成于该半导体基底内且具有异于该第一晶体管的一导电性，其中该第二晶体管具有由该第二半导体材料所构成的第二通道区，该第二晶体管亦具有对称地设置于邻近该第二通道区的一第二源极区及一第二汲极区，而该第二源极区及第二汲极区包含与异于该第二半导体材料的一材料。
10.根据权利要求9所述的半导体组件，其特征在于：更包括一高应力膜层，覆盖于该第一晶体管及第二晶体管上。
11.根据权利要求9所述的半导体组件，其特征在于：该第一晶体管更包括邻近第一闸电极且覆盖于该第一通道区上的一第一间隔物，而该第一间隔物包含形成于其内的一第一空隙，其中该第二晶体管更包括邻近该第二闸电极且覆盖于该第二通道区上的一第二间隔物，而该第二间隔物包括有形成于其内的第二空隙。
12.根据权利要求11所述的半导体组件，其特征在于：该第一间隔物及该第二间隔物分别包括一介电衬层，其中该第一空隙与第二空隙是位于该介电衬层内。
13.根据权利要求9所述的半导体组件，其特征在于：该第一半导体材料具有一第一自然晶格常数，而该第二半导体材料具有一第二自然晶格常数，其中该第二自然晶格常数大于该第一晶格常数。
14.根据权利要求13所述的半导体组件，其特征在于：该第一通道区的至少一部分是处于源极至汲极方向上的压缩应力。
15.根据权利要求9所述的半导体组件，其特征在于：该第二半导体材料向上延伸至高于该第一通道区高度的10～500埃。
16.根据权利要求9所述的半导体组件，其特征在于：该第二通道区的至少一部分是处于源极至汲极方向上的拉伸应力。
17.根据权利要求9所述的半导体组件，其特征在于：更包括一高应力膜层，形成于该第一晶体管及第二晶体管的至少一部分上，其中该高应力薄膜具有介于0.1～1.9Gpa的拉伸应力。
18.根据权利要求9所述的半导体组件，其特征在于：更包括一高应力膜层，形成于该第一晶体管及第二晶体管的至少一部分上，其中该高应力薄膜具有介于0.1～1.9Gpa的压缩应力。
19.根据权利要求9所述的半导体组件，其特征在于：更包括形成于该第一晶体管的至少一部分上的一高应力膜层以及形成于第二晶体管上的一第二高应力膜层，其中该第一高应力薄膜具有异于该第二高应力膜层的应力。
20.根据权利要求9所述的半导体组件，其特征在于：该第一晶体管包含一p通道晶体管而该第二晶体管则包含一n通道晶体管。
21.根据权利要求20所述的半导体组件，其特征在于：更包括一高应力膜层，形成于该第一晶体管上，其中该高应力膜层具有压缩应力。
22.根据权利要求21所述的半导体组件，其特征在于：更包括一第二高应力膜层，形成于该第二晶体管上，其中该第二高应力膜层具有拉伸应力。
23.根据权利要求20所述的半导体组件，其特征在于：更包括一高应力膜层，形成于该第二晶体管上，其中该高应力膜层具有拉伸应力。
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