CN203536411U - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
- Publication number
- CN203536411U CN203536411U CN201320597022.1U CN201320597022U CN203536411U CN 203536411 U CN203536411 U CN 203536411U CN 201320597022 U CN201320597022 U CN 201320597022U CN 203536411 U CN203536411 U CN 203536411U
- Authority
- CN
- China
- Prior art keywords
- chip
- lead frame
- fin
- pins
- framework
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
The utility model discloses a semiconductor packaging structure. The semiconductor packaging structure comprises a heat sink frame and a lead wire frame. The heat sink frame is connected with a heat sink, and a chip is bonded to a chip seat of the lead wire frame. The heat sink and the chip are connected by bonding material. The lead wire frame is provided with first pins, and the heat sink frame is provided with second pins and third pins. The second pins and the third pins are arranged on the heat sink. The first pins are connected with an electrode on the bottom of the chip seat as a current input terminal. Three second pins of the heat sink frame are connected with an electrode on the upper surface of the chip as a current output terminal. The third pins of the heat sink frame are welded with a wire as a current control terminal. According to the semiconductor packaging structure provided by the utility model, the use of wires is greatly reduced, and the operation procedures are decreased, thereby accelerating the heat radiation.
Description
Technical field
The utility model belongs to semiconductor packages field, is specifically related to a kind of semiconductor package.
Background technology
In the last few years, the integrated level of semiconductor device was more and more higher, and its memory space, conversion speed and power develops rapidly, but volume is more and more less, and this trend has been accelerated the high speed development of semiconductor integrated circuit.Wherein, lead frame is the skeleton of semiconductor integrated circuit, lead frame is as the chip carrier of integrated circuit or discrete device, it is a kind of electrical connection that realizes chip internal circuit exit and outer lead by means of bonding gold wire, the key structure part that forms electric loop, it has played the function served as bridge being connected with outer lead.Lead frame is mainly comprised of two parts: chip carrier and pin.Wherein chip carrier provides mechanical support at encapsulation process meta chip, and pin is to connect chip to arrive the electric path outside encapsulation.The function of lead frame is apparent, and first it has played the supporting role of encasing electronic components, prevent simultaneously resin lead-in wire between gush out suddenly, for plastics provide support; Secondly it makes chip be connected to substrate, and electricity and the passage of heat of chip wiring board is provided.Integrated circuit in use, inevitably can produce heat, especially the larger circuit of power consumption, the heat producing just more strengthens, therefore when work, just require lead frame must there is good thermal conductivity, otherwise at work will be because heat is compared with large and can not exhale in time and burn out chip.The major function of lead frame is for integrated circuit (IC) chip provides mechanical support carrier, and connects integrated circuit external circuit as conducting medium, transmits the signal of telecommunication, and together with encapsulating material, the heat producing while outwards distributing chip operation.
Existing lead frame dispels the heat by fin, but shortcoming is because pin on chip is too much, causes dissipation of heat excessively slow, and the combination of existing lead frame and fin simultaneously also has a lot of other defects, such as: in conjunction with inaccuracy, inefficiency etc.
A kind of heat-dissipation packaging structure of lead frame is disclosed in Chinese utility model patent specification CN201629305U, comprise a lead frame and fin, it is characterized in that: described lead frame surrounding offers through hole and described through hole and is engaged in and on fin, offers projection, described lead frame and fin via through holes and projection punching press engagement connection.Described encapsulating structure is by this mode of projection punching press engagement connection, and heat sinking function is limited.
In Chinese utility model patent specification CN202394951U, circuit lead frame fin is disclosed, circuit lead frame fin of the present utility model, at middle part, lamellar body bottom surface, establish a groove, in groove, be provided with one and mate consistent mold insert, silver coating on the outer surface of mold insert with groove.Described circuit lead frame fin heat sinking function is limited.
Utility model content
The utility model provides a kind of semiconductor package, a kind ofly constructs clear succinct, semiconductor package that heat sinking function is good.
The utility model provides a kind of semiconductor package, comprise fin framework and lead frame, described fin framework is connected with fin, on the chip carrier of described lead frame, post chip, described fin and chip are by linking together in conjunction with material, described lead frame is provided with the first pin, and described fin framework is provided with the second pin and three-prong.
Wherein, on described lead frame, 4 the first pins are connected with chip carrier bottom electrode, are current input terminal; 3 the second pins on fin framework are connected with chip upper surface electrode, are current output terminal; Three-prong welding lead on fin framework is current controling end.
Preferably, superimposed for the exact position of control lead frame and fin framework, described lead frame is provided with location notch, and described fin framework is provided with angle.
Preferably, for chip carrier is connected and improves bonding strength with corresponding framework with fin, on described lead frame and fin framework, be respectively equipped with first connecting rod and second connecting rod.
Preferably, described fin framework is provided with for balance fin and stand on the feet on chip.
Preferably, in order to prevent from cannot distinguishing when mounted the pin position of each pin, semiconductor is anti-loaded,, described lead frame is provided with pin position identifying hole.
The utility model at least has the following advantages:
1) the second pin, three-prong are arranged on above fin, the use that has reduced wire has reduced work flow and has accelerated heat radiation, has reduced the use of second connecting rod simultaneously, has solved follow-up injection mo(u)lding and second connecting rod cutting problem.
2) the first pin is connected with chip carrier bottom electrode, is current input terminal; 3 the second pins on fin framework are connected with chip upper surface electrode, are current output terminal; Three-prong welding lead on fin framework is current controling end; Greatly reduce the application of wire, and then reduced the loss of heat.
3), by location notch and angle, can accurately control the position folded of lead frame and fin framework.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the utility model semiconductor package structural representation;
Fig. 2 is the utility model lead frame structure schematic diagram;
Fig. 3 is the utility model lead frame end view;
Fig. 4 is the utility model half fin frame structure schematic diagram;
Fig. 5 is the utility model fin frame side view.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
Referring to figs. 1 to Fig. 5, a kind of semiconductor package, comprise fin framework 2 and lead frame 1, described fin framework 2 is connected with fin 4, on the chip carrier 21 of described lead frame 1, post chip 3, described fin 4 and chip 3 are by linking together in conjunction with material 5, described lead frame 1 is provided with the first pin two 2, location notch 25, first connecting rod 27 and pin position identifying hole 26, described fin framework 2 is provided with the second pin 43, three-prong 44, angle 48, second connecting rod 46 and feet 47, on described lead frame 1,4 the first pin twos 2 are connected with chip carrier 21 bottom electrodes, for current input terminal, 3 the second pins 43 on fin framework 2 are connected with chip 3 upper surface electrodes, are current output terminal, three-prong 44 welding leads (not shown) on fin framework 2 are current controling end.
Above content is in conjunction with concrete preferred implementation further detailed description of the utility model, can not assert that concrete enforcement of the present utility model is confined to these explanations.For the utility model person of an ordinary skill in the technical field, without departing from the concept of the premise utility, can also make some simple deduction or replace, all should be considered as belonging to protection range of the present utility model.
Claims (6)
1. a semiconductor package, comprise fin framework and lead frame, described fin framework is connected with fin, on the chip carrier of described lead frame, post chip, described fin and chip are by linking together in conjunction with material, it is characterized in that, described lead frame is provided with the first pin, and described fin framework is provided with the second pin and three-prong.
2. a kind of semiconductor package according to claim 1, is characterized in that, on described lead frame, 4 the first pins are connected with chip carrier bottom electrode, are current input terminal; 3 the second pins on fin framework are connected with chip upper surface electrode, are current output terminal; Three-prong welding lead on fin framework is current controling end.
3. a kind of semiconductor package according to claim 2, is characterized in that, described lead frame is provided with location notch, and described fin framework is provided with angle.
4. a kind of semiconductor package according to claim 1, is characterized in that, on described lead frame and fin framework, is respectively equipped with first connecting rod and second connecting rod.
5. a kind of semiconductor package according to claim 1, is characterized in that, described fin framework is provided with for balance fin and stand on the feet on chip.
6. a kind of semiconductor package forming method according to claim 1, is characterized in that, described lead frame is provided with pin position identifying hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320597022.1U CN203536411U (en) | 2013-09-26 | 2013-09-26 | Semiconductor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320597022.1U CN203536411U (en) | 2013-09-26 | 2013-09-26 | Semiconductor packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203536411U true CN203536411U (en) | 2014-04-09 |
Family
ID=50422590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320597022.1U Expired - Lifetime CN203536411U (en) | 2013-09-26 | 2013-09-26 | Semiconductor packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203536411U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531551A (en) * | 2013-09-26 | 2014-01-22 | 杰群电子科技（东莞）有限公司 | Semiconductor packaging structure and forming method thereof |
| CN104600049A (en) * | 2014-12-31 | 2015-05-06 | 杰群电子科技（东莞）有限公司 | Lead frame and chip packing body thereof |
-
2013
- 2013-09-26 CN CN201320597022.1U patent/CN203536411U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531551A (en) * | 2013-09-26 | 2014-01-22 | 杰群电子科技（东莞）有限公司 | Semiconductor packaging structure and forming method thereof |
| WO2015043499A1 (en) * | 2013-09-26 | 2015-04-02 | 杰群电子科技（东莞）有限公司 | Semiconductor encapsulation structure and forming method thereof |
| US9673138B2 (en) | 2013-09-26 | 2017-06-06 | Great Team Backend Foundry (Dongguan), Ltd. | Semiconductor package structure having a heat sink frame connected to a lead frame |
| CN104600049A (en) * | 2014-12-31 | 2015-05-06 | 杰群电子科技（东莞）有限公司 | Lead frame and chip packing body thereof |
| CN104600049B (en) * | 2014-12-31 | 2018-04-17 | 杰群电子科技（东莞）有限公司 | Lead frame and its chip packing-body |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140409 |