CN1992072B - On-chip termination circuit and method for semiconductor memory apparatus - Google Patents
On-chip termination circuit and method for semiconductor memory apparatus Download PDFInfo
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- CN1992072B CN1992072B CN2006101682770A CN200610168277A CN1992072B CN 1992072 B CN1992072 B CN 1992072B CN 2006101682770 A CN2006101682770 A CN 2006101682770A CN 200610168277 A CN200610168277 A CN 200610168277A CN 1992072 B CN1992072 B CN 1992072B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0005—Modifications of input or output impedance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
Abstract
The present invention disclosed an on-die termination circuit for semiconductor memory apparatus includes an ODT (On Die Termination) input driving unit that divides an input voltage on the basis of aresistance ratio according to a first code.
Description
Technical field
The present invention relates to semiconductor storage unit, more particularly, relate to terminal method on (on-die termination) circuit of terminal on the sheet that is used for semiconductor storage unit and the sheet.
Background technology
Generally speaking, when treating to run into another bus with different impedances by the signal that the bus with predetermined impedance transmits, the part of signal can be lost.Therefore, terminal (being called " ODT " hereinafter) technology matches each other the impedance of two buses on the use sheet, reduces the loss of signal by this.
As shown in Figure 1, comprise according to terminating circuit on the sheet of prior art: ODT enter drive 10, it is molded as class likelihood data enter drive, and it is with according to first yard Pcode＜0:N〉resistance ratio be that supply voltage VDDQ is cut apart on the basis, and export the first line voltage P_out; The one ODT controller 20, its relatively first line voltage P_out and reference voltage Vref and count (count) first yard Pcode＜0:N according to this comparative result; ODT output driver 30, it is molded as similar data output driver, it is with according to second yard Ncode＜0:N〉resistance ratio be that supply voltage VDDQ is cut apart on the basis, and export the second line voltage N_out; And the 2nd ODT controller 40, it comes comparison second line voltage N_out and reference voltage Vref and counts this second yard Ncode＜0:N according to comparative result 〉.
When initial operation, ODT enter drive 10 is according to first yard Pcode＜0:N〉initial value export the first line voltage P_out.
Next, an ODT controller 20 relatively the first line voltage P_out and reference voltage Vref and carry out first yard Pcode＜0:N according to comparative result the counting that adds deduct (up ordown-count).
At this moment, first yard Pcode＜0:N of ODT enter drive 10 count pick ups〉and according to first yard Pcode＜0:N of counting the first line voltage P_out to an ODT controller 20 fed back.Then, repeat the output function of the first line voltage P_out of the compare operation of an ODT controller 20 and this ODT enter drive 10.
If the first line voltage P_out and reference voltage Vref meet each other, first of an ODT controller 20 yard Pcode＜0:N then〉counting operation stops, and finishes this ODT and operate.
The operation of ODT output driver 30 and the 2nd ODT controller 40 is same as the operation of an ODT enter drive 10 and an ODT controller 20, therefore omits its explanation at this.
In above-mentioned prior art, at first yard Pcode＜0:N〉and second yard Ncode＜0:N adjustment the time, as the first line voltage P_out and the second line voltage N_out during, need to increase resistance value greater than reference voltage Vref.For this reason, increase by first yard Pcode＜0:N〉value and reduce by second yard Ncode＜0:N value.
At this moment, when the impedance of storer outside (promptly, when the impedance on the input/output terminal of semiconductor storage unit) very high and line voltage is higher than reference voltage continuously, first yard Pcode＜0:N〉value increase continuously and finally become maximal value, so resistance value is substantially near infinitary value (infinite value).Similarly, second yard Ncode＜0:N〉reduce continuously and finally become minimum value, so resistance value is substantially near infinitary value.
Therefore, on according to the sheet of the semiconductor storage unit of prior art, in the terminating circuit, adjust a mistake, promptly maximum first yard Pcode＜0:N owing to sign indicating number appears in external impedance〉and second yard Ncode＜0:N of minimum.So resistance value is near infinitary value, thereby can't realize the accurate data I/O.
Summary of the invention
Embodiments of the invention are in order to solve problem intrinsic in the prior art, and embodiments of the invention provide and can prevent that sign indicating number from adjusting on the wrong sheet that is used for semiconductor storage unit terminal method on the terminating circuit and sheet.
According to embodiments of the invention, terminating circuit on a kind of sheet that is used for semiconductor storage unit comprises: driver element, its reception have at least two sign indicating number, be that input voltage, and the voltage cut apart of output are cut apart in the basis with the resistance ratio according to this yard; And Terminal Control Element on the sheet, its whether meet based on line voltage that reference voltage is counted this sign indicating number according to the resistance ratio of the resistance ratio of driver element and external resistor unit or this sign indicating number of resetting to initial value.
According to embodiments of the invention, terminal method on a kind of sheet that is used for semiconductor storage unit is provided, described semiconductor storage unit comprises external resistor and driver element, this driver element has the resistance ratio of determining according to the sign indicating number with at least two.Terminal method comprises on this sheet: will compare according to line voltage and the reference voltage that the resistance ratio of the resistance ratio of external resistor and driver element is exported; And according to comparative result count this sign indicating number or this sign indicating number of resetting to initial value.
According to another embodiment of the present invention, terminating circuit on a kind of sheet that is used for semiconductor storage unit, comprise: ODT (terminal on the sheet) imports driver element, and it is based on according to having first yard Pcode＜0:N of at least two〉resistance recently cut apart input voltage and export the first line voltage; The one ODT control module, whether it matches each other according to the first line voltage and reference voltage is counted first yard Pcode＜0:N〉or this first yard Pcode＜0:N that reset to first setting value; ODT exports driver element, and it is based on according to first yard Pcode＜0:N〉resistance ratio and according to the second yard Ncode＜0:N that has two at least resistance recently cut apart input voltage and export the second line voltage; And the 2nd ODT control module, whether it matches each other according to the second line voltage and reference voltage is counted second yard Ncode＜0:N〉or the second yard Ncode＜0:N that reset to second setting value.
According to another embodiment of the present invention, terminal method on a kind of sheet that is used for semiconductor storage unit is provided, and described semiconductor storage unit comprises having according to first yard Pcode＜0:N〉the input driver element of the resistance ratio determined and have according to second yard Ncode＜0:N the output driver element of the resistance ratio determined.Terminal method comprises on this sheet: relatively from importing first line voltage and the reference voltage of driver element output; Count first yard Pcode＜0:N according to comparative result〉or the first yard Pcode＜0:N that reset to first setting value; Relatively from exporting second line voltage and the reference voltage of driver element output; And count second yard Ncode＜0:N according to result for the second time relatively〉or the second yard Ncode＜0:N that reset to second setting value.
Description of drawings
Fig. 1 is a block diagram, shows the configuration according to terminating circuit on the sheet that is used for semiconductor storage unit of prior art;
Fig. 2 is a block diagram, shows the configuration according to terminating circuit on the sheet that is used for semiconductor storage unit of the first embodiment of the present invention;
Fig. 3 is a circuit diagram, the configuration of the ODT enter drive in the displayed map 2;
Fig. 4 is a block diagram, the configuration of the ODT controller in the displayed map 2;
Fig. 5 is a circuit diagram, the configuration of the second reset signal generator in the displayed map 4;
Fig. 6 is a sequential chart, shows the signal waveform according to the each several part of the first embodiment of the present invention;
Fig. 7 is a block diagram, shows the configuration of terminating circuit on the sheet that is used for semiconductor storage unit according to a second embodiment of the present invention;
Fig. 8 is a circuit diagram, the configuration of the ODT enter drive in the displayed map 7;
Fig. 9 is a circuit diagram, the configuration of first controller in the displayed map 7;
Figure 10 is a circuit diagram, the configuration of the ODT output driver in the displayed map 7;
Figure 11 is a circuit diagram, the configuration of second controller in the displayed map 7;
Figure 12 is a sequential chart, shows the first yard Pcode＜0:N that relate to according to a second embodiment of the present invention〉signal waveform adjusted; And
Figure 13 is a sequential chart, shows the second yard Ncode＜0:N that relate to according to a second embodiment of the present invention〉signal waveform adjusted.
Embodiment
Hereinafter, be used on the sheet of semiconductor storage unit that the exemplary embodiments of terminal method will be described with reference to the accompanying drawings on the terminating circuit and sheet.
First embodiment
As shown in Figure 2, comprise according to terminating circuit on the sheet that is used for semiconductor storage unit of the embodiment of the invention: ODT enter drive 50, its reception have sign indicating number Pcode＜0:N of at least two 〉, based on according to this yard Pcode＜0:N resistance recently cut apart input voltage and export this voltage through cutting apart; And ODT controller 60, whether it meets reference voltage Vref according to line voltage P_out is come count code Pcode＜0:N〉or this yard Pcode＜0:N that resets to initial value, its neutral voltage P_out is according to the resistance ratio of ODT enter drive 50 and the resistance ratio of external resistor ZQ.
As shown in Figure 3, ODT enter drive 50 comprises: a plurality of transistors (P0 to Pn), its be coupled to power supply terminal VDDQ and according to sign indicating number Pcode＜0:N and conducting; And a plurality of resistors (NR0 to NRn), it is coupling between a plurality of transistors (P0 to Pn) and the ground terminal VSSQ respectively.
As shown in Figure 4, ODT controller 60 comprises: first comparer 61, and its alternative line voltage P_out and reference voltage Vref are also exported compare result signal cmp_out according to this comparative result; Second comparer 62 is according to sign indicating number Pcode＜0:N〉come output code count end signal code_end with compare result signal cmp_out; Internal clock generator 63 is counted end signal code_end according to external clock CLK and yardage and is produced internal clocking CLK_i; The second reset signal generator 64 is according to sign indicating number Pcode＜0:N 〉, internal clocking CLK_i and reset signal RST produce the second reset signal C_RST; And code controller 65, according to internal clocking CLK_i and the second reset signal C_RST counts or yard Pcode＜0:N that resets.
First comparer 61 is configured to when line voltage P_out and reference voltage Vref meet each other, enables compare result signal cmp_out to for example high level.
Second comparer 62 be configured to compare result signal cmp_out be enabled or the forbidden state of this compare result signal cmp_out in, as sign indicating number Pcode＜0:N〉when reaching setting value, enable code count end signal code_end is to high level for example.
Setting value can be a yard Pcode＜0:N〉maximal value and at least one in the minimum value.This maximal value is the situation of " 1 " (height) corresponding to all, and this minimum value is the situation of " 0 " (low) corresponding to all positions.
Internal clock generator 63 comprises: the first reverser IV1, its receiving code count end signal code_end; The one NAND door ND1, it receives output and the external clock CLK of the first reverser IV1; And the second reverser IV2, it receives output and the output internal clocking CLK_i of a NAND door ND1.
The second reset signal generator 64 comprises logical circuit, and it is as a sign indicating number Pcode＜0:N〉all positions have identical value or reset signal RST when being enabled, enable this second reset signal C_RST.
As shown in Figure 5, the logical circuit of the second reset signal generator 64 can comprise: XNOR door XNOR1, its receiving code Pcode＜0:N 〉; The 3rd reverser IV3, it receives internal clocking CLK_i; The 2nd NAND door ND2, it receives the output of XNOR door XNOR1 and the output of the 3rd reverser IV3; The 4th reverser IV4, it receives the output of the 2nd NAND door ND2; NOR door NOR1, it receives output and the reset signal RST of the 4th reverser IV4; And the 5th reverser IV5, its output that receives NOR door NOR1 is also exported the second reset signal C_RST.
Code controller 65 has register, and it comes count code Pcode＜0:N according to this internal clocking CLK_i subsequently〉and according to the second reset signal C_RST yard Pcode＜0:N that resets to initial code.
Now, the operation that description is had above-mentioned configuration according to terminating circuit on the sheet that is used for semiconductor storage unit of first embodiment of the invention.
At first, in initial operation, the default initial code Pcode＜0:N of ODT controller 60 outputs〉to ODT enter drive 50.
Then, P_out inputs to ODT controller 60 with line voltage, and this line voltage P_out is by with according to the initial code Pcode in the ODT enter drive 50＜0:N〉resistance ratio of the resistor that connects and the resistance ratio of external resistor ZQ be that the basis is cut apart supply voltage VDDQ and obtained.
Then, first comparer, 61 alternative line voltage P_out shown in Figure 4 and reference voltage Vref and when it does not meet each other, the compare result signal cmp_out of output low level, as shown in Figure 6.
Then, under the forbidden state of compare result signal cmp_out, as sign indicating number Pcode＜0:N〉when not reaching setting value, second comparer, the 62 disable code count end signal code_end shown in Fig. 4 are to low level, as shown in Figure 6.
Then, counting end signal code_end at yardage is under an embargo under the state of (low level), internal clock generator 63 shown in Fig. 4 will export code controller 65 to as internal clocking CLK_i by the external clock CLK that a NAND door ND1 and the second reverser IV2 postpone, as shown in Figure 6.
Then, as sign indicating number Pcode＜0:N〉all positions have identical value (all position for high or low) and internal clocking CLK_i is in low level or when reset signal RST was enabled, the second reset signal generator 64 described in Fig. 5 enabled the second reset signal C_RST.
Yet, as sign indicating number Pcode＜0:N〉do not reach maximal value (as sign indicating number Pcode＜0:N〉figure place when being 4, for example, 1111) or minimum value (as sign indicating number Pcode＜0:N〉figure place when being 4, for example, 0000) time, sign indicating number Pcode＜0:N〉all positions do not have identical value.In this case, the second reset signal generator 64 described in Fig. 5 keeps the second reset signal C_RST in illegal state, as shown in Figure 6.
Therefore, the code controller 65 shown in Fig. 4 is under the forbidden state of the second reset signal C_RST, according to internal clocking CLK_i count code Pcode＜0:N sequentially 〉, as shown in Figure 6.
At this moment, according to by count code Pcode＜0:N sequentially〉the line voltage P_out of the resistance ratio of the ODT enter drive 50 that obtained and the resistance ratio of external resistor ZQ (Fig. 3) fed back to first comparer 61 among Fig. 4 continuously.Then, the internal clocking CLK_i that will produce by the operation of first comparer 61, second comparer 62 and internal clock generator 63 among Fig. 4 is supplied to code controller 65.
Simultaneously, even the compare result signal cmp_out from first comparer 61 among Fig. 4 is under an embargo to low level, if the sign indicating number Pcode＜0:N that treats sequentially to count〉reach maximal value or minimum value, then second comparer, the 62 enable code count end signal code_end among Fig. 4 are to high level, as shown in Figure 6.
Then, when yardage was counted end signal code_end and is enabled to high level, the internal clock generator 63 among Fig. 4 kept internal clocking CLK_i in the generation of low level and stop pulse, as shown in Figure 6.
Moreover, as sign indicating number Pcode＜0:N〉reach maximal value or minimum value and have identical value in all positions then, and when internal clocking CLK_i was in low level, the second reset signal generator 64 enabled the second reset signal C_RST to high level, as shown in Figure 6.
Therefore, owing to do not supply with internal clocking CLK_i, code controller 65 stops count code Pcode＜0:N 〉.Moreover, when the second reset signal C_RST is enabled, sign indicating number Pcode＜0:N that code controller 65 is reset and counted at present〉to initial code Pcode＜0:N 〉.
Second embodiment
As shown in Figure 7, comprise according to terminating circuit on the sheet that is used for semiconductor storage unit of second embodiment of the invention: ODT (terminal on the sheet) enter drive 100, it is with according to having first yard Pcode＜0:N of at least two〉resistance ratio be that the basis is cut apart input voltage and exported the first line voltage P_ out; The one ODT controller 200, whether it meets each other according to the first line voltage P_out and reference voltage Vref is counted first yard Pcode＜0:N〉or the first yard Pcode＜0:N that reset to first setting value; ODT output driver 300, it is based on first yard Pcode＜0:N〉resistance ratio and second yard Ncode＜0:N resistance recently cut apart input voltage and export the second line voltage N_out; And the 2nd ODT controller 400, whether it meets each other according to the second line voltage N_out and reference voltage Vref is counted second yard Ncode＜0:N〉or the second yard Ncode＜0:N that reset to second setting value.
The one ODT controller 200 comprises: first comparer 210, and it comes comparison first line voltage P_out and reference voltage Vref and exports the first compare result signal Pcmp_out according to the first enable signal P_en; First register 220, it counts first yard Pcode＜0:N according to the first compare result signal Pcmp_out and reset signal RST〉or the first yard Pcode＜0:N that reset to first setting value; And first controller 230, it is according to the first enable signal P_en and first yard Pcode＜0:N〉produce reset signal RST.
The 2nd ODT controller 400 comprises: second comparer 410, and it comes comparison second line voltage N_out and reference voltage Vref and exports the second compare result signal Ncmp_out according to the second enable signal N_en; Second register 420, it counts second yard Ncode＜0:N according to the second compare result signal Ncmp_out and reset signal RST〉or the second yard Ncode＜0:N that reset to second setting value; And second controller 430, it is according to the second enable signal N_en and second yard Ncode＜0:N〉produce reset signal RST.
As shown in Figure 8, ODT enter drive 100 comprises: a plurality of transistors (P0 to Pn), and it is coupled to power supply terminal VDDQ, and according to first yard Pcode＜0:N and conducting; And a plurality of resistors (NR0 to NRn), it is coupled respectively between a plurality of transistors (P0 to Pn) and the ground terminal VSSQ.
As shown in figure 10, ODT output driver 300 comprises: a plurality of transistors (P0 to Pn), and it is coupled to power supply terminal VDDQ, and according to first yard Pcode＜0:N and conducting; A plurality of resistors (NR0 to NRn), it is coupled respectively to a plurality of transistors (P0 to Pn); A plurality of resistors (PR0 to PRn), it is coupled respectively to a plurality of resistors (NR0 to NRn); A plurality of transistors (N0 to Nn), it is coupling in respectively between a plurality of resistors (PR0 to PRn) and the ground terminal VSSQ, and according to second yard Ncode＜0:N and conducting.
The operation that now description is had above-mentioned configuration according to terminating circuit on the sheet of the semiconductor storage unit of second embodiment of the invention.
At first illustrate and first yard Pcode＜0:N the relevant operation of adjustment.
In initial operation, will default in initial first yard Pcode＜0:N of first register 220〉input to ODT enter drive 100.
Then, ODT enter drive 100 is based on according to first yard Pcode＜0:N〉resistance ratio of the resistor that connects and the resistance of external resistor ZQ recently exports the first line voltage P_out.
Then, first comparer 210 comes the comparison first line voltage P_out and reference voltage Vref and exports the first compare result signal Pcmp_out according to comparative result according to the first enable signal P_en.
At this moment, if the first line voltage P_out does not meet reference voltage Vref, as shown in figure 12, then first comparer 210 is exported the first compare result signal Pcmp_0ut with high level, adds counting to allow first register 220 to carry out.
Then, first register 220 adds first yard Pcode＜0:N of counting according to the first compare result signal Pcmp_out 〉, as shown in figure 12.
At this moment, ODT enter drive 100 is according to the first yard Pcode＜0:N that adds counting〉feed back first line voltage P_out to the first comparer 210, and then first comparer 210 repeats above-mentioned compare operation and according to the output function of the first compare result signal Pcmp_out of compare operation.
Under the state that the first enable signal P_en is enabled, promptly when producing pulse, if the first line voltage P_out and reference voltage Vref meet each other, then first comparer 210 is exported the first compare result signal Pcmp_out with low level.Then, stop the counting operation of first register 220, and finish the ODT operation.
Yet, as shown in figure 12, even first yard Pcode＜0:N〉the counting that adds under the state that the first enable signal P_en is enabled, carry out continuously because the first line voltage P_out and reference voltage Vref do not meet each other, so the first compare result signal Pcmp_out keeps high level.Then, first yard Pcode＜0:N〉reach maximal value (11111), and the first enable signal P_en is under an embargo.
Therefore, first controller 230 of Fig. 9 receives the first yard Pcode＜0:N that reaches maximal value (11111)〉and forbid to the low level first enable signal P_en, and enable reset signal RST to high level.
Then, first register 220 is according to the reset signal RST first yard Pcode＜0:N that reset〉first yard Pcode＜0:N being reset to first setting value and storage 〉.
Therefore, the impedance on the I/O end of semiconductor storage unit is very high, thus prevent sign indicating number adjust wrong and thus with first yard Pcode＜0:N save as maximal value.
Then explanation relates to second yard Ncode＜0:N〉operation adjusted.
In initial operation, with the initial second yard Pcode＜0:N that defaults in second register 420〉input to ODT output driver 300.
Then, ODT output driver 300 is with according to second yard Ncode＜0:N〉resistance ratio of the resistor that connects is that the second line voltage N_out is exported on the basis.
Then, second comparer 410 comes comparison second line voltage N_out and the reference voltage Vref according to the second enable signal N_en, and exports the second compare result signal Ncmp_out according to comparative result.
When the second line voltage N_out did not meet reference voltage Vref, second comparer 410 was exported the second compare result signal Ncmp_out with low level, subtracted counting to allow second register 420 to carry out, as shown in figure 13.
Then, second register 420 subtracts second yard Ncode＜0:N of counting according to the second compare result signal Ncmp_out 〉, as shown in figure 13.
At this moment, ODT output driver 300 is according to through subtracting second yard Ncode＜0:N of counting〉feed back second line voltage N_out to the second comparer 410, and then second comparer 410 repeats above-mentioned compare operation and according to the output function of the second compare result signal Ncmp_out of compare operation.
Under the state that the second enable signal N_en is enabled, promptly when producing pulse, if the second line voltage N_out and reference voltage Vref meet each other, then second comparer 410 is exported the second compare result signal Ncmp_out with high level.Then, stop the counting operation of second register 420, and finish the ODT operation.
Yet, as shown in figure 13, even under the state that the second enable signal N_en is enabled, carry out second yard Ncode＜0:N continuously〉subtract counting because the second line voltage N_out and reference voltage Vref do not meet each other, so the second compare result signal Ncmp_out keeps low level.Then, second yard Ncode＜0:N〉reach minimum value (00000), and the second enable signal N_en is under an embargo.
Therefore, second controller 430 of Figure 11 receives the second yard Ncode＜0:N that reaches minimum value (00000)〉and forbid to the low level second enable signal N_en, and enable reset signal RST to high level.
Then, second register 420 is according to the reset signal RST second yard Ncode＜0:N that reset〉to second setting value and store second yard Ncode＜0:N through resetting.
Therefore, the impedance on the I/O end of semiconductor storage unit is very high, and therefore prevent sign indicating number adjust wrong and thus with second yard Ncode＜0:N save as minimum value.
At this moment, relate to first yard Pcode＜0:N〉first setting value with relate to second yard Ncode＜0:N second setting value set by the emulation or the operational testing of semiconductor storage unit, or be set at the sign indicating number initial value, even the impedance on the I/O end of feasible semiconductor storage unit is high, still can carry out the data I/O.
Obviously, to those skilled in the art, under the situation that does not depart from spirit of the present invention and scope, various modifications are possible with changing.Therefore, will be appreciated that above-mentioned all embodiment are only unrestricted for example.Scope of the present invention by claims but not instructions limit, and therefore, contained all changes and modification in the claim scope by claim, and these change and being equal to of revising.
Can prevent code value adjustment mistake according to terminating circuit and method on the sheet that is used for semiconductor storage unit of the embodiment of the invention, to allow normal data input and output.Therefore, can improve the reliability of storage operation.
Claims (36)
1. terminating circuit on the sheet that is used for semiconductor storage unit comprises:
Driver element, it is configured to receive sign indicating number with at least two, be that the basis is cut apart input voltage and exported described voltage through cutting apart with the resistance ratio according to the described driver element of described sign indicating number; And
Terminal Control Element on the sheet, its be configured to based on the line voltage according to the resistance ratio of the described resistance ratio of described driver element and external resistor unit whether meet that reference voltage is counted described sign indicating number or the described sign indicating number of resetting to initial value.
2. go up terminating circuit for as claimed in claim 1,
Wherein said driver element comprises:
A plurality of changeover modules, it is coupled to power supply terminal, and according to described sign indicating number and conducting, and
A plurality of resistors, it is coupling in respectively between corresponding and the ground terminal VSSQ in described a plurality of changeover module.
3. go up terminating circuit for as claimed in claim 1,
Going up Terminal Control Element for wherein said comprises:
First comparer, it is configured to more described line voltage and described reference voltage and exports compare result signal,
Second comparer, it is configured to come the output code count end signal according to described sign indicating number with described compare result signal,
Internal clock generator, it is configured to count end signal according to external clock and described yardage and produces internal clocking,
The second reset signal generator, it is configured to produce second reset signal according to described sign indicating number, described internal clocking and reset signal, and
Code controller, it is configured to according to described internal clocking and the described second reset signal described sign indicating number of counting or reset.
4. go up terminating circuit for as claimed in claim 3,
Wherein said first comparator arrangement enables described compare result signal for when described line voltage and described reference voltage are consistent each other.
5. go up terminating circuit for as claimed in claim 3,
Wherein said second comparer is configured to when described compare result signal is enabled, and enable described yardage and count end signal, and under the forbidden state of described compare result signal, described sign indicating number reaches setting value.
6. go up terminating circuit for as claimed in claim 3,
Wherein said internal clock generator comprises:
First reverser, it is configured to receive described yardage and counts end signal and produce output according to it,
Sheffer stroke gate, it is configured to receive the described output of described first reverser and described external clock and produces output according to it, and
Second reverser, it is configured to receive the output of described Sheffer stroke gate and exports described internal clocking.
7. go up terminating circuit for as claimed in claim 3,
The wherein said second reset signal generator is configured to enable described second reset signal when all of described sign indicating number have identical value or when described reset signal is enabled.
8. go up terminating circuit for as claimed in claim 3,
The wherein said second reset signal generator comprises:
Biconditional gate, it is configured to receive described sign indicating number and produces output according to it,
First reverser, it is configured to receive described internal clocking and produces output according to it,
Sheffer stroke gate, it is configured to receive the described output of the described output of described biconditional gate and described first reverser and produces output according to it,
Second reverser, it is configured to receive the described output of described first Sheffer stroke gate and produces output according to it,
Rejection gate, it is configured to receive the described output of described second reverser and described reset signal and produces output according to it, and
The 3rd reverser, it is configured to receive the described output and described second reset signal of described rejection gate.
9. go up terminating circuit for as claimed in claim 3,
Wherein said code controller comprises register, and it is configured to count described sign indicating number and reset described yard according to described second reset signal according to described internal clocking.
10. terminal method on the sheet that is used for semiconductor storage unit, described semiconductor storage unit comprises external resistor and driver element, described driver element has the resistance ratio of determining according to the sign indicating number with at least two, goes up terminal method for described and comprises:
To compare according to line voltage and the reference voltage that the described resistance ratio of the resistance ratio of described external resistor and described driver element is exported; And
Result according to described comparison counts described sign indicating number or resets described yard to initial value.
11. as terminal method on the sheet of claim 10,
Wherein counting described sign indicating number according to the result of described comparison comprises: do not reach under the state of setting value at described sign indicating number, when described line voltage and described reference voltage do not meet each other, count described yard.
12. as terminal method on the sheet of claim 11,
Wherein said setting value comprises at least one in the minimum value of the maximal value of described sign indicating number or described sign indicating number.
13. as terminal method on the sheet of claim 10,
Wherein comprise according to reset described sign indicating number of described comparative result: the value at described sign indicating number reaches under the state of setting value, when described line voltage and described reference voltage do not meet each other, and the described yard extremely described initial value of resetting.
14. as terminal method on the sheet of claim 13, wherein said setting value comprises at least one in the minimum value of the maximal value of described sign indicating number or described sign indicating number.
15. terminating circuit on the sheet that is used for semiconductor storage unit, it comprises:
ODT (terminal on the sheet) imports driver element, and it is configured to being that the basis is cut apart input voltage and exported the first line voltage according to having two first yard resistance ratio at least;
The one ODT control module, its be configured to according to the described first line voltage and reference voltage whether meet each other count described first yard or reset described first yard to first setting value;
ODT exports driver element, and it is configured to recently cut apart input voltage and export the second line voltage according to described first yard described resistance ratio with according to second yard resistance with at least two based on described; And
The 2nd ODT control module, its be configured to according to the described second line voltage and described reference voltage whether match each other count described second yard or reset described second yard to second setting value.
16. as terminating circuit on the sheet of claim 15,
Wherein said ODT input driver element comprises:
A plurality of changeover modules, it is coupled to power supply terminal and according to described first yard and conducting, and
A plurality of resistors, it is coupling in respectively between corresponding and the ground terminal VSSQ in described a plurality of changeover module.
17. as terminating circuit on the sheet of claim 15,
A wherein said ODT control module comprises:
Comparer, it is configured to come more described first line voltage and described reference voltage and export first compare result signal according to first enable signal,
Register, it is configured to count described first yard Pcode＜0:N according to described first compare result signal and reset signal〉or the described first yard Pcode＜0:N that reset to described first setting value, and
Controller, it is configured to produce described reset signal according to described first enable signal and described first yard.
18. as terminating circuit on the sheet of claim 17,
Wherein said comparator arrangement is described first compare result signal of output, with when the described first line voltage and described reference voltage are inconsistent, allows described register execution to add counting.
19. as terminating circuit on the sheet of claim 17,
Wherein said controller is configured to when reaching maximal value for described first yard, enable described reset signal under the forbidden state of described first enable signal.
20. as terminating circuit on the sheet of claim 17,
Wherein said first enable signal comprises pulse signal.
21. as terminating circuit on the sheet of claim 17,
Wherein said controller comprises:
Reverser, it is configured to receive described first enable signal and produces output according to it, and
Biconditional gate, it is configured to receive the described output of described reverser and described first yard.
22. as terminating circuit on the sheet of claim 15,
Wherein said ODT output driver element comprises:
The first transistor group, it has a plurality of transistors, and described a plurality of transistors couple are to power supply terminal and according to described second yard and conducting,
The first resistor group, it has a plurality of resistors, and described a plurality of resistors are coupling in respectively between the transistor AND gate ground terminal of described the first transistor group,
The second resistor group, it has a plurality of resistors, and described a plurality of resistors are coupled respectively to the described resistor of the described first resistor group, and
The transistor seconds group, it has a plurality of transistors, and described a plurality of transistors are coupling in respectively between the described resistor and described ground terminal of the described second resistor group, and according to described second yard and conducting.
23. as terminating circuit on the sheet of claim 15,
Wherein said the 2nd ODT control module comprises:
Comparer, it is configured to come more described second line voltage and described reference voltage and export second compare result signal according to second enable signal,
Register, its be configured to according to described second compare result signal and reset signal count described second yard or reset described second yard to second setting value, and
Controller, it is configured to produce reset signal according to described second enable signal and described second yard.
24. as terminating circuit on the sheet of claim 23,
Wherein said comparator arrangement is described second compare result signal of output, with when the described second line voltage and described reference voltage are inconsistent, allows described register execution subtracting counting.
25. as terminating circuit on the sheet of claim 23,
Wherein said controller is configured to when reaching minimum value for described second yard, enable described reset signal under the forbidden state of described second enable signal.
26. as terminating circuit on the sheet of claim 23,
Wherein said second enable signal comprises pulse signal.
27. as terminating circuit on the sheet of claim 23,
Wherein said controller comprises:
First reverser, it is configured to receive described second enable signal and produces output according to it,
Second reverser, it is configured to receive respectively described second yard position and produces output respectively according to the quantity of described second reverser, and the quantity of described second reverser is corresponding to the quantity of described second yard position, and
Biconditional gate, it receives the output of described first reverser and second reverser.
28. as terminating circuit on the sheet of claim 15,
Wherein said first setting value and described second setting value are set by the simulation or the operational testing of described semiconductor storage unit.
29. terminal method on the sheet that is used for semiconductor storage unit, described semiconductor storage unit comprises having according to first yard Pcode＜0:N〉the input driver element of the resistance ratio determined and have output driver element according to second yard resistance ratio of determining, terminal method comprises on described:
Relatively from first line voltage and the reference voltage of described input driver element output;
According to the comparative result of the described comparison of first line voltage of being exported and described reference voltage count described first yard or reset described first yard to first setting value;
Relatively from the second line voltage and the described reference voltage of described output driver element output; And
According to the comparative result of the described second line voltage of output and the described comparison of described reference voltage count described second yard or reset described second yard to second setting value.
30. as terminal method on the sheet of claim 29,
Wherein counting described first yard comprises: under the state that first enable signal is enabled, when the described first line voltage and described reference voltage do not meet each other, count described first yard.
31. as terminal method on the sheet of claim 30,
Wherein said first enable signal comprises pulse signal.
32. as terminal method on the sheet of claim 29,
Wherein reset described first yard and comprise to described first setting value: under the forbidden state of described first enable signal, when reaching maximal value for described first yard, reset described first yard to described first setting value.
33. as terminal method on the sheet of claim 29,
Wherein counting described second yard comprises: under the state that second enable signal is enabled, when the described second line voltage and described reference voltage do not meet each other, count described second yard.
34. as terminal method on the sheet of claim 33,
Wherein said second enable signal comprises pulse signal.
35. as terminal method on the sheet of claim 29,
Wherein reset described second yard and comprise to described second setting value: under the forbidden state of described second enable signal, when reaching minimum value for described second yard, reset described second yard to described second setting value.
36. as terminal method on the sheet of claim 29,
Wherein said first setting value and described second setting value are set by the simulation or the operational testing of described semiconductor storage unit.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050130344 | 2005-12-27 | ||
| KR10-2005-0130345 | 2005-12-27 | ||
| KR1020050130345A KR100656461B1 (en) | 2005-12-27 | 2005-12-27 | Apparatus and method for on die termination of semiconductor memory |
| KR10-2005-0130344 | 2005-12-27 | ||
| KR1020050130345 | 2005-12-27 | ||
| KR1020050130344A KR100656456B1 (en) | 2005-12-27 | 2005-12-27 | Apparatus and method for on die termination of semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1992072A CN1992072A (en) | 2007-07-04 |
| CN1992072B true CN1992072B (en) | 2010-05-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101682770A Expired - Fee Related CN1992072B (en) | 2005-12-27 | 2006-12-25 | On-chip termination circuit and method for semiconductor memory apparatus |
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| Country | Link |
|---|---|
| KR (1) | KR100656456B1 (en) |
| CN (1) | CN1992072B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100681881B1 (en) | 2006-04-06 | 2007-02-15 | 주식회사 하이닉스반도체 | Apparatus and method for on die termination of semiconductor memory |
| KR100821585B1 (en) | 2007-03-12 | 2008-04-15 | 주식회사 하이닉스반도체 | Circuit for on die termination of semiconductor memory apparatus |
| JP2009246725A (en) * | 2008-03-31 | 2009-10-22 | Renesas Technology Corp | Semiconductor device equipped with impedance adjustable output buffer |
| KR20100104686A (en) | 2009-03-18 | 2010-09-29 | 삼성전자주식회사 | Semiconductor device capable of impendence calibration code transmission line test |
| KR101841622B1 (en) * | 2010-11-04 | 2018-05-04 | 삼성전자주식회사 | Nonvolatile memory device having on die termination circuit and control method thereof |
| KR20190075788A (en) * | 2017-12-21 | 2019-07-01 | 삼성전자주식회사 | Storage device including calibration device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5920518A (en) * | 1997-02-11 | 1999-07-06 | Micron Technology, Inc. | Synchronous clock generator including delay-locked loop |
| CN1259743A (en) * | 1998-12-17 | 2000-07-12 | 西门子公司 | Adjustable strength driving circuit and adjusting method |
-
2005
- 2005-12-27 KR KR1020050130344A patent/KR100656456B1/en active IP Right Grant
-
2006
- 2006-12-25 CN CN2006101682770A patent/CN1992072B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5920518A (en) * | 1997-02-11 | 1999-07-06 | Micron Technology, Inc. | Synchronous clock generator including delay-locked loop |
| CN1259743A (en) * | 1998-12-17 | 2000-07-12 | 西门子公司 | Adjustable strength driving circuit and adjusting method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1992072A (en) | 2007-07-04 |
| KR100656456B1 (en) | 2006-12-11 |
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