CN1967799A - 一种具有空气间隔的集成电路的制作方法 - Google Patents

一种具有空气间隔的集成电路的制作方法 Download PDF

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CN1967799A
CN1967799A CNA2006101458489A CN200610145848A CN1967799A CN 1967799 A CN1967799 A CN 1967799A CN A2006101458489 A CNA2006101458489 A CN A2006101458489A CN 200610145848 A CN200610145848 A CN 200610145848A CN 1967799 A CN1967799 A CN 1967799A
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dielectric layer
pattern
metal
conductive line
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CN100514597C (zh
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卢火铁
李大为
王光志
杨名声
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United Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures

Abstract

本发明是提供一种具有空气间隔(air gap)的集成电路的制作方法。首先于一基底上形成一底层，并于该底层上形成一第一层金属导线图案。接着于第一层金属导线图案以及底层上形成一介电层，并于该介电层上形成一第二层金属导线图案。随后利用第一层金属导线图案以及第二层金属导线图案作为一蚀刻屏蔽，非等向性蚀刻部分的该介电层以及该底层，以形成复数个凹槽，同时使剩余的介电层构成第二层金属导线图案的支撑结构。最后进行一化学气相沉积(CVD)制程，以于各该凹槽表面以及第二层金属导线图案上沉积一盖层，并封盖各该凹槽，形成复数个空气间隔。

Description

一种具有空气间隔的集成电路的制作方法
本申请是分案申请，原案申请日是2003年11月7日，申请号是200310103485.9，发明创造名称是：一种具有空气间隔的集成电路结构及其制作方法。
技术领域
本发明是提供一种高效能(high performance)集成电路(integratedcircuit，IC)结构，尤指一种具有空气间隔(air gap)的集成电路的制作方法。本发明尤其适用于需要高运作效能以及高积集度的逻辑IC或整合性IC(例如系统整合芯片(system-on-chip，SOC))领域。而本发明形成具有空气间隔的集成电路结构的方法则提供半导体制造业者一可达到量产(massproduction)规模的完整解决方案。
背景技术
随着半导体制造技术的进步，制作于一半导体晶圆上的半导体组件设计尺寸也持续地缩小，并已经演进到深次微米世代。然而，集成电路密度不断地提高的结果，却造成各金属导线间的时间延迟(RC delay)问题对集成电路的运作效能的影响日渐显著，尤其当制程线宽(line width)降到0.15微米以下，甚至0.13微米以下的半导体制程时，时间延迟对组件运作效能所造成的影响更为明显。
金属内联机间的时间延迟可以用金属导线的电阻值(R)与金属导线间的寄生电容(C)的相乘积来表达。目前减少半导体芯片的金属内联机时间延迟现象主要朝两个方向进行：第一是使用电阻值较低的金属材料做为金属导线，第二则是降低各金属导线间的寄生电容，以增加金属内联机的传输速度同时减少电能消耗。
在习知的作法中，降低各金属导线间的寄生电容的方法主要是采用如FSG、HSQ、FLAREKTM或SiLKTM等低介电常数(k＜3)材料。这些低介电常数材料的特性基本上需包括有低介电常数、低表面导电度(surface conductance，surface resistivity＞1015Ω)、低应力(compressive or weak tensile＞30MPa)、优异的机械强度及化学与热稳定性、低吸水性以及制程兼容性(process compatibility)。然而许多低介电常数材料都有严重的可靠度(reliability)以及与金属整合后产生的问题。因此，在新世代的低介电常数材料尚未问世之前，如何以制程技术克服时间延迟所造成的运作效能降低问题，便成为一值得探讨与改进的课题。
由于空气的理想介电常数接近于1，因此使用空气(air)做为金属内联机的绝缘物质，也是降低金属导线间寄生电容的解决方案之一。虽然许多利用空气的低介电常数特性应用于集成电路的技术已经被公布出来，但是大部分却都不具有量产价值。例如在美国专利第4920639号中，Lan Y.K.Yee即揭露一种制作具有空气间隔的集成电路的方法，其作法是先利用光阻作为金属内联机间的暂时介电层，待完成金属内联机的制作后，再利用溶剂去除部分、甚至所有的光阻，而于金属内联机间形成大量的空气间隔。这种作法会使得金属内联机几乎完全被架空，而无法获得足够的支撑，容易造成集成电路受到机械力而损坏。
此外，美国专利第6130151号揭露一种形成空气间隔于金属内联机间的硅氧层内的方法，其作法是先形成硅氧层以及一氮硅层于金属层上，然后经由一微影(photo lithography)制程于氮硅层上定义出复数个开口，再进行一蚀刻制程沿着前述的开口依序蚀刻硅氧层及氮硅层或仅蚀刻硅氧层，以形成空气间隔于硅氧层内。
美国专利第5949143号则揭露一种形成空气间隔于金属内联机间的方法，其作法是先形成一双镶嵌金属内联机于介电层中，然后再沉积一蚀刻终止层(etch stop layer)于金属内联机及介电层之上，但裸露出部分的介电层，最后进行一蚀刻制程完全地去除未被蚀刻终止层覆盖的介电层，以于各该金属联机以及蚀刻终止层之间形成空气间隔。其它诸如美国专利案号5324683、6077767、6083821与5407860等，也都分别揭露各式于金属内联机间形成空气间隔的方法，在此不多赘述。
然而，上述这些习知技术除了制程过于复杂，难以整合之外，同时也面临一些可靠度问题，例如金属内联机无法获得足够的支撑。本发明则可以提供一完整的解决方案，以解决习知技术无法突破的瓶颈，可达到一量产规模。
发明内容
本发明的主要目的在提供一种高操作效能的集成电路结构及其制作方法。
本发明的另一目的在提供一种具有空气间隔以及足够支撑的集成电路结构及其制作方法，以于金属内联机间制作大量的空气间隔，进而达到减少金属内联机的时间延迟的功效。
依据本发明的目的，一种同时具有大量空气间隔以及使内联机金属线路具备足够支撑的高性能集成电路结构首先被揭露出来。该集成电路结构包含有一第一层金属导线图案，形成于一底层上；一第二层金属导线图案，形成于该第一层金属导线图案上方；一支撑结构，形成于该第一层金属导线图案以及该第二层金属导线图案之间，用来支撑该第二层金属导线图案，其中该支撑结构包含有一经过非等向性蚀刻的介电层；以及由一盖层所形成的复数个空气间隔，形成于该第二层金属导线图案之间。
本发明同时揭露一种制作上述高性能集成电路的方法。在本发明的最佳实施例中，该方法首先于一基底上形成一底层，并于该底层上形成一第一层金属导线图案。接着于第一层金属导线图案以及底层上形成一介电层，并于该介电层上形成一第二层金属导线图案。随后利用第一层金属导线图案以及第二层金属导线图案作为一蚀刻屏蔽，非等向性蚀刻部分的该介电层以及该底层，以形成复数个凹槽，同时使剩余的介电层构成第二层金属导线图案的支撑结构。最后进行一化学气相沉积(CVD)制程，以于各该凹槽表面以及第二层金属导线图案上沉积一盖层，并封盖各该凹槽，形成复数个空气间隔。
由于本发明利用金属层图案、或用于定义金属层图案的光阻层作为蚀刻屏蔽，来对金属层图案下方的介电层进行一等向性蚀刻及一非等向性蚀刻，以于金属内联机间形成复数个空气间隔，进而达到减少金属内联机的时间延迟的功效。此外，利用本发明方法所形成的集成电路结构具有使金属内联机或得足够支撑的介电层架构，可以提高集成电路的可靠度。
附图说明
图1为本发明较佳实施例中具有空气间隔或空气悬隔(air bridge)的集成电路结构的剖面示意图；
图2至图6为本发明的较佳实施例中具有空气间隔的集成电路的制作方法示意图；
图7与图8为本发明实施例二的制程方法示意图；
图9与图10为本发明实施例三的制程方法示意图；
图11至图14为制作具有空气间隔的集成电路的制作方法示意图，而此空气间隔是形成于导线间空隙过大的区域内。
符号说明：
10-半导体芯片
11-基底
12-底层
13-第一层金属图案
13a-金属插塞
14-介电层
15-第二层金属
16-光阻层
17-第二层金属图案
17a-虚设图案
17b-侧壁子
18-孔隙
18a-空气间隔
19-盖层
20-光阻层
22a-空气间隔
22b-空气间隔
23a-空气间隔
23b-空气间隔
24-介电层
24a-插塞
26-介电层
26a-插塞
28-介电层
M1-金属图案层
M2-金属图案层
M3-金属图案层
具体实施方式
请参考图1，图1为本发明较佳实施例中具有空气间隔(air gap)或空气悬隔(air bridge)的集成电路结构的剖面示意图。如图1所示，半导体芯片10包含有一基底11，可以为一单晶硅基底或其它半导体基底。在基底11的表面上可以包含有已经制作完成的半导体组件，例如存储单元(memorycell)、MOS晶体管、电阻或电容等等。由于这些组件并非本发明的重点，因此并未显示在图标之中。底层12形成于基底11之上，其中底层12可以为单一介电层所构成，或由多层介电层所构成。三层金属图案层(M1、M2及M3)、各金属插塞24a以及26a以及介电层24、26以及28形成于底层12之上，构成一层叠堆积的金属内联机架构。此处，金属图案层(M1、M2及M3)是指定义于同一层的金属导线图案。定义金属导线图案(M1、M2及M3)以及金属插塞24a以及26a可以利用传统的金属溅镀以及蚀刻技术，介电层24、26以及28则可以利用一般的化学气相沉积或旋转涂布方式形成。
在图1中，空气间隔22a以及22b形成于金属图案层M2之间，并向下延伸至介电层24，甚至更向下延伸至底层12中。空气间隔23a以及23b则形成于金属图案层M3之间，并向下延伸至介电层26。其中空气间隔22a以及22b是由介电层26所包覆形成，并且在空气间隔22b顶部具有一突悬(overhang)封闭结构。空气间隔23a以及23b是由介电层28所包覆形成。空气间隔22a与空气间隔23a呈现连通状态，这是由于形成空气间隔23a的过程中，非等向性蚀刻挖穿原先由介电层26所包覆的空气间隔22a。在本发明的其它实施例中，被挖穿的空气间隔22a可以利用介电层28再次被封闭起来，而形成独立的两个空气间隔22a以及23a。这可以借由调整沉积介电层28时的阶梯覆盖(step coverage)程度来达到。
实施例一
请参考图2至图6，图2至图6为依据本发明具有空气间隔的集成电路结构的制作方法示意图。如图2所示，半导体芯片10包含有一基底11及一底层12位于基底11之上。第一层金属图案13可以经由溅镀、微影及蚀刻等程序形成于底层12之上。接着于第一层金属图案13与底层12上沉积一介电层14，然后经由微影、蚀刻、沉积及化学机械研磨(CMP)等制程，再于介电层14之内制作金属插塞13a。随后形成一金属层15于介电层14及金属插塞13a之上，并于金属层15表面形成一经过定义的光阻层16。光阻层16于金属层15上定义出一第二层金属图案。
接着如图3所示，利用光阻层16为蚀刻屏蔽对金属层15进行蚀刻，以于介电层14及金属插塞13a上方形成一第二层金属图案17，并借由金属插塞13a作为接触插塞(via plug)与第一层金属图案13电连接。随后去除光阻层16。第一金属层图案13与第二层金属图案17可以由铝金属、铝铜合金或铜金属所构成。金属插塞13a可以由钨(W)、钛/氮化钛(Ti/TiN)所构成。介电层14的组成可以是二氧化硅、氟硅玻璃(fluorinated silicate glass，FSG)、或其它利用电浆加强化学气相沉积法(plasma-enhanced chemicalvapor deposition，PECVD)或高密度电浆化学气相沉积法(high-densityplasma chemical vapor deposition，HDPCVD)所形成的介电层。
需强调的是，本发明的具有空气间隔的集成电路结构亦可应用于铜金属内联机结构中。此时，上述的第一层金属图案13、金属插塞13a及第二层金属图案17亦可利用双镶嵌(dual damascene)制程形成于介电层之中。双镶嵌制程为习知该项技艺者所熟知的技术，因此不再赘述。习知该项技艺者应可参考本发明而将本发明轻易地应用在铜制程上。
如图4所示，以第二层金属图案17作为蚀刻屏蔽，进行一非等向性(anisotropic)蚀刻制程，垂直向下去除一预定深度未被第二层金属图案17覆盖的介电层14，以形成复数个凹槽18于介电层14之内。其中，借由控制蚀刻的时间(time-mode)可以适当地调整延伸至底层12中的凹槽深度，但此一凹槽深度以不影响组件的电性表现为原则。
接着如图5所示，对凹槽18内的介电层14进行一等向性(isotropic)干蚀刻或湿蚀刻制程，以进一步地扩大凹槽18的面积，形成一底切轮廓(undercut profile)于第二层金属图案17之下。需注意的是，前述的该等向性蚀刻制程是为一选择性的步骤，亦即该等向性蚀刻制程亦可省略不进行，另一方面，进行该等向性蚀刻制程的主要目的乃是选择性地扩大凹槽18的面积，因此只部分移除位于第二层金属图案17下的介电层14。用于支撑第二层金属图案17的支撑结构包含有介电层14及金属插塞13a。
如图5以及图6所示，接着进行一化学气相沉积(CVD)制程，于凹槽18及第二层金属导线图案17的表面沉积一盖层(cap layer)19，并封盖住凹槽18而形成复数个空气间隔18a。值得注意的是，在沉积盖层19时，须尽量经由调整化学气相沉积的制程参数而让盖层19于第二层金属导线图案17的角落部分形成突悬(overhang)，以快速地将凹槽18封盖住，进而减少盖层19沉积入凹槽18内的情形。
实施例二
请参阅图7与图8，图7与图8为本发明的另一实施例的制程方法示意图。其中，图7是延续图2的制程步骤，经过曝光、显影及蚀刻等制程，于介电层14及金属插塞13a上形成一第二层金属图案17，并且不移除用于定义第二层金属图案17的光阻层16。如图8所示，本发明方法可以光阻层16作为蚀刻屏蔽，依序进行图四与图五所示的非等向性蚀刻及等向性蚀刻制程，在蚀刻金属层15之后随即于介电层14内蚀刻形成复数个凹槽18，并凹槽18形成一底切轮廓(undercut profile)于第二层金属图案17之下。也就是说，在完成第二层金属图案17之后，随即调整蚀刻气体的成份，以同时(in-situ)蚀刻介电层14。最后才去除光阻层16，并进行图6所示的化学气相沉积(CVD)制程，于凹槽18及第二层金属导线图案17的表面沉积一盖层(cap layer)19，封盖住凹槽18而形成复数个空气间隔18a。
实施例三
依据本发明所揭露于图4、图5与图8所示的制作空气间隔18a的制程方法，亦可实施于多重金属内联机制程的任一层金属图案层或每一层金属图案层。请参阅图9，连续做完三层金属图案层(M1、M2及M3)以及各金属插塞13a之后，再利用最上面的金属图案层M3作为蚀刻屏蔽，并利用金属图案层M2、金属图案层M1作为蚀刻停止层，以进行一非等向性蚀刻，而于多重金属内联机间制作大量的空气凹槽18。此外，如图10所示，本发明可在底层12中加入一阻绝层(stop layer)12a，如此一来便可避免过度蚀刻，而破坏底层12下的组件。
实施例四
为了避免发生当如图10中第二层金属图案17的导线间空隙过大，以至于不论如何调整化学气相沉积制程的制程参数，盖层19皆会沉积入凹槽18之内，因而发生空气间隔18a的体积减少的情况，可以在金属导线间空隙较大的区域上形成虚设图案(dummy pattern)。请参阅图11至图14，图11至图14为于导线间空隙过大的金属内联机制作空气间隔的示意图。首先如图11所示，当第二层金属图案17的导线间空隙过大，本发明可适当地加入虚设图案(dummy pattern)17a于过大的导线间空隙中的介电层14之上。其中，虚设图案17a的形成方法可在第二层金属图案17的光罩的布局(layout)中加入复数个虚设图案，使第二层金属图案17与虚设图案17a同时形成于介电层14之上，借此缩小第二层金属图案17的导线间空隙。接着再依序进行图4至图6所示的非等向性蚀刻、等向性蚀刻及化学气相沉积制程，以于介电层14内形成复数个空气间隔18a，如图12所示。
如图13所示，当第二层金属图案17的导线间空隙较大时，本发明的方法也可在形成第二层金属图案17之后，先沉积一薄膜层(未显示)于第二层金属图案17之上，再利用一蚀刻制程以于第二层金属图案17的侧边形成侧壁子(spacer)17b。其中，形成侧壁子17b的方法为习知该项技艺者所熟知，因此不再赘述。由于侧壁子17b的形成，因而缩小了导线间空隙。接着再依序进行图三至图五所示的非等向性蚀刻、等向性蚀刻及化学气相沉积制程，以于介电层14内形成复数个空气间隔18a。
如图14所示，当第二层金属图案17的导线间空隙过大，本发明的方法亦可于形成完第二层金属图案17之后，再利用一光阻层20覆盖于导线间空隙较大的第二层金属图案17之上，而仅裸露出导线间空隙较小的第二层金属图案17，或利用光阻层20而于导线间空隙过大的第二层金属图案17间形成至少一个虚设图案。接着再依序进行图4与图5所示的非等向性蚀刻、等向性蚀刻，以于未被光阻层20覆盖的介电层14内形成复数个凹槽18。然后移除光阻层20，并进行图6所示的化学气相沉积制程，以于介电层14内形成复数个空气间隔18a。
相较于习知的方法，本发明的特点乃是直接利用金属导线图案、或用于定义金属导线图案的光阻层作为蚀刻屏蔽，来对金属导线图案下方的介电层进行一等向性蚀刻及一非等向性蚀刻，以于金属内联机间形成复数个空气间隔，进而达到减少金属内联机的时间延迟的功效。在每一金属导线的正下方皆有一层间介电层(interlayer dielectric)使金属内联机获得足够的支撑。本发明方法所形成的空气间隔可以随着每一层金属导线图案的定义同时制作，或在完成数层金属导线图案之后以各层的金属导线图案为蚀刻屏蔽进行一次的蚀刻，以在集成电路中形成大量的空气间隔，而又同时能够使各层金属导线图案底下皆可获得介电层足够的支撑。

Claims (13)

1.一种具有空气间隔的集成电路的制作方法，该制作方法包含有：
提供一基底，其上具有一底层；
于该底层上形成一第一层金属导线图案；
于该第一层金属导线图案以及该底层上形成一介电层；
于该介电层上形成一第二层金属导线图案；
利用该第二层金属导线图案以及该第二层金属导线图案作为一蚀刻屏蔽，非等向性蚀刻该介电层，以形成多个凹槽，同时使剩余的该介电层构成该第二层金属导线图案的支撑结构；
利用等向性蚀刻该第二层金属导线图案的支撑结构，以形成一底切轮廓，扩大该凹槽的面积；以及
进行一化学气相沉积制程，以于该凹槽表面以及该第二层金属导线图案上沉积一盖层，以封盖该凹槽，形成多个空气间隔。
2.根据权利要求1所述的制作方法，其中该基底为一硅基底。
3.根据权利要求1所述的制作方法，其中该第一层金属导线图案是镶嵌于该底层上。
4.根据权利要求1所述的制作方法，其中该第二层金属导线图案是镶嵌于该介电层上。
5.根据权利要求1所述的制作方法，其中该第一层金属导线图案以及该第二层金属导线图案是皆由铜所构成。
6.根据权利要求1所述的制作方法，其中该第一层金属导线图案以及该第二层金属导线图案是皆包含有铝金属。
7.根据权利要求1所述的制作方法，其中该第二层金属导线图案包含有一虚设图案，使缩小该第二金属导线图案的金属导线间孔隙。
8.一种具有空气间隔的集成电路的制作方法，包含有：
提供一基底，其上具有一底层；
于该底层上形成一介电层；
于该介电层上形成一金属导线图案；利用该金属导线图案作为一蚀刻屏蔽，蚀刻该介电层至一预定深度，以于该介电层中形成多个凹槽，同时使剩余的该介电层构成该金属导线图案的支撑结构；以及
利用等向性蚀刻该剩余的该介电层构成该金属导线图案的支撑结构，以形成一底切轮廓，扩大该凹槽的面积。
9.根据权利要求8所述的制作方法，其中该金属导线图案于该介电层上构成多个导线间空隙，且该多个凹槽是形成于该多个导线间空隙内的该介电层中。
10.根据权利要求8所述的制作方法，其中蚀刻该介电层的方法是利用一非等向性蚀刻技术。
11.根据权利要求8所述的制作方法，其中该金属导线图案是镶嵌于该介电层上。
12.根据权利要求8所述的制作方法，其中该制作方法于形成该底切轮廓蚀刻之后，另包含有下列步骤：
进行一化学气相沉积制程，以于该凹槽表面以及该金属导线图案上沉积一盖层，同时封盖该凹槽，形成多个空气间隔。
13.根据权利要求8所述的制作方法，其中该金属导线图案包含有一虚设图案，使缩小该金属导线图案的金属导线间孔隙。
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