CN1950946A - 用于增进信道载子移动性之具有高应力衬料之基于Si－Ge的半导体装置 - Google Patents

用于增进信道载子移动性之具有高应力衬料之基于Si－Ge的半导体装置 Download PDF

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CN1950946A
CN1950946A CNA2005800140631A CN200580014063A CN1950946A CN 1950946 A CN1950946 A CN 1950946A CN A2005800140631 A CNA2005800140631 A CN A2005800140631A CN 200580014063 A CN200580014063 A CN 200580014063A CN 1950946 A CN1950946 A CN 1950946A
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silicon
transistor
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S-P·孙
D·E·布朗
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Abstract

藉由采用应力衬料增加在Si－Ge装置的晶体管信道区内之载子移动性，于实施例中包括在松弛源极/漏极区上运用高压缩或拉伸应力膜，并且在其它实施例中包括于除去硅化物间隔件后，在P－信道或N－信道晶体管的栅极电极(72)与应变硅源极/漏极区(71)之上方，各别地运用高压缩(90)或高拉伸应力膜(120)。

Description

用于增进信道载子移动性之具有高应力衬料之基于Si-Ge 的半导体装置
技术领域
本发明系关于包含晶体管在硅-锗上之微型化半导体装置。本发明特别可用在制造具有增进信道载子移动性的晶体管。
背景技术
坚持不懈的寻求小型化高速半导体装置继续挑战传统半导体材料与制造技术之极限。典型传统半导体装置系在平常的半导体基板之内或上包含复数个主动装置，例如CMOS装置在间隔邻近包含至少一对PMOS与NMOS晶体管。目前技术系利用结晶半导体晶圆做为基板，例如在重度掺杂结晶硅(Si)基板上生成轻度p-掺杂外延(“epi”)层。该重度掺杂基板之低电阻需用以最小化电纳系数来锁定(latch-up)，由于轻度掺杂之epi层允许形成于其内之p型与n型井两者之掺杂分布之独立裁饰作为制造序列之一部分，从而产生最佳化PMOS与NMOS晶体管效能。
藉由利用浅沟隔离区(shallow trench isolation；STI)从较重度掺杂基板至该轻度掺杂epi层内有利地最小化p型掺杂之上扩散(up-diffusion)，将使用很薄之epi层(例如几μm厚)变成可能。此外，藉由避免在各区域性硅氧化法(LOCOS，local oxidation of silicon)隔离结构之边缘形成鸟喙(bird’s beak)，STI容许邻近主动区之较近间隔。STI亦藉由创造较陡之结构而提供较佳之隔离、从主动区至隔离区降低垂直跳升(vertical step)以改善栅极微影之控制、排除以大直径(例如8inch)晶圆可能造成问题之高温场氧化步骤、以及对未来逻辑技术世代是可升级的。
基于”应变硅(strained silicon)”的基板成为吸引人感兴趣之半导体材料系因其中提供电子与电洞流之增速，从而允许以较高速度操作、增进效能特点、以及较低电源消耗之半导体装置制造。一很薄之拉伸应变结晶硅层生成在几微米厚之松弛渐变(relaxed，graded)组成之硅-锗缓冲层上，其硅-锗缓冲层系依序形成在合适之结晶基板上，例如硅晶圆或绝缘层上硅(silicon-on-insulator；SOI)晶圆。典型硅-锗缓冲层含有12至25％之锗。应变硅技术系基于硅原子趋势当硅原子沉积在硅-锗缓冲层上时会与较大之硅与锗原子其内之晶格常数(间距)(相对于纯硅)对齐。在包含更间隔开原子的基板(Si-Ge)上沉积硅原子的结果，硅原子伸展(stretch)”与在下面的硅与锗原子对齐，从而”伸展(stretching)”或拉伸应变该沉积硅层。在该应变硅层内之电子与电洞较具有较小原子间距(即电子与/或电洞流具有较少之电阻)之传统松弛硅层具有较大之移动性。举例来说，在应变硅内之电子流可能较在传统硅内之电子流快至70％。在不需减少晶体管尺寸下，以该应变硅层形成的晶体管与IC装置较以传统硅形成之相等装置的晶体管与IC装置可以显现快至约35％之操作速度。基于应变硅技术之习知作法亦涉及在拉伸应力的硅层上外延生长一松弛硅层，该拉伸应力的硅层随后在松弛硅层内掺杂以形成松弛源极/漏极区。
在传统整体硅(bulk silicon)基板中，电子之移动性快于电洞之移动性。于是，在传统CMOS晶体管中，PMOS晶体管之驱动电流(drive current)低于创造不平衡之NMOS晶体管之驱动电流。因电子移动性之增加较电洞移动性之增加为快，此不平衡系加重于制造在形成在应变晶格半导体基板(例如应变硅于Si-Ge上)内之拉伸应力主动装置区上或其内之CMOS晶体管内。
当进行微型化时，随即需要藉由增进载子移动性来增加晶体管之驱动电流，包括形成在不同类型之应变Si-Ge基板上的晶体管。于是，需要有一种方法，以制造具备晶体管于Si-Ge基板上之半导体装置，该晶体管系以增加信道载子之移动性来增加驱动电流，而且也需要这种半导体装置。
发明内容
本发明之一优点系一种制造包含在Si-Ge基板上具有增进驱动电流的晶体管之半导体装置之方法。
本发明之另一优点系一种包含基于Si-Ge基板上具有增进驱动电流的晶体管之半导体装置。
本发明之额外优点与其它观点与特征将陈述于随后之叙述且对于在所属技术领域具有通常知识者透过随后之检查可将某些部分变得显而易见或可从本发明之实行来得知。本发明之诸项优点特别在附加之申请专利范围中指出而得以了解与取得。
本发明某些部分之先前与其它优点之取得系藉由一种半导体装置，该装置包含：基板，系包含在硅-锗(Si-Ge)层上具有应变晶格的硅层；晶体管，系包含源极/漏极区与基板上方在其间具有栅极介电质层的栅极电极；以及受应力介电质衬料，系在栅极电极的侧表面上方与源极/漏极区之上方。
本发明另一优点系一种半导体装置之制造方法，该方法包含：形成包含在硅-锗(Si-Ge)层上具有应变晶格硅层的基板；形成包含源极/漏极区与基板上方在其间具有栅极介电质层且具有上表面与侧表面的栅极电极的晶体管；以及形成在栅极电极的侧表面上方与源极/漏极区上方的受应力介电质衬料。
本发明之实施例包含在栅极电极的侧表面上形成例如氧化物衬料与氮化物层之介电质侧壁间隔件；在应变硅层上外延生长松弛硅层；在松弛硅层内形成源极/漏极区；然后在侧壁间隔件上、松弛源极/漏极区上、以及在侧壁间隔件与升起式的源极/漏极区间之部份应变硅层上再沉积受应力介电质衬料。
本发明之实施例亦包括在栅极电极的侧表面上形成介电质侧壁间隔件；在应变硅层内形成源极/漏极区；在栅极电极的上表面形成金属硅化物层与在源极/漏极区上形成金属硅化物层；除去介电质侧壁间隔件以显露邻近栅极电极侧表面的部份应变硅层；然后在金属硅化物层上、在栅极电极的上表面上、在栅极电极的侧表面上、在应变硅层之邻近显露部分上、以及在覆于源极/漏极区上之硅化物层上形成应力介电质衬料。
在本发明包含N信道晶体管之实施例中，受应力介电质衬料显现高拉伸应力。在本发明包含P信道晶体管之实施例中，受应力介电质衬料显现高压缩应力。该受应力介电质衬料可能包含厚度约200埃(Angstrom；)至1000埃的硅氮化物、硅碳化物、或硅氮氧化物层。
本发明之实施例包括制造包含在PMOS晶体管上具有压缩膜与在NMOS晶体管上具有拉伸膜之互补金氧半导体(complementary metal oxide semiconductor；CMOS)的晶体管之半导体装置。根据本发明一观点之流程包括在NMOS与PMOS晶体管两者上方沉积压缩应力氮化物膜，然后在NMOS与PMOS晶体管两者上方沉积例如氧化物或氮氧化物膜之薄缓冲膜。当屏蔽PMOS晶体管时，从NMOS晶体管导入选择的蚀刻以除去氧化物与压缩应力氮化物膜。然后在NMOS与PMOS晶体管两者上方沉积拉伸应力氮化物膜，接着远离PMOS晶体管选择性的蚀刻。最后的CMOS装置包含具有拉伸应力膜在其上之NMOS晶体管与具有压缩应力膜在其上之PMOS晶体管。
本发明之额外优点与观点从陈述于后之叙述对于在所属技术领域具有通常知识者将变得非常显而易见，其中本发明显示与描述之实施例经由图解最佳模式简化本发明之实行。如后所述，本发明适用于其它及不同之实施例且在不同明显之观点下容易地在不悖离本发明之精神下进行各种修饰与变更。因此，图标与叙述仅例示性说明本发明之原理及其功效，而非用于限制本发明。
附图说明
图1及图2系根据本发明实施例中方法之连续阶段示意图；
图3至图6系根据本发明另一实施例中方法之连续阶段示意图；以及
图7至图14系根据本发明另一实施例中方法之连续阶段示意图。
在图1及图2中相似之特征或组件以相似的参考字符来表示；在图3至图6中相似之特征或组件以相似的参考字符来表示；在图7至图14中相似之特征或组件以相似的参考字符来表示。
主要组件符号说明
10  硅-锗层                    11  硅层
12  栅极电极                   13  栅极介电质层
14  氧化物衬料                 15  氮化物层
16  松弛硅层(松弛源极/漏极区)
20  金属硅化物层                      20a 属硅化物层
21  受应力介电质衬料                  22  钨栓
23  阻障金属                          24  层间介电质
25  钨栓                              26  金属线
27  接触孔洞                          30  硅-锗层
31  硅层                              32  栅极电极
33  栅极介电质层                      34  衬料
35  硅氮化物隔件                      40  镍硅化物
41  镍硅化物                          50  受高应力介电
质层
70  硅-锗层                           71  硅层
72  栅极电极                          73  栅极介电质层
74  衬料                              75  侧壁间隔件
76  金属硅化物层                      77  金属硅化物层
90  受应力介电质衬料
100 氧化物或氮氧化物衬料              110 屏蔽
120 受应力介电质衬料
130 氧化物或氮氧化物衬料              131 屏蔽
具体实施方式
建造在Si-Ge基板上的晶体管较建造在基体硅基板上的晶体管涉及不同的考量。因为硅基板的大厚度，沉积其上之应力膜倾向于影响该具有藉由该膜显现其相反应力的基板。举例来说，若在基体硅基板上沉积拉伸应力膜，则压缩应力传至基板以及信道区。然而根据本发明之典型实施例中，Su-Ge基板系以具有厚度约200埃至300埃之应变硅层形成。松弛源极/漏极区可能以约至400埃之厚度形成于其上。因此典型应变硅层与源极/漏极区之厚度加起来未超过800埃。结果该应变硅层甚至连同松弛硅层系相对透明于藉由沉积其中之膜显现应力之类型。于是，在应变硅层上沉积之拉伸应力层或在应变硅层上形成的松弛硅层亦将拉伸应力传至形成其中之信道区；以及在该一薄硅层或诸层上沉积压缩应力层将压缩应力传至形成其中之信道区；然而，在基体基板将发生相反之情形。
本发明提出与解决藉由明显增进信道载子移动性以有效的成本和高效率的方式增加基于应变硅基板的晶体管之驱动电流之问题。本发明系来自此基于应变硅基板的晶体管之信道载子移动性可藉由运用应力至此来增加之认知。在形成P-信道晶体管中，藉由运用受应力介电质层对增加电洞移动性显现高压缩应力来增进信道载子移动性。在N-信道晶体管中，藉由运用受应力介电质层对增加电子移动性显现高拉伸应力来明显增加信道载子移动性。受应力介电质层可能运用至其中有形成在应变硅层内部之源极/漏极区的晶体管以及运用至形成在应变硅层上具有松弛源极/漏极区的晶体管。受应力介电质层可能包含硅碳化物、硅氮化物或硅氮氧化物，且可能借助离子加强化学蒸气沉积(plasma enhanced chemical vapor deposition；PECVD)以约200埃至1000埃之厚度沉积。传统PECVD条件可能采用于高压缩或高拉伸介电质层之沉积。在沉积显现高压缩受应力之受应力介电质层中，高频功率与低频功率两者均被运用。当沉积显现高拉伸应力之受应力介电质层，低频功率明显被降低。在沉积显现高拉伸应力之受应力介电质层中，运用拉伸受应力至其下之应变或松弛硅层。在运用显现高压缩应力之层中，运用压缩应力至其下之应变或松弛硅层。
举例来说，显现高压缩应力(例如大于1Gpa)之应力共形(conformal)硅氮化物层可能沉积在：硅烷(SiH4)，流量在200至500sccm；氮(N2)，流量在2000至10000sccm；氨(NH3)，流量在2500至5000sccm；SiH4/NH3比例在0.2至0.04，温度在350℃至550℃；压力在1至6Torr；高频功率在70至300watts；低频功率在20至60watts以及电极(淋气头(shower head))距离在400至600mils。硅氮化物层显现高拉伸应力(例如大于1Gpa)可能沉积在：SiH4，流量在50至500sccm；NH3，流量在1500至5000sccm；N2，流量在4000至30000sccm；SiH4/NH3比例在0.2至0.04，温度在350℃至550℃；压力在2至10Torr；高频功率在40至300watts；低频功率在0至10watts。
在本发明其它实施例中，藉由化学蒸气沉积法沉积介电质层以及接以紫外或电子束辐射施于该沉积介电质层以增加其拉伸应力可能形成显现高拉伸应力之介电质层。
根据本发明之实施例在相对低温下运用应力层。于是在不超过镍硅化物层之热稳定度限制下，本发明使在晶体管内之拉伸或压缩应力层之沉积能具有形成在源极/漏极区与栅极电极上之镍硅化物层。本发明亦适用于具有其它金属硅化物(例如钴硅化物)的晶体管。在钴硅化中，在沉积钴层与实现硅化之前先沉积分开的硅层。
图1至图6系本发明一实施例之示意图。请参照图1，应变硅层11系形成在Si-Ge层10上。需了解在传统实行中，硅层11可能在源极/漏极区内完全地应变或局部地应变，而本实施例包含两种类型之应变硅层。栅极电极12在应变硅层11上方形成且两者间有栅极介电质层13。然后形成包含L型氧化物衬料14(例如硅氧化物)以及氮化物层15(例如硅氮化物)于其上之侧壁间隔件。然后在应变硅层11与源极/漏极区上外延生长松弛硅层16，当掺杂延伸源极/漏极区至应变硅层11内。金属硅化物层20，20A(例如镍硅化物)各别地形成在栅极电极12之上表面上以及在松弛源极/漏极区16上。然后在侧壁间隔件上、硅化物20，20A上、以及在硅层11上的氧化物衬料14与松弛源极/漏极区16间形成受应力介电质衬料21。在本发明实施例中该硅层局部应变于源极/漏极区，该应力介电质层21将应变传至栅极电极下方与间隔件下方的硅层11，因此有利地增加信道载子移动性。在实施例中整个硅层11应变，受应力介电质层在栅极电极与间隔件下方之信道区内更增加应变，因此更增加信道载子移动性。受应力介电质层21可以是例如藉由PECVD沉积显现高压缩或拉伸应力的硅氮化物。图2图标之额外特征包括将钨栓22与阻障金属(barrier metal)23(例如钛氮化物)填入层间介电质24内之开口，以及将钨栓25与阻障金属线26(例如钛氮化物)填入层间介电质24内之接触孔洞27。藉由受高应力介电质层21运用之应力增进了信道载子移动性，因此增加晶体管之驱动电流。
图3至图6系本发明另一实施例之示意图。请参照图3，应变硅层31系在Si-Ge层30上方形成。如之前实施例中所讨论，硅层31可能在源极/漏极区下方全面地应变或局部地应变。栅极电极32在应变硅层31上方形成且两者间有栅极介电质层33。在栅极电极32之侧表面上与应变硅层31之部分上表面上形成包含如厚度约60埃至600埃氧化物衬料34之侧壁间隔件。较佳该衬料34可能藉由ALD沉积以及可能包含硅氮化物。硅氧化物衬料藉由在侧表面上硅化有利地预防栅极电极的消耗，以及在硅氮化物侧壁间隔件上有利地预防随后形成之镍硅化物薄层接触到栅极电极上表面上之镍硅化物接触层与/或接触到应变硅层31上表面上之镍硅化物接触层，因此有效预防镍硅化物沿着硅氮化物侧壁间隔件桥接。
藉由采用随后蚀刻之PECVD在硅氧化物衬料34上形成硅氮化物间隔件35。如图4所示，再藉由在栅极电极32上表面上形成镍硅化物层40以及在应变硅层31或应变部分硅层31内形成之源极/漏极区上形成镍硅化物层41接着实现了硅化。
如图5所示，接着除去衬料与侧壁间隔件显露出在硅化物层41与栅极电极32侧表面间之应变硅层31之部分上表面，其上具有当作缓冲层之薄(约小于50埃)氧化物层。如图6所示，藉由PECVD再沉积受高应力介电质层50(例如显现高压缩应力的硅氮化物层)。该受高应力介电质层50作为增加信道电洞移动性，因此增加了驱动电流。
图7至图14系本发明另一实施例之示意图。请参照图7，系包含NMOS晶体管部分在左方以及PMOS晶体管部分在右方之CMOS装置之示意图，其相似之特征以相似的参考字符来表示。在Si-Ge层70上方形成应变硅层71。如之前所讨论实施例中，硅层71可能在源极/漏极区内全面地应变或局部地应变。栅极电极72在应变硅层71上方形成且两者间有栅极介电质层73。在栅极电极72之侧表面上与应变硅层71之部分上表面上形成包含如厚度约60埃至600埃氧化物衬料74之侧壁间隔件。硅氧化物衬料74可以用如图3中硅氧化物衬料34相同之方式来形成。藉由采用随后蚀刻之PECVD在硅氧化物衬料74上形成硅氮化物间隔件75。再藉由在栅极电极72上表面上形成镍硅化物层76以及在应变硅层71上形成之源极/漏极区上形成镍硅化物层77接着实现了硅化。
如图8所示，从各晶体管除去衬料74与侧壁间隔件75显露出在硅化物层77与栅极电极72侧表面间之应变硅层71之部分上表面。如图9所示，然后在NMOS与PMOS晶体管两者上方沉积具有大于1.5GPa压缩应力之高压缩应力硅氮化物膜90。高压缩应力硅氮化物膜90之沉积可能实现在：温度约400℃至480℃；硅烷(SiH4)，流量在200至300sccm；氨(NH3)，流量在3000至4000sccm；氮(N2)，流量在3500至4500sccm；压力在2至6Torr；淋气头(shower head)间距在400至600mils；高频RF功率在60至100watts；低频RF功率在40至90watts；后接NH3/N2离子处理与NH3，流量在500至1500sccm；以及与N2，流量在2000至4000sccm；高频RF功率在100至600watts；以及低频RF功率在20至60watts以约20至60秒。多层沉积与离子处理更增加了压缩应力。如图10所示，接着藉由传统CVD处理来沉积薄氧化物或氮氧化物膜100。典型薄氧化物或氮氧化物膜100之沉积厚度约为30至60埃。
如图11所示，接着在PMOS晶体管上方运用如光阻剂或硬屏蔽之屏蔽110，而从NMOS晶体管除去氧化物或氮氧化物膜100与高压缩应力硅氮化物膜90。
请参照图12，从PMOS晶体管除去屏蔽110，接着在PMOS与NMOS晶体管两者上方沉积具有大于1.5GPa拉伸应力之高拉伸应力硅氮化物膜120。高压缩应力硅氮化物膜120之沉积可能实现在：温度约400℃至480℃；硅烷(SiH4)，流量在40至80sccm；氨(NH3)，流量在1500至2500sccm；氮(N2)，流量在20000至40000sccm；基板与淋气头间之距离在400至600mils；压力在2至8Torr；高频功率在40至80watts；以及低频功率约至10watts。接着藉由传统CVD处理来沉积厚度约为30至60埃之薄氧化物或氮氧化物膜130。
请参照图13，接着在NMOS晶体管上方运用如光阻剂或硬屏蔽之屏蔽131，而从PMOS晶体管选择地除去氧化物或氮氧化物膜130与高拉伸应力硅氮化物膜120而停在氧化物或氮氧化物膜100上。如图14所示，接着除去屏蔽131而得到结果包含在NMOS晶体管上方的氧化物或氮氧化物膜130与高拉伸应力硅氮化物膜120以及在PMOS晶体管上方的氧化物或氮氧化物膜100与高压缩应力硅氮化物膜90之结构。此结果的CMOS装置包含具有增加载子移动性以及因此而增加驱动电流之PMOS与NMOS晶体管。
本发明提供使基于应变晶格技术之高品质、高操作速度之微型半导体装置能具有最大化晶体管驱动电流之方法学。此发明方法学可以利用传统处理技术与设备并满足自动制造技术之产量需求来实行，且完全兼容于传统高密度积体半导体装置之制造流程。
本发明在制造不同类型之半导体装置拥有极佳之产业利用性，尤其是在制造具有高操作速度之微型半导体装置。
为了提供本发明之较佳了解，在之前的叙述中描述了许多特定细节(例如特定材料、结构、反应物、处理等)。然而不需凭借之前描述的特定细节亦可以实行本发明。为了不模糊本发明之精神，在其它例子中并未在细节中描述已知之处理材料与技术。
本发明说明仅显示与描述本发明之较佳实施例与少数用途广泛之范例。本发明亦可藉由其它不同的组合与环境加以施行或应用，本说明书中的各项细节亦可基于不同观点与应用，在不悖离本发明之精神下进行各种修饰与变更。

Claims (10)

1.一种半导体装置，包含：
基板，包含在硅-锗层(70)上具有应变晶格的硅层(70)；
晶体管，包含源极/漏极区以及在基板上方且两者之间有栅极介电质层(73)的栅极电极；以及
受应力介电质衬料(90，120)，位于栅极电极的侧表面上方以及源极/漏极区上方。
2.如权利要求1所述的半导体装置，其中，该源极/漏极区是形成在生长于应变硅层上的松弛硅层内，且受应力介电质衬料显现高压缩(90)或拉伸(120)应力。
3.如权利要求2所述的半导体装置，进一步包含：
介电质侧壁间隔件，位于栅极电极的侧表面上；
金属硅化物层，位于栅极电极的上表面上，其中，该应力介电质衬料位于侧壁间隔件上；
侧壁间隔件，包含在栅极电极的侧表面上和在应变硅层上表面部分上的氧化物衬料，以及氧化物衬料上的氮化物层；以及
受应力介电质衬料，位于氮化物层上以及氧化物衬料的底部与松弛硅层之间。
4.如权利要求3所述的半导体装置，其中，该晶体管为P-信道晶体管，且受应力介电质衬料(90)显现高压缩应力。
5.如权利要求3所述的半导体装置，其中，该晶体管为N-信道晶体管，且受应力介电质衬料(120)显现高拉伸应力。
6.一种半导体装置的制造方法，包含：
形成包含有在硅-锗层(70)上具有应变晶格硅层(71)的基板；
形成包含有源极/漏极区以及在其间具有栅极介电质层、且位于基板上方具有上表面与侧表面的栅极电极的晶体管；以及
形成在栅极电极的侧表面上方以及源极/漏极区上方的受应力介电质衬料(90，120)，其中，应变硅层(71)在源极/漏极区内完全地应变或局部地应变。
7.如权利要求6所述的方法，包含：
形成侧壁间隔件于栅极电极的侧表面上；
在应变硅层上外延生长松弛硅层；
形成源极/漏极区于松弛硅层内；以及
沉积受应力介电质衬料于侧壁间隔件上、松弛源极/漏极区上以及侧壁间隔件与松弛源极/漏极区之间的部分应变硅层上，其中，该受应力介电质衬料包含厚度约200至1000埃的硅氮化物、硅碳化物或硅氮氧化物层。
8.如权利要求7所述的方法，包含：
形成源极/漏极区于应变硅层(71)内；
形成第一金属硅化物层于栅极电极(76)的上表面上以及形成第二金属硅化物层于源极/漏极区(71)上；
除去介电质侧壁间隔件，以显现邻近栅极电极侧表面的部分应变硅层；以及
形成受应力介电质衬料(90，120)于第一金属硅化物层(76)上、栅极电极(72)的侧表面上以及应变硅层(71)的邻近显露部分。
9.如权利要求8所述的方法，其中，该晶体管是：
P-信道晶体管，该方法包含借助离子加强化学蒸气沉积法沉积介电质层以形成受应力介电质层(90)，因此显现高压缩应力；或
N-信道晶体管，该方法包含借助离子加强化学蒸气沉积法沉积介电质层以形成受应力介电质衬料层(120)，因此显现高拉伸应力。
10.一种半导体装置的制造方法，包含：
形成包含有在硅-锗层(70)上具有应变晶格的硅层(71)的基板；
形成包含有NMOS晶体管和PMOS晶体管的CMOS晶体管，各晶体管包含源极/漏极区以及在其间具有栅极介电质层(73)、且位于基板上方具有上表面与侧表面的栅极电极(72)；
形成侧壁间隔件于各栅极电极的侧表面上；
形成金属硅化物层(76，77)于各栅极电极(72)的上表面上以及各晶体管源极/漏极区的表面上；
从各栅极电极(72)的侧表面除去侧壁间隔件；
沉积显现有高压缩应力的硅氮化物层(90)于NMOS与PMOS晶体管上方；
在显现有高压缩应力的硅氮化物层(90)上沉积氧化物或氮氧化物衬料(100)；
从NMOS晶体管选择地除去氧化物或氮氧化物衬料(100)和显现高压缩应力的硅氮化物层(90)；
沉积显现高拉伸应力的硅氮化物层(120)于NMOS晶体管上；以及于PMOS晶体管上；以及
在NMOS晶体管与PMOS晶体管上，在显现有高拉伸应力的硅氮化物层上沉积氧化物或氮氧化物衬料(130)；以及
从PMOS晶体管选择地除去氧化物或氮氧化物衬料和显现高拉伸应力的硅氮化物层。
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