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Publication numberCN1905072 A
Publication typeApplication
Application numberCN 200610110018
Publication date31 Jan 2007
Filing date28 Jul 2006
Priority date29 Jul 2005
Also published asCN1905072B, DE602006011684D1, EP1750279A2, EP1750279A3, EP1750279B1, EP2043104A1, EP2043104B1, US7366033, US7773422, US8085607, US20070025161, US20080165580, US20100271873
Publication number200610110018.2, CN 1905072 A, CN 1905072A, CN 200610110018, CN-A-1905072, CN1905072 A, CN1905072A, CN200610110018, CN200610110018.2
Inventors朴起台, 崔正达, 曹成奎
Applicant三星电子株式会社
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
3-level non-volatile semiconductor memory device and method of driving the same
CN 1905072 A
Abstract  translated from Chinese
一种用于非易失半导体存储器设备的页缓冲器,包含:开关,被配置来将耦合于第一存储器单元的第一比特线耦合到耦合于第二存储器单元的第二比特线;第一锁存块,耦合于第一比特线,并且被配置来将第一锁存数据传送给第一存储器单元;以及第二锁存块,耦合于第二比特线及第一锁存块,并且被配置来将第二锁存数据传送给第二存储器单元。 A non-volatile semiconductor memory device of the page buffer, comprising: a switch configured to be coupled to the first bit line of the first memory cell coupled to a second bit line coupled to the second memory cell; first latch block, coupled to the first bit line, and configured to latch the first data transfer to the first memory unit; and a second latch block coupled to the second bit line and the first latch block, and is configuration to the second latch data to the second memory cell.
Claims(30)  translated from Chinese
1.一种用于非易失半导体存储器设备的页缓冲器,包含:开关,被配置来将耦合于第一存储器单元的第一比特线耦合到耦合于第二存储器单元的第二比特线;第一锁存块,耦合于第一比特线,并且被配置来将第一锁存数据传送给第一存储器单元;以及第二锁存块,耦合于第二比特线及第一锁存块,并且被配置来将第二锁存数据传送给第二存储器单元。 1. A method for the nonvolatile semiconductor memory device page buffer, comprising: a switch configured to be coupled to the first memory cell is coupled to a first bit line coupled to the second memory cells of the second bit line; a first latch block coupled to the first bit line, and configured to transfer a first latch data to the first memory cell; and a second latch block coupled to the second bit line and the first latch block, and configured to transmit the second latch data to the second memory unit.
2.如权利要求1所述的页缓冲器,其中第一锁存块还包含:第一锁存单元,被配置来存储第一锁存数据;翻转触发单元,被配置来将第一锁存数据设置为第一逻辑状态;以及第一触发单元,被配置来将第一锁存数据设置为第二逻辑状态。 2. The page buffer according to claim 1, wherein the first latch block further comprises: a first latch unit configured to store the first latch data; flip trigger unit configured to latch the first data is set to a first logic state; and a first trigger unit configured to set the first latch data to a second logic state.
3.如权利要求2所述的页缓冲器,其中第一触发单元包含:传送触发单元,被配置来响应于第二锁存数据,将第一锁存数据设置为第二逻辑状态;以及触发电路,被配置来响应于第一存储器单元与第二存储器单元中一个的门限电压,将第一锁存数据设置为第二逻辑状态。 3. The page buffer of claim 2, wherein the first trigger unit comprises: a trigger transmitting unit configured to latch data in response to the second, the first latch data is set to a second logic state; and a trigger circuit configured to respond to the first memory cell and a second memory cell in the threshold voltage, the first latch data is set to a second logic state.
4.如权利要求2所述的页缓冲器,其中翻转触发单元还被配置来响应于第二锁存数据、以及第一存储器单元与第二存储器单元中一个的门限电压,将第一锁存数据设置为第一逻辑状态。 The page buffer of claim 2, wherein the triggering unit is further configured to flip in response to the second latch data, and a first memory unit and the second memory cell threshold voltage of one of the first latch data is set to a first logic state.
5.如权利要求1所述的页缓冲器,其中第二锁存块还包含:第二锁存单元,被配置来存储第二锁存数据;以及第二触发单元,被配置来响应于第一存储器单元与第二存储器单元中一个的门限电压,将第二锁存数据设置为第二逻辑状态。 5. The page buffer according to claim 1, wherein the second latch block further comprises: a second latch unit configured to store the second latch data; and a second trigger unit configured to respond to the first a memory cell and a second memory cell threshold voltage in the second latch data is set to a second logic state.
6.如权利要求1所述的页缓冲器,其中第一锁存块还被配置来输出在第一存储器单元与第二存储器单元中存储的至少三个数据比特中的一个。 Page buffer as claimed in one of the preceding claims, wherein the first latch block is further configured to output the at least three data bits stored in the first memory unit and the second memory unit a.
7.如权利要求1所述的页缓冲器,其中:第一锁存块还被配置来改变第一存储器单元的门限电压;以及第二锁存块还被配置来改变第二存储器单元的门限电压。 7. The page buffer according to claim 1, wherein: the first latch block is further configured to change the threshold voltage of the first memory cell; and a second latch block is further configured to change the second memory cell threshold Voltage.
8.如权利要求1所述的页缓冲器,其中第一存储器单元与第二存储器单元为NAND存储器单元。 8. The page buffer according to claim 1, wherein the first memory unit and the second memory cell for NAND memory cell.
9.如权利要求1所述的页缓冲器,其中第一存储器单元与第二存储器单元为NOR存储器单元。 9. A page buffer as claimed in claim 1, wherein the first memory unit and the second memory unit for NOR memory cells.
10.一种对非易失半导体存储器设备编程的方法,包含:响应于第一数据比特,对第一存储器单元门限电压编程;响应于第二数据比特以及第一存储器单元门限电压,对第一存储器单元门限电压以及第二存储器单元门限电压中的一个编程;以及响应于第三数据比特以及第二存储器单元门限电压,对第一存储器单元门限电压以及第二存储器单元门限电压中的一个编程。 10. A method for programming a non-volatile semiconductor memory device, comprising: in response to the first data bit of the first memory cell threshold voltage programming; in response to the second data bit and the first memory cell threshold voltage, the first memory cell threshold voltage and a second memory cell threshold voltage in a program; and in response to the third data bit and the second memory cell threshold voltage, the first memory cell threshold voltage and a second memory cell threshold voltage of a programmed.
11.如权利要求10所述的方法,所述响应于第三数据比特以及第二存储器单元门限电压、对第一存储器单元门限电压以及第二存储器单元门限电压中的一个编程还包含:响应于第一存储器单元门限电压,对第一存储器单元门限电压以及第二存储器单元门限电压中的一个编程。 11. A method as claimed in claim 10, wherein the response to the third data bit and the second memory cell threshold voltage, to the first memory cell threshold voltage and a second memory cell threshold voltages in a programming further comprising: in response to first memory cell threshold voltage, the first memory cell threshold voltage and a second memory cell threshold voltage of a programmed.
12.如权利要求10所述的方法,还包含:验证所述响应于第一数据比特、对第一存储器单元门限电压的编程;重复所述响应于第一数据比特、对第一存储器单元门限电压的编程,直至编程被验证;验证所述响应于第二数据比特以及第一存储器单元门限电压、对第一存储器单元门限电压以及第二存储器单元门限电压中的一个的编程;重复所述响应于第二数据比特以及第一存储器单元门限电压、对第一存储器单元门限电压以及第二存储器单元门限电压中的一个的编程,直至编程被验证;验证所述响应于第三数据比特以及第二存储器单元门限电压,对第一存储器单元门限电压以及第二存储器单元门限电压中的一个的编程;以及重复所述响应于第三数据比特以及第二存储器单元门限电压,对第一存储器单元门限电压以及第二存储器单元门限电压中的一个的编程,直至编程被验证。 12. The method of claim 10, further comprising: verifying that the response to the first data bit of the first memory cell threshold voltage programming; repeating the response to the first data bit of the first memory cell threshold voltage programming until programming is verified; verifying the response to the second data bit and the first memory cell threshold voltage, the programming of the first memory cell threshold voltage and a second memory cell threshold voltage of one of; repeating said response to the second data bit and the first memory cell threshold voltage, the first memory cell threshold voltage and a second memory cell threshold voltage in a programming until programming is verified; verifying the response to the third data bit and a second memory cell threshold voltage, the first memory cell threshold voltage and a second memory cell threshold voltage in the programmed one; and repeating the response to the third data bit and the second memory cell threshold voltage, to the first memory cell threshold voltage and a second memory cell threshold voltage of a programming until programming is being verified.
13.如权利要求10所述的编程方法,其中:所述响应于第一数据比特、对第一存储器单元门限电压编程还包含:响应于第一数据比特,增加第一存储器单元的门限;所述响应于第二数据比特以及第一存储器单元门限电压、对第一存储器单元门限电压以及第二存储器单元门限电压中的一个编程还包含:响应于第二数据比特以及第一存储器单元门限电压,增加第一存储器单元门限电压以及第二存储器单元门限电压中的一个;以及所述响应于第三数据比特以及第二存储器单元门限电压、对第一存储器单元门限电压以及第二存储器单元门限电压中的一个编程还包含:响应于第三数据比特以及第二存储器单元门限电压,增加第一存储器单元门限电压以及第二存储器单元门限电压中的一个门限电压。 13. The programming method according to claim 10, wherein: said response to the first data bit of the first memory cell threshold voltage program further comprising: in response to the first data bit, the increase threshold of the first memory cell; the said response to the second data bit and the first memory cell threshold voltage, the first memory cell threshold voltage and a second memory cell threshold voltage in a programmed further comprising: in response to the second data bit and the first memory cell threshold voltage, increase the first memory cell threshold voltage and a second memory cell threshold voltage in a; and the response to the third data bit and the second memory cell threshold voltage, the first memory cell threshold voltage and a second memory cell threshold voltage A program further comprising: in response to the third data bit and the second memory cell threshold voltage, increase the first memory cell threshold voltage and a second memory cell threshold voltage in a threshold voltage.
14.如权利要求10所述的方法,所述对第一存储器单元门限电压编程还包含:响应于第一数据比特,将第一存储器单元门限电压编程至基本在至少三个门限电压组中的第二个门限电压组内。 14. The method of claim 10, wherein the first memory cell threshold voltage program further comprising: in response to a first data bit, the first memory cell threshold voltage programmed to the base of at least three threshold voltage groups The second threshold voltage in the group.
15.如权利要求10所述的方法,所述响应于第二数据比特以及第一存储器单元门限电压、对第一存储器单元门限电压以及第二存储器单元门限电压中的一个编程还包含:如果第一存储器单元门限电压在至少三个门限电压组中的第一个门限电压组内,则响应于第二数据比特,将第二存储器单元的门限编程至基本在第三个门限电压组内;以及如果第一存储器单元门限电压在第二个门限电压组内,则响应于第二数据比特,将第一存储器单元的门限编程至基本在第三个门限电压组内。 15. A method as claimed in claim 10, wherein the response to the second data bit and the first memory cell threshold voltage, to the first memory cell threshold voltage and a second memory cell threshold voltages in a programming further comprises: if the first a memory cell threshold voltage of at least three threshold voltage groups within the first threshold voltage group in response to the second data bit, the gate of the second memory cell programmed to limit substantially within the third threshold voltage group; and If the first memory cell threshold voltage is within the second threshold voltage group in response to the second data bit, the gate of the first memory cell programmed to limit substantially within the third threshold voltage group.
16.如权利要求10所述的方法,所述响应于第三数据比特以及第二存储器单元门限电压、对第一存储器单元门限电压以及第二存储器单元门限电压中的一个编程还包含:如果第二存储器单元门限电压在至少三个门限电压组中的第一个门限电压组内,则响应于第三数据比特,将第二存储器单元门限电压编程至基本在第二个门限电压组内;否则,响应于第三数据比特,将第一存储器单元门限电压编程至基本在第二个门限电压组内。 16. A method as claimed in claim 10, wherein the response to the third data bit and the second memory cell threshold voltage, to the first memory cell threshold voltage and a second memory cell threshold voltages in a programming further comprises: if the first second memory cell threshold voltage of at least three threshold voltage groups within the first threshold voltage group in response to the third data bit, the second memory cell threshold voltage is programmed to substantially within a second threshold voltage group; otherwise, , in response to the third data bit, the first memory cell threshold voltage programmed to the base in a second threshold voltage within a group.
17.一种读取非易失半导体存储器的方法,包含:利用第一参考电压,读出第一存储器单元门限电压;利用第二参考电压,读出第二存储器单元门限电压;以及响应于读出第一存储器单元门限电压与第二存储器单元门限电压,生成数据比特。 17. A method for reading the nonvolatile semiconductor memory, comprising: using a first reference voltage, reads out the first memory cell threshold voltage; using a second reference voltage, the memory cell is read out of the second threshold voltage; and in response to the read a first memory cell threshold voltage and the second memory cell threshold voltage, to generate data bits.
18.如权利要求17所述的方法,所述第一参考电压不同于所述第二参考电压。 18. The method of claim 17, said first reference voltage different from said second reference voltage.
19.如权利要求17所述的方法,还包含:将第一锁存数据与第二锁存数据设置为第一状态;响应于读出第一存储器单元门限电压,改变第二锁存数据。 19. The method of claim 17, further comprising: a first data latch and the second latch data is set to a first state; in response to the read out of the first memory cell threshold voltage, changing the second latch data. 响应于第二锁存数据,改变第一锁存数据;响应于读出第二存储器单元门限电压,改变第一锁存数据;以及所述生成数据比特还包括:提供第一锁存数据。 In response to the second latch data, changing the first latch data; in response to the read out of the second memory cell threshold voltage, to change the first latch data; and generating the data bit further comprising: providing a first latch data.
20.如权利要求17所述的方法,其中所述读出第二存储器单元门限电压还包括:利用第二参考电压,读出第二存储器单元门限电压,该第二参考电压基本等于第一参考电压。 20. The method of claim 17, wherein said memory cell is read out of the second threshold voltage further comprising: a second reference voltage, the memory cell is read out of the second threshold voltage, the second reference voltage is substantially equal to the first reference Voltage.
21.如权利要求17所述的方法,还包含:将第一锁存数据与第二锁存数据设置为第一状态;响应于读出第二存储器单元门限电压,改变第二锁存数据;响应于读出第一存储器单元门限电压,改变第二锁存数据;响应于第二锁存数据,改变第一锁存数据;以及所述生成数据比特还包括:提供第一锁存数据。 21. The method of claim 17, further comprising: a first data latch and the second latch data is set to a first state; in response to the read out of the second memory cell threshold voltage, changing the second latch data; in response to the read out of the first memory cell threshold voltage, changing the second latch data; in response to the second latch data, changing the first latch data; and generating the data bit further comprising: providing a first latch data.
22.如权利要求17所述的方法,还包括:利用第三参考电压,读出第二存储器单元门限电压。 22. The method of claim 17, further comprising: a third reference voltage, the memory cell is read out of the second threshold voltage.
23.如权利要求22所述的方法,其中:第一参考电压与第二参考电压基本相等;以及第三参考电压不同于第一参考电压与第二参考电压。 And a third reference voltage different from the first reference voltage and the second reference voltage; a first reference voltage and the second reference voltage is substantially equal to: 23. The method of claim 22, wherein.
24.如权利要求22所述的方法,还包含:将第一锁存数据与第二锁存数据设置为第一状态;响应于利用第一参考电压、读出第二存储器单元门限电压,改变第二锁存数据;响应于第二锁存数据,改变第一锁存数据;响应于利用第二参考电压、读出第二存储单元门限电压,改变第一锁存数据;响应于第二锁存数据、以及读出第一存储单元门限电压,改变第一锁存数据;以及所述生成数据比特还包括:提供第一锁存数据。 24. The method of claim 22, further comprising: a first data latch and the second latch data is set to a first state; in response to the use of a first reference voltage, the memory cell is read out of the second threshold voltage, change the second latch data; in response to the second latch data, changing the first latch data; in response to the use of the second reference voltage, the memory cell is read out of the second threshold voltage, to change the first latch data; in response to a second lock stored data, and reading out the first memory cell threshold voltage, to change the first latch data; and generating the data bit further comprising: providing a first latch data.
25.一种非易失半导体存储器设备,包含:第一存储器单元串与第二存储器单元串,所述第一存储器单元串与第二存储器单元串每个都包含至少一个两级存储器单元与至少一个三级存储器单元,第一存储器单元串的每个三级存储器单元与第二存储器单元串的对应的三级存储器单元形成存储器单元对;以及页缓冲器,耦合至第一存储器单元串与第二存储器单元串,并且被配置来将三比特数据映射到第一存储器单元串与第二存储器单元串的存储器单元对的门限电平,以及将一比特数据映射到两级存储器单元的门限电平。 25. A nonvolatile semiconductor memory device, comprising: a first memory cell string and the second string of memory cells, the first memory cell string and the second string of memory cells each comprising at least one memory cell and at least two a three memory cells, the first string of memory cells each memory cell and the three second string of memory cells corresponding to the three memory cells of the memory cell is formed; and a page buffer, coupled to the first memory cell string and the first Second string of memory cells, and configured to map the three-bit data to the first memory cell string and the second string of memory cells of the memory cell of the threshold level, and mapping the one-bit data to the memory cell threshold levels level.
26.如权利要求25所述的非易失半导体存储器设备,其中第一存储器单元串与第二存储器单元串的每个还包含:第一两级存储器单元;多个三级存储器单元;以及第二两级存储器单元;其中,所述第一两级存储器单元、三级存储器单元、以及第二两级存储器单元相互串联耦合,从而第一两级存储器单元与第二两级存储器单元被放置在存储器单元串的相对端。 A plurality of third memory cells;; a first level memory unit and the second: 25 26. A non-volatile semiconductor memory device according to claim, wherein the first memory cell string and the second string of memory cells each further comprises twenty-two memory unit; wherein the first two memory cell, three memory cells, and a second two memory cells coupled in series to each other, so that the first two memory cell and the second memory cells are disposed in two opposite ends of the memory cell strings.
27.如权利要求25所述的非易失半导体存储器设备,其中存储器单元对的存储器单元被耦合到同一字线。 27. The nonvolatile semiconductor memory device according to claim 25, wherein the memory cells of the memory cell is coupled to the same word line.
28.如权利要求25所述的非易失半导体存储器设备,还包含:控制信号生成电路,被配置来控制页缓冲器,从而如果行地址为对应于在多个三级存储器单元中存储的页的三级地址,则执行三级存储器单元操作,而如果行地址为对应于在两级存储器单元中存储的页的两级地址,则执行两级存储器单元操作。 25 28. The nonvolatile semiconductor memory device according to claim, further comprising: control signal generating circuit configured to control the page buffer, so that if the row address is stored in a corresponding plurality of memory cells in the three pages tertiary address, the memory cell operation is performed three, and if the row address is the address corresponding to the levels stored in the page-level memory cell, the memory cell is performed two-stage operation.
29.一种操作非易失半导体存储器设备的方法,包含:接收与命令相关的行地址;确定所述行地址是否对应于在多个三级存储器单元中存储的页;以及如果所述行地址确实对应于这样的页,则在三级存储器单元上执行对应于所述命令的操作。 29. A method of operating a non-volatile semiconductor memory device, comprising: receiving a row address associated with the command; determining whether the row address stored in a corresponding plurality of memory cells in the three pages; and if the row address indeed corresponds to a page, on the third memory unit to perform the operation corresponding to the command.
30.如权利要求29所述的操作非易失半导体存储器设备的方法,还包含:如果所述行地址确实不对应于这样的页,则在与行地址相关的至少一个存储器单元上执行对应于所述命令的操作。 30. The operation method of the nonvolatile semiconductor memory device according to claim 29, further comprising: if the row address does not correspond to such a page, then at least one memory cell with the row address corresponding to the associated execution The command of the operation.
Description  translated from Chinese
三级非易失半导体存储器设备及其驱动方法 Three non-volatile semiconductor memory device and driving method thereof

本申请要求分别于2005年7月29日、2006年1月26日提交的韩国专利申请2005-69270与2006-8358的优先权,其全部内容通过引用融入本文。 This application claims respectively in July 29, 2005, the Korean Patent January 26, 2006 filed with the 2006-8358 2005-69270 priority in its entirety by reference into the article.

技术领域 FIELD

一般地,本发明涉及半导体存储器设备;更具体地,涉及具有三级存储器单元的非易失半导体存储器设备,以及操作该非易失半导体存储器设备的方法。 Generally, the present invention relates to semiconductor memory devices; and more particularly, relates to a nonvolatile semiconductor memory device having three memory cells, and a method of operating the non-volatile semiconductor memory device.

背景技术 BACKGROUND

非易失半导体存储器设备当电源从其断开时保持所存储的数据。 The nonvolatile semiconductor memory device when the power supply to maintain the stored data when disconnected therefrom. 已经知道有适合于非易失半导体存储器设备的各种类型的存储器单元。 There has been known a non-volatile semiconductor memory device suitable for various types of memory cells. 用于非易失半导体存储器设备的一种此类存储器单元为单晶体管型存储器单元。 One such memory cell is non-volatile semiconductor memory device of a single transistor type memory cell.

一般地,晶体管型存储器单元MC,如图1所示,包含半导体基底上的源极S与漏极D,在介电氧化物层DOX与栅极氧化物层GOX之间形成的浮动栅极FG,以及控制栅极CG。 Generally, the transistor type memory cell MC, shown in Figure 1, contains the source S and the drain D of the semiconductor substrate, the floating gate FG between DOX and the dielectric oxide layer formed on the gate oxide layer GOX , and a control gate CG. 浮动栅极FG俘获电子。 Floating gate FG capture electrons. 被俘获的电子设立存储器单元MC的门限电压。 The trapped electrons to establish a memory cell MC of the threshold voltage. 当非易失半导体存储器设备运行于读取操作时,检测存储器单元MC的门限电压,并且在其中存储所检测的数据。 When the nonvolatile semiconductor memory device operating in read operation, the memory cell MC detection threshold voltage, and in which to store the detected data.

一般地,在非易失半导体存储器设备的存储器单元MC中,可以反复运行编程与擦除快做。 Generally, in the memory cell MC nonvolatile semiconductor memory device, you can run the program and erase repeatedly done fast. 单晶体管存储器单元MC的各种功能由各种类型的施加电压确定。 Various functions of single-transistor memory cell MC is determined by the various types of the applied voltage. 当电子移动到浮动栅极FG时,对此类单晶体管存储器单元MC编程。 When electrons move to the floating gate FG, for such one-transistor memory cell MC is programmed. 电子可以通过Fowler-Nordheim隧道(FN)或者电子注入移动到浮动栅极FG。 Electrons can tunnel through the Fowler-Nordheim (FN) or electron injection into the floating gate move FG. 电子注入可以为沟道热电子注入(CHE)或沟道启动次级电子注入(CISEI)。 Electron injection can electron injection (CHE) is a channel or channel hot electron injection start secondary (CISEI). FN广泛用于一次擦除所有数据的闪烁存储器。 FN is widely used to erase all data on the flash memory. 、一般地,晶体管存储器单元MC存储两个值之一。 One, in general, the transistor memory cell MC stores two values. 这两个数据值,如图2所示,由被设置为两个电平之一的门限值存储。 These two data values, as shown in Figure 2, the power is set to one of two threshold levels are stored. 例如,当存储器单元MC的门限电压低于参考电压VM时,数据读取为“1”;而当存储器单元MC的门限电压高于参考电压VM时,数据读取为“0”。 For example, when the memory cell MC is lower than the threshold voltage of the reference voltage VM, the data read is "1"; and when the memory cell MC is higher than the threshold voltage of the reference voltage VM, the data read is "0."

随着半导体存储器设备变得高度集成,人们开发出了四级存储器单元。 As semiconductor memory devices become highly integrated, people developed four memory cells. 四级存储器单元,如图3所示,可以被编程为四个门限电压电平之一。 Four memory cells, as shown in Figure 3, can be electrically programmed to one of four threshold voltage level. 结果,四级存储器单元可以存储四种数据类型之一。 As a result, four memory cells may store one of four data types. 因此,具有四级存储器单元的非易失半导体存储器设备(此后称为“四级非易失半导体存储器设备”)的数据存储容量是具有两级存储器单元的非易失半导体存储器设备(此后称为“两级非易失半导体存储器设备”)的两倍。 Therefore data storage capacity, the nonvolatile semiconductor memory device having four memory cells (hereinafter referred to as "four nonvolatile semiconductor memory device") is a non-volatile semiconductor memory device having a two-level memory cells (hereinafter referred to as twice the "two non-volatile semiconductor memory device") are.

在四级存储器单元中,临近级别的门限电压之间的余量一般为0.67V,这是非常窄的。 In the four memory cells, the balance level near the threshold voltage is generally between 0.67V, which is very narrow. 由于电子泄露等等,每个存储器单元的门限电压可能移动。 As electronic leakage, etc., the threshold voltage of each memory cell may move. 相应地,被编程为四个门限电平之一的存储器单元MC的门限电压可能移动到临近的门限电压。 Accordingly, is programmed to one of four threshold levels of the memory cell MC threshold voltage may move to near the threshold voltage. 结果,四级非易失半导体存储器设备具有可靠性低的问题。 As a result, four non-volatile semiconductor memory device having a low reliability problem.

另外,在四级存储器单元中,临近级别的门限电压之间的余量非常窄,并且施加到存储器单元的控制栅极的编程电压需要间隔非常窄的增量。 Further, in the four memory units, the balance level near the threshold voltage between the very narrow, and is applied to the control gate programming voltage of the memory cell requires a very narrow interval increment. 相应地,四级非易失半导体存储器设备具有编程所需时间非常长的问题。 Accordingly, four non-volatile semiconductor memory device having a very long time required for programming problem.

为了提高四级存储器单元的可靠性、以及减少编程所需时间,人们提出了具有三级存储器单元的非易失半导体存储器设备(此后称为“三级非易失半导体存储器设备”)。 In order to improve the reliability of the four memory cells, and to reduce the time required for programming, it is proposed a nonvolatile semiconductor memory device having a three-level memory cells (hereinafter referred to as "three non-volatile semiconductor memory device").

三级存储器单元MC,如图4所示,具有三级门限电压组G1、G2、G3。 Three memory cells MC, shown in Figure 4, having three threshold voltage groups G1, G2, G3. 在这种情况下,两个存储器单元MC形成一组,并且操作来存储3比特数据。 In this case, two memory cells MC to form a set, and the operation to store the 3-bit data.

因此,与两级存储器单元相比,三级存储器单元具有更大量的存储状态,由此具有相对较高的集成度。 Therefore, compared with the two-stage memory cell, three memory cell has a greater amount of stored state, thereby having a relatively high degree of integration. 另外,与四级存储器单元相比,三级存储器单元在门限电压组之间具有更大的间隔。 In addition, compared with the four memory cell, three memory cells having a threshold voltage greater spacing between groups. 由此,三级存储器单元具有相对较高的可靠性,并且相对减少了编程所需时间。 Accordingly, three memory cell has relatively high reliability, and relatively reduce the required programming time.

同时,现有的三级非易失半导体存储器设备,如图5所示,使用以下方法作为基本操作:从两个存储器单元MC1与MC2的每一个中,读取3级(G1、G2、G3)状态,并且将所读取的状态转换为3比特(BIT1、BIT2、BIT3)信息。 Meanwhile, conventional non-volatile semiconductor memory device of the three, as shown in Figure 5 using the following method as a basic operation: From the two memory cells MC1 and MC2 each of the, reading stage 3 (G1, G2, G3 ) state, and the state of the read is converted to 3 bits (BIT1, BIT2, BIT3) information. 因此,现有的三级非易失半导体存储器设备,如图6所示,具有以下缺点:其在页缓冲器20与数据输入/输出(I/O)线30之间,需要三级代码转换电路40,从而增加了对布局的限制。 Thus, three conventional nonvolatile semiconductor memory device, as shown in Figure 6, has the following disadvantages: it between the page buffer 20 and data input / output (I / O) lines 30, three requires transcoding circuit 40, thereby increasing the restriction on the layout.

另外,在现有的三级非易失半导体存储器设备中,在读取操作时,通过检查两个存储器单元的每一个的三级状态,来确定三比特数据值。 Further, in the conventional three-level nonvolatile semiconductor memory devices, when a read operation, by checking the two memory cells of each of the three state, three-bit data value is determined. 相应地,即使在确定一比特数据值的情况下,也需要进行总共四个数据取操作。 Accordingly, even in the case of one-bit data value is determined, but also the need for a total of four data fetch operation. 结果,现有的三级非易失半导体存储器设备具有总体取速度低的缺点。 As a result, the three conventional nonvolatile semiconductor memory device having a take-off speed low overall disadvantages.

另外,在现有的三级非易失半导体存储器设备中,在编程时依次编程两个存储器单元,因此其具有总体编程速度低的缺点。 Further, in the conventional three-level nonvolatile semiconductor memory devices, programming in sequence during programming two memory cells, and therefore it has the shortcomings of low overall programming speed.

发明内容 SUMMARY

一种实施例包括一种用于非易失半导体存储器设备的页缓冲器,包含:开关,被配置来将耦合于第一存储器单元的第一比特线耦合到耦合于第二存储器单元的第二比特线;第一锁存块,耦合于第一比特线,并且被配置来将第一锁存数据传送给第一存储器单元;以及第二锁存块,耦合于第二比特线及第一锁存块,并且被配置来将第二锁存数据传送给第二存储器单元。 A second switch configured to be coupled to the first bit line coupled to a first memory unit coupled to the second memory cells: An embodiment includes a method for the nonvolatile semiconductor memory device page buffer, comprising bit line; a first latch block coupled to the first bit line, and configured to latch the first data transfer to the first memory unit; and a second latch block coupled to the second bit line and a first lock block of memory, and is configured to transmit the second latch data to the second memory unit.

另一实施例包括一种对非易失半导体存储器设备编程的方法,包含:响应于第一数据比特,对第一存储器单元门限电压编程;响应于第二数据比特以及第一存储器单元门限电压,对第一存储器单元门限电压以及第二存储器单元门限电压中的一个编程;以及响应于第三数据比特以及第二存储器单元门限电压,对第一存储器单元门限电压以及第二存储器单元门限电压中的一个编程。 Another embodiment includes a non-volatile semiconductor memory device programming method, comprising: in response to the first data bit of the first memory cell threshold voltage programming; in response to the second data bit and the first memory cell threshold voltage, the first memory cell threshold voltage and a second memory cell threshold voltage in a programming; and in response to the third data bit and the second memory cell threshold voltage, the first memory cell threshold voltage and a second memory cell threshold voltages a programming.

另一实施例包括一种读取非易失半导体存储器的方法,包含:利用第一参考电压,读出第一存储器单元门限电压;利用第二参考电压,读出第二存储器单元门限电压;以及响应于读出第一存储器单元门限电压与第二存储器单元门限电压,生成数据比特。 Another embodiment includes a method for reading the nonvolatile semiconductor memory, comprising: using a first reference voltage, reads out the first memory cell threshold voltage; using a second reference voltage, the memory cell is read out of the second threshold voltage; and in response to the read out of the first memory cell threshold voltage and the second memory cell threshold voltage, to generate data bits.

附图说明 Brief Description

图1为显示典型晶体管型存储器单元的纵向剖面图;图2为显示典型两级存储器单元的门限电压的分布的图示;图3为显示典型四级存储器单元的门限电压的分布的图示;图4为显示典型三级存储器单元的门限电压的分布的图示;图5为常规非易失半导体存储器设备中的三比特数据与相关门限电压的表;图6为显示部分常规非易失半导体存储器设备的方框图;图7为显示根据实施例的部分非易失半导体存储器设备的方框图;图8为显示图7存储器阵列部分的方框图,其显示NAND型非易失半导体存储器设备的存储器阵列;图9为显示图7的页缓冲器的电路图;图10与11为分别显示根据实施例的非易失半导体存储器设备的编程方法中第一页编程的流程图与数据流图;图12为显示在根据实施例的非易失半导体存储器设备的编程方法中、在进行第一页编程之后、存储器单元的门限电压变化的视图;图13a与13b为显示根据实施例的非易失半导体存储器设备的编程方法中第二页编程的流程图;图14a与14b为基于图13a与13b的流程图的数据流图;图15为显示在根据实施例的非易失半导体存储器设备的编程方法中、在进行第二页编程之后、存储器单元的门限电压变化的视图;图16a与16b为显示根据实施例的非易失半导体存储器设备的编程方法中第三页编程的流程图;图17a与17b为基于图16a与16b的流程图的数据流图;图18为显示在根据实施例的非易失半导体存储器设备的编程方法中、在进行第三页编程之后、第一存储器单元与第二存储器单元的门限电压变化的视图;图19为显示在根据实施例的非易失半导体存储器设备的读取方法中、第一页读取步骤的流程图;图20a与20b为基于图19流程图的数据流图;图21为显示在根据实施例的非易失半导体存储器设备的读取方法中、第二页读取的流程图;图22a与22b为基于图21流程图的数据流图;图23a与23b为显示在根据实施例的非易失半导体存储器设备的读取方法中、第三页读取的流程图;图24a与24b为基于图23a与23b流程图的数据流图;图25为显示由根据实施例的非易失半导体存储器设备执行的页解码方法的图示;图26为显示由非易失半导体存储器设备执行的编程操作的实施例的流程图;图27为显示由非易失半导体存储器设备执行的读取操作的实施例的流程图;图28为显示根据另一实施例的图7的存储器阵列部分的图示;图29为显示根据另一实施例的图7的存储器阵列部分的图示,其显示NOR型非易失半导体存储器设备的存储器阵列;图30为显示根据另一实施例的图7的存储器阵列部分的图示,其显示OR型非易失半导体存储器设备的存储器阵列。 Figure 1 is a longitudinal sectional view of a typical transistor type memory cell; Fig. 2 is shown a typical two-stage gate memory cell threshold voltage distribution; FIG. 3 is a display illustrating a typical four door threshold voltage of the memory cell distribution; Figure 4 shows the distribution diagram for a typical three gate threshold voltage of the memory cell; FIG. 5 is a conventional non-volatile semiconductor memory device of three-bit data associated with the threshold voltage of the table; Fig. 6 is a part of a conventional nonvolatile semiconductor display a block diagram of a memory device; FIG. 7 is a block diagram illustrating part of a nonvolatile semiconductor memory device according to an embodiment; FIG. 8 is a block diagram showing a memory array portion of FIG. 7, which shows a memory array of the NAND type nonvolatile semiconductor memory device; FIG. Figure 9 is a circuit diagram of a display page buffer 7; Fig. 10 and 11 show an embodiment of the method of programming a non-volatile semiconductor memory device of the first page programming flowchart according to the data flow diagram; Fig. 12 is displayed in According to the programming method of the nonvolatile semiconductor memory device of the embodiment, after performing the first page programming, the threshold voltage of the memory cell gate change view; Fig. 13a and 13b to display the nonvolatile semiconductor memory device according to an embodiment of the programming flowchart of a method of programming the second page; Figure 14a and 14b is a flowchart based on Fig. 13a and 13b of the data flow diagram; Fig. 15 is displayed in accordance with the programming method of the nonvolatile semiconductor memory device of the embodiment, during the After the second page programming, the threshold voltage of the memory cell gate change view; Fig. 16a and 16b is a flowchart showing the programming method of embodiments of the nonvolatile semiconductor memory device according to the third page programming; Figures 17a and 17b is based on FIG. 16a and 16b is a flowchart of the data flow diagram; Fig. 18 is displayed after the programming method according to a non-volatile semiconductor memory device of the embodiment, during the third page programming, the first memory cell and the gate of the second memory cell limit voltage change view; Fig. 19 is displayed in the read method of an embodiment of the nonvolatile semiconductor memory device, the step of reading the first page of a flowchart according to; Figures 20a and 20b Figure 19 is a flowchart based on the data flow diagram ; Fig. 21 is displayed in the read method according to an embodiment of the nonvolatile semiconductor memory device, the second page of the flowchart is read; Fig. 22a and 22b is based on the flowchart of FIG. 21 the data flow diagram; Fig. 23a and 23b is displayed in the reading method of an embodiment of the nonvolatile semiconductor memory device, the third page is read according to a flowchart; Figure 24a and 24b Figures 23a and 23b based on the flowchart of the data flow diagram; Fig. 25 is displayed by the According to the illustrated page decoding method performed by the nonvolatile semiconductor memory device of the embodiment; FIG. 26 is a flowchart showing an embodiment of a nonvolatile semiconductor memory device to perform the program operation; Fig. 27 is displayed by the nonvolatile semiconductor flowchart of an embodiment of a memory device to perform the read operation; FIG. 28 is a diagram of another embodiment of the display according to a memory array portion 7 is not shown; FIG. 29 is a diagram of another embodiment according to the display memory array portion 7 illustration showing a memory array NOR type nonvolatile semiconductor memory device; FIG. 30 is a display portion of the memory array according to another embodiment shown in Fig. 7, which shows the memory OR type nonvolatile semiconductor memory device array.

具体实施方式 DETAILED DESCRIPTION

通过以下结合附图的详细描述,将会更清楚地理解本发明的以上以及其他目的、特征、以及其他优点。 By the following detailed description taken in conjunction, will be more clearly understood from the present invention, the above and other objects, features, and other advantages. 参照附图描述了优选实施例。 Described with reference to the drawings preferred embodiments. 在以下描述中,如果认为对相关公知功能与构造的详细描述会使实施例的理解不清楚,则省略详细描述。 In the following description, detailed descriptions of relevant if deemed well-known functions and structure of the embodiment will be understood unclear, the detailed description is omitted.

在非易失半导体存储器设备的实施例中,包含三级存储器单元。 In an embodiment the non-volatile semiconductor memory device, comprising the three memory cells. 如上所述,三级存储器单元(MC)具有三个门限电压组。 As described above, three memory cells (MC) has three threshold voltage groups. 可以根据第一参考电压VR1与第二参考电压VR2,划分存储器单元MC的门限电压组。 According to a first reference voltage VR1 and the second reference voltage VR2, dividing the memory cell MC threshold voltage group. 例如,可以将门限电压低于第一参考电压VR1的门限电压组指定为“第一门限电压组G1”,可以将门限电压在第一参考电压VR1与第二参考电压VR2之间的门限电压组指定为“第二门限电压组G2”。 For example, the threshold voltage may be lower than the first reference voltage VR1 threshold voltage group designated as "a first threshold voltage group G1", the gate threshold voltage can be between a first reference voltage VR1 and the second reference voltage VR2 threshold voltage group designated as "a second threshold voltage group G2". 另外,可以将门限电压高于第二参考电压VR2的门限电压组指定为“第三门限电压组G3”。 Further, the threshold voltage is higher than the second reference voltage VR2 threshold voltage group designated as "a third threshold voltage group G3".

可以分别在验证编程是否成功的验证读取操作以及读取所存储的数据的正常读取操作中,将第一参考电压VR1与第二参考电压VR2设置为不同的电平。 Can verify the success of the verification program, respectively the normal read operation and the reading operation to read the stored data, the first reference voltage VR1 and the second reference voltage VR2 is set to different levels. 在该文中,假定第一参考电压VR1与第二参考电压VR2中的每一个在验证读取操作以及正常读取操作中不变。 In this paper, assuming that the first reference voltage VR1 and the second reference voltage VR2 each read operation and the verify read operation normally constant. 但是,作出该假定是为了描述方便。 However, this assumption is made for convenience of description. 如上所述,此类参考电压可能变化。 As described above, such a reference voltage may vary.

图7为显示根据实施例的部分非易失半导体存储器设备的方框图。 Figure 7 is a block diagram showing the nonvolatile semiconductor memory device according to an embodiment of the display. 在图7中,显示有存储器阵列100、页缓冲器200、以及行解码器300。 In Figure 7, memory array 100 is displayed, the page buffer 200, and the row decoder 300.

图8为显示图7存储器阵列100的一部分的方框图,其显示NAND型非易失半导体存储器设备的存储器阵列。 Figure 8 is a block diagram of a portion of the memory array 100 shown in Figure 7, which shows a memory array of the NAND type nonvolatile semiconductor memory device. 存储器阵列100包含按行列矩阵结构排列的存储器单元MC。 The memory array 100 includes memory cells MC arranged in rows and columns of a matrix structure.

如图8所示,存储器阵列100包含第一单元串ST1与第二单元串ST2。 8, the memory array 100 includes a first cell string ST1 and the second cell string ST2. 第一单元串ST1耦合至第一比特线,第二单元串ST2耦合至第二比特线。 The first cell string ST1 is coupled to a first bit line, a second cell string ST2 coupled to the second bit line. 第一单元串ST1包含多个第一存储器单元MC1,第二单元串ST2包含多个第二存储器单元MC2。 The first cell string ST1 comprises a plurality of first memory cell MC1, the second cell string ST2 comprises a plurality of second memory cell MC2. 第一存储器单元MC1与第二存储器单元MC2可以电气方式编程与擦除,并且保持数据,即使没有供电也如此。 The first memory cell MC1 and MC2 second memory cell can be electrically programmed and erased and maintain data, even if no power is also true. 一个第一存储器单元MC1与一个第二存储器单元MC2可以形成一对。 A first memory cell MC1 and a second memory cell MC2 may form a pair.

在第一存储器单元MC1与第二存储器单元MC2的对中,可以对形成单个组的第一到第三比特数据编程。 In the first memory cell MC1 and the second memory cell MC2 alignment, the first to third bits of data may be programmed to form a single group. 另外,可以读取根据第一存储器单元MC1与第二存储器单元MC2对的门限电压的存储状态,作为第一到第三比特数据。 Further, the threshold voltage can be read according to a first memory cell MC1 and the second memory cell MC2 to the door storage state, as the first to third bit data.

在此处,所使用的第一到第三比特数据可以标记为“BIT1 to BIT3”(BIT1到BIT3)。 Here, the first to third bit data used may be marked as "BIT1 to BIT3" (BIT1 to BIT3).

优选地,形成对的第一存储器单元MC1与第二存储器单元MC2分别位于第一单元串ST1与第二单元串ST2。 Preferably, the formation of the first memory cell MC1 and the second memory cell MC2 are located on the first cell string ST1 and the second cell string ST2.

再次参照图7,通过第一比特线BL1与第二比特线BL2,页缓冲器200耦合至存储器阵列。 Referring again to Figure 7, through the first bit line BL1 and a second bit line BL2, the page buffer 200 is coupled to the memory array. 页缓冲器200被驱动来将形成组的第一到第三比特数据BIT1到BIT3映射到第一存储器单元MC1与第二存储器单元MC2对的门限电压组。 The page buffer 200 is driven to the formation of the first to third bit data BIT1 to BIT3 groups mapped to the first memory cell MC1 and the second memory cell MC2 to the threshold voltage group.

图9为详细显示图7的页缓冲器200的电路图。 Figure 9 is a schematic diagram of the page buffer 7 200 shown in detail. 页缓冲器200包含开关SW、第一锁存块LTBK1与第二锁存块LTBK2。 The page buffer 200 includes a switch SW, a first latch block LTBK1 and the second latch block LTBK2.

可以响应于开关控制信号SWC,控制该开关,以将第一比特线BL1连接到第二比特线BL2。 In response to the switching control signal SWC, controlling the switch to the first bit line BL1 connected to the second bit line BL2.

第一锁存块LTBK1可以存储第一锁存数据DLT1。 The first latch block LTBK1 first latch can store data DLT1. 另外,通过第一比特线BL1,第一锁存块LTBK1可以发送/接收去向/来自存储器阵列100的数据。 Further, through the first bit line BL1, the first latch block LTBK1 can send / receive to / from the data memory array 100. 第一缓冲器块LTBK1包含读出节点NSEN、第一锁存单元210、第一触发单元220、以及翻转触发单元230。 The first buffer contains the readout node block LTBK1 NSEN, the first latch unit 210, the first trigger unit 220, and flip the trigger unit 230.

响应于第一比特线连接信号,将读出节点NSEN连接到第一比特线BL1。 In response to the first bit line connected to the signal, the readout node NSEN connected to the first bit line BL1. 然后,通过比特线闭锁元件240,可以提供读出节点NSEN上的数据。 Then, bit line latch member 240 may be provided to read the data on the node NSEN.

第一锁存单元210锁存并存储第一锁存数据DLT1。 The first latch unit 210 latches and stores the first latch data DLT1. 响应于第一比特线选择信号BLSLT1,第一锁存单元210将第一锁存数据DLT1映射到第一比特线BL1。 In response to the first bit line selection signal BLSLT1, the first latch unit 210 of the first latch data DLT1 is mapped to a first bit line BL1.

第一触发单元220可以根据读出节点NSEN的电压电平或者第二缓冲器块LTBK2的第二锁存数据DLT2,将第一锁存数据DLT1改变为逻辑H状态。 The first trigger unit 220 may read out the data according to the second latch node NSEN voltage level or the second buffer block LTBK2 of DLT2, the first latch data DLT1 is logic H state change. 在此处,所使用的逻辑L状态与逻辑H状态可以分别被指定为“第一逻辑状态”与“第二逻辑状态”。 Here, the logic L state and the logic H state to be used may be respectively designated as "a first logic state" and "a second logic state."

详细地,第一触发单元220包含传送单元221与触发电路223。 In detail, the first trigger unit 220 includes a transmission unit 221 and the trigger circuit 223. 响应于传送控制信号TR,使能传送单元221。 In response to transfer control signal TR, so that unit 221 can be transmitted. 在这种情况下,根据第二缓冲器块LTBK2的第二锁存数据DLT2,传送单元221将第一锁存数据DLT1从逻辑L状态触发到逻辑H状态。 In this case, DLT2, the transmission unit 221 of the first latch data DLT1 is triggered according to a second latch data from the second buffer block LTBK2 logic L state to a logic H state.

响应于第一锁存控制信号LCH1,使能触发电路223。 In response to the first latch control signal LCH1, enabling trigger circuit 223. 在这种情况下,根据读出节点NSEN的电压电平,触发电路223进行控制操作,从而在第一锁存单元210中锁存的第一锁存数据DLT1被设置为逻辑H状态。 In this case, based on the read node NSEN voltage level, the trigger circuit 223 performs a control operation so that the first latch data latched in the first latch unit 210 of DLT1 is set to logic H state.

根据读出节点NSEN的电压电平与第二缓冲器块LTBK2的第二锁存数据DLT2,翻转触发单元230可以将在第一锁存单元210中锁存的第一锁存数据DLT1改变为逻辑L状态。 According to a second latch data read node NSEN voltage level and the second buffer block LTBK2 of DLT2, flip DLT1 trigger unit 230 may be changed to logic in the first latch data latched in the first latch unit 210 of L state. 根据读出节点NSEN的电压电平,翻转触发单元230进行控制操作,从而第一锁存数据DLT1可以改变。 According to the read node NSEN voltage level, flip trigger unit 230 performs a control operation, so that the first latch data DLT1 may vary. 例如,当在第二锁存块LTBK2中锁存的第二锁存数据DLT2的逻辑状态为逻辑L时,翻转触发单元230不会将第一锁存数据DLT1改变为逻辑L状态。 For example, when latched in the second latch block LTBK2 the logic state of the second latch data DLT2 is logic L, flip trigger unit 230 does not change the first latch data DLT1 is logic L state.

优选地,第一缓冲器块LTBK1还包含第一输入/输出单元250。 Preferably, the first buffer block LTBK1 further comprises a first input / output unit 250. 第一输入/输出单元250可以装入(load)第一锁存单元210的第一锁存数据DLT1,或者可以将第一锁存数据DLT1提供给内部数据线IDL。 A first input / output unit 250 may load (load) of the first latch unit 210 of the first latch data DLT1, or may be supplied to the first latch data DLT1 internal data line IDL.

响应于读出预充电信号/PRE,读出预充电块201用电源电压VDD对读出节点NSEN预充电。 In response to the read precharge signal / PRE, the precharge block 201 is read out by the read power supply voltage VDD node NSEN precharged.

参照图9,第二锁存块LTBK2可以存储第二锁存数据DLT2。 Referring to Figure 9, the second latch block LTBK2 can store the second latch data DLT2. 另外,通过第二比特线BL2,第二锁存块LTBK2可以发送/接收去向/来自存储器阵列100的数据。 Further, the second bit line BL2, the second latch block LTBK2 can transmit / receive to / from the data memory array 100.

第二缓冲器块LTBK2包含第二锁存单元260与第二触发单元270。 The second buffer block LTBK2 comprises a second latch unit 260 and the second trigger unit 270. 第二锁存单元260锁存并存储第二锁存数据DLT2。 Second latch unit 260 latches and stores the second latch data DLT2. 另外,响应于第二比特线选择信号BLSLT2,第二锁存单元260可以发送/接收到第二比特线BL2的第二锁存数据DLT2。 Further, in response to the second bit line selection signal BLSLT2, the second latch unit 260 may transmit / receive data to the second latch of the second bit line BL2 DLT2.

第二触发单元270可以根据读出节点NSEN的电压电平,将第二锁存数据DLT2改变为逻辑H状态。 The second trigger unit 270 can read out the voltage level of node NSEN and the second latch data DLT2 is changed to a logic H state. 响应于第二锁存控制信号LCH2,使能第二触发单元270。 In response to the second latch control signal LCH2, enabling the second trigger unit 270. 在这种情况下,根据读出节点NSEN的电压电平,第二触发单元270进行控制操作,从而在第二锁存单元260中锁存的第二锁存数据DLT2被改变为逻辑H状态。 In this case, based on the read node NSEN voltage level, the second trigger unit 270 performs a control operation so that the second latch element latched in the second latch data DLT2 260 is changed to a logic H state.

再次参照图7,行解码器300耦合至存储器阵列100,以控制选定字线WL的电压电平。 Referring again to FIG. 7, a row decoder 300 coupled to the memory array 100 to control the selected word line WL voltage level. 根据行地址XADD,行解码器300激活选定字线WL。 According to the row address XADD, the row decoder 300 to activate the selected word line WL. 行解码器300提供串选择信号SSL与地选择信号GSL。 Row decoder 300 provides a string selection signal SSL and ground selection signal GSL. 数据输入/输出电路700将在页缓冲器200中锁存的数据输出到外部系统,并且将从外部系统输入的数据装到页缓冲器200上。 Data input / output circuit 700 will be latched in the page buffer 200 outputs the data to an external system, and data input from the external system is attached to the page buffer 200.

图7的非易失半导体存储器设备还包含页识别电路500与控制信号生成电路600。 Figure 7 is a non-volatile semiconductor memory device further comprises a page identification circuit 500 and the control signal generating circuit 600.

页识别电路500接收行地址XADD,并且提供页信息PGIF给控制信号生成电路600。 Page identification circuit 500 receives the row address XADD, and to provide page information PGIF to the control signal generating circuit 600. 在这种情况下,页信息PGIF包含指示第一到第三页中哪页对应于收到的行地址XADD的信息。 In this case, the page PGIF contains information indicating which of the first page to the third page corresponding to the received row address XADD information.

响应于操作命令CMD与页信息PGIF,控制信号生成电路600确定编程操作、读取操作等等,并且向页缓冲器200、行解码器300、以及数据I/O电路400提供根据所确定的操作的控制信号。 In response to the command CMD and page PGIF, the control signal generating circuit 600 determines a program operation, a read operation and the like, and provided to the page buffer 200, row decoder 300, and data I / O circuit 400 in accordance with the determined operation The control signal.

同时,在该实施例中,假定内部数据线IDL上的数据值等于第一到第三比特数据BIT1到BIT3中每一个的数据值,其在进行编程或读取操作时从页缓冲器之外提供。 Meanwhile, in this embodiment, assumed that the data values on the internal data line IDL is equal to the first to third bit data BIT1 to BIT3 of data values in each, other than from the page buffer during programming or reading its operation available. 即,假定当每个比特数据值为“1”时,内部数据线IDL的逻辑电平为逻辑H,而当每个比特数据值为“0”时,内部数据线IDL的逻辑电平为逻辑L。 That is, assuming that when each bit data value is "1", the internal data line IDL is logic level is a logic H, and when each bit data value is "0", the internal data line IDL is logic level is a logic L.

如图3所示,在三级非易失半导体存储器设备中,在页缓冲器与数据I/O线之间,不需要三级代码转换电路。 As shown in Figure 3, in the three non-volatile semiconductor memory device, between the page buffer and the data I / O lines, does not require three code conversion circuit. 由此,显著减少了对布局的限制。 Thus, significantly reducing restrictions on the layout.

接着描述非易失半导体存储器设备编程方法的实施例。 Next, embodiments are described nonvolatile semiconductor memory device programming methods. 对存储器单元对的编程按照第一到第三页编程步骤的次序进行,其分别使用第一到第三比特数据BIT1到BIT3。 Programming the memory cell in the order of the first to the third page programming steps performed, using respectively the first to third bit data BIT1 to BIT3.

图10与11为分别显示非易失半导体存储器设备编程方法的实施例中第一页编程的流程图与数据流图。 Figures 10 and 11 show embodiments of the nonvolatile semiconductor memory device programming method of the first page programming flowchart and data flow diagram. 在第一页编程时,根据第一比特数据BIT1,将第一存储器单元MC1的门限电压编程为第二门限电压组G2。 In the first page program, according to the first bit data BIT1, the first memory cell MC1 threshold voltage programmed to the second threshold voltage group G2.

参照图10,在S1110,第一锁存数据DLT1被重置为逻辑H状态。 Referring to FIG. 10, in S1110, the first latch data DLT1 is reset to a logic H state. 在S1120,通过内部数据线IDL,装入第一比特数据BIT1,作为第一锁存数据DLT1(参照图11的A1)。 In S1120, via the internal data line IDL, fitted into the first bit data BIT1, as the first latch data DLT1 (A1 of FIG. 11). 即,当第一比特数据BIT1为“0”时,第一锁存数据DLT1被锁存为逻辑L状态。 That is, when the first bit data BIT1 is "0", the first latch data DLT1 is latched to a logic L state. 相反,当第一比特数据BIT1为“1”时,第一锁存数据DLT1被维持在逻辑H状态。 On the contrary, when the first bit data BIT1 is "1", the first latch data DLT1 is maintained at a logic H state.

接着,在S1130,利用第一锁存数据DLT1,对第一存储器单元MC1进行编程(参照图11的A2)。 Subsequently, in S1130, the use of the first latch data DLT1, for programming the first memory cell MC1 (see Fig. 11 A2). 即,如果第一比特数据BIT1为“0”,则第一存储器单元MC1的门限电压增加,而如果第一比特数据BIT1为“1”,则第一存储器单元MC1的门限电压被维持在其先前状态上。 That is, if the first bit data BIT1 is "0", the first memory cell MC1 of the threshold voltage is increased, and if the first bit data BIT1 is "1", the first memory cell MC1 of the threshold voltage is maintained at its previous Status on.

另外,在S1140,根据第一参考电压VR1,第一存储器单元MC1的门限电压被反映到读出节点NSEN上(参照图11的A3)。 Further, in S1140, according to the first reference voltage VR1, the first memory cell MC1 is reflected in the threshold voltage read out to the node NSEN (refer Fig. 11 A3). 即,在读出节点NSEN上,反映第一存储器单元MC1的门限电压是否高于第一参考电压VR1。 That is, in the readout node NSEN, reflecting the first memory cell MC1 is higher than the threshold voltage of the first reference voltage VR1. 例如,如果第一存储器单元MC1的门限电压高于第一参考电压VR1,则读出节点NSEN的电压电平被调整到电源电压VDD。 For example, if the first memory cell MC1 is higher than the threshold voltage of the first reference voltage VR1, the read-out voltage level of node NSEN is adjusted to the supply voltage VDD. 相反,如果第一存储器单元MC1的门限电压低于第一参考电压VR1,则读出节点NSEN的电压电平被调整到地电压VSS。 Conversely, if the first memory cell MC1 of the threshold voltage is lower than the first reference voltage VR1, the read-out voltage level of node NSEN is adjusted to the ground voltage VSS.

在S1150,生成第一锁存控制信号LCH1,作为H脉冲。 In S1150, generating a first latch control signal LCH1, as an H pulse. 此时,根据读出节点NSEN的电压电平,第一锁存数据DLT1选择性地改变到逻辑H状态(参照图11的A4)。 At this time, based on the read node NSEN voltage level, the first latch data DLT1 selectively changes to a logic H state (see Fig. 11 A4). 换言之,如果读出节点NSEN的电压电平为电源电压VDD,则第一锁存数据DLT1被设置为逻辑H状态。 In other words, if the read node NSEN voltage level of the supply voltage VDD, the first latch data DLT1 is set to a logic H state. 相反,如果读出节点NSEN的电压电平被调整到地电压VSS,则第一锁存数据DLT1被维持在其先前数据状态上。 Conversely, if the read-out voltage level of node NSEN is adjusted to the ground voltage VSS, the first latch data DLT1 is maintained at its previous state data.

因此,在进行了S1150之后第一锁存数据DLT1为逻辑L状态这一事实意味着:虽然对第一存储器单元MC1进行编程,但是第一存储器单元MC1的门限电压没有被调整到根据第一比特数据BIT1的第一或第二门限电压组G1或G2的目标。 Thus, after performing the first S1150 latch data DLT1 is logic L state This fact means that: Although the first memory cell MC1 to be programmed, but first memory cell MC1 of the threshold voltage is not adjusted according to the first bit data BIT1 is the first or second threshold voltage group G1 or G2 target.

在S1160,生成第一数据线控制信号DIO1,作为H脉冲,从而读出第一锁存数据DLT1的逻辑状态(参照图11的A5)。 In S1160, generating a first data line control signal DIO1, as an H pulse, thereby reading out the first latch data DLT1 is logic state (A5 with reference to FIG. 11). 在S1170,验证编程是否成功。 In S1170, verify the programming is successful. 在该实施例中,在S1160读取的数据的逻辑H状态指示编程成功。 In this embodiment, the logic H state of the data read in S1160 indicate successful programming. 相反,在S1160读取的数据的逻辑L状态指示编程失败。 In contrast, in the logic of the read data S1160 L status indication failed programming.

如果编程失败,则流程返回到S1130。 If the program fails, the flow returns to S1130. 在这种情况下,在S1130,选定字线的电压电平逐步增加。 In this case, in S1130, the selected word line voltage level gradually increased.

图12为显示在根据实施例的非易失半导体存储器设备的编程方法中、在进行第一页编程之后、第一存储器单元MC1与第二存储器单元MC2的门限电压变化的视图。 Figure 12 is a programming method according to an embodiment of the nonvolatile semiconductor memory device, after performing a first page program, the first memory cell MC1 and the second memory cell MC2 of the threshold voltage variation of view.

当第一比特数据BIT1为“1”(情况11)时,第一存储器单元MC1与第二存储器单元MC2的门限电压都维持在擦除状态,即在第一门限电压组G1上。 When the first bit data BIT1 is "1" (the case 11), the first memory cell MC1 and the second memory cell MC2 is maintained at the threshold voltage of the erased state, i.e., on the first threshold voltage group G1.

当第一比特数据BIT1为“0”(情况12)时,第一存储器单元MC1的门限电压被调整到第二门限电压组G2,并且,第二存储器单元MC2的门限电压被维持在第一门限电压组G1上。 When the first bit data BIT1 is "0" (case 12), the first memory cell MC1 is adjusted to the threshold voltage of the second threshold voltage group G2, and the second memory cell MC2 of the threshold voltage is maintained at the first threshold the voltage group G1.

图13a与13b为显示根据实施例的非易失半导体存储器设备编程方法中第二页编程的流程图。 Figures 13a and 13b is displayed according to the nonvolatile semiconductor memory device programming method of an embodiment of the second page programming flowchart. 另外,图14a与14b为基于图13a与13b的流程图的数据流图。 Further, FIG. 14a and 14b is a flowchart based on Fig. 13a and 13b are data flow diagram. 在第二页编程时,根据第二比特数据BIT2、以及第一存储器单元MC1的门限电压,将第一存储器单元MC1或第二存储器单元MC2的门限电压编程为第三门限电压组G3。 In the second page program, according to the second bit data BIT2, the first memory cell MC1 and the threshold voltage, the first memory cell MC1 or the second memory cell MC2 is programmed to a third threshold voltage threshold voltage group G3.

参照图13a与13b,在S1205,第一锁存数据DLT1与第二锁存数据DLT2被重置为逻辑H状态。 Referring to Figures 13a and 13b, at S1205, the first latch data DLT1 and the second latch data DLT2 are reset to a logic H state. 在S1210,通过内部数据线IDL,利用第二比特数据BIT2,进行控制第一锁存数据DLT1与第二锁存数据DLT2的数据装入步骤(参照图14a的B1)。 In S1210, via the internal data line IDL, using the second bit data BIT2, control of the first latch data DLT1 and the second latch data DLT2 of the data loaded in step (see Fig. B1 14a of). 即,当第二比特数据BIT2为“0”时,第一锁存数据DLT1与第二锁存数据DLT2被锁存为逻辑L状态。 That is, when the second bit data BIT2 is "0", the first latch data DLT1 and the second latch data DLT2 are latched as a logic L state. 相反,当第二比特数据BIT2为“1”时,第一锁存数据DLT1与第二锁存数据DLT2被维持在逻辑H状态。 On the contrary, when the second bit data BIT2 is "1", the first latch data DLT1 and the second latch data DLT2 is maintained at a logic H state.

此后,在S1215与S1220,利用在第一页编程步骤中在第一存储器单元中编程的数据,进行控制在数据装入步骤控制的第二锁存数据DLT2的先前数据反映步骤。 Thereafter, in S1215 and S1220, the use of programming data in the first page programming step in a first memory unit, the second latch data control step of controlling the loading of data DLT2 previous data reflect step.

详细地,在S1215,根据第一参考电压VR1,将在第一页编程步骤中编程的第一存储器单元MC1的数据反映在读出节点NSEN上(参照图14a的B2)。 In detail, at S1215, in accordance with a first reference voltage VR1, the first page will be programmed in the programming step of the first memory cell MC1 is reflected on the read node NSEN (refer to FIG B2 14a of). 另外,在S1220,利用在S1215获得的读出节点NSEN的电压电平,控制第二锁存数据DLT2(参照图14a的B3)。 Further, in S1220, the use of the read node NSEN obtained at S1215 voltage level, controlling the second latch data DLT2 (refer FIG B3 14a of). 因此,如果第一比特数据BIT1为“0”,则读出节点NSEN为逻辑H状态,并且第二锁存数据DLT2改变为逻辑H状态。 Therefore, if the first bit data BIT1 is "0", the read node NSEN is a logic H state, and the second latch data DLT2 is changed to a logic H state. 相反,如果第一比特数据BIT1为“1”,则读出节点NSEN为逻辑L状态,并且第二锁存数据DLT2被维持在其当前状态上。 Conversely, if the first bit data BIT1 is "1", the readout node NSEN logic L state, and the second latch data DLT2 is maintained in its current state.

在S1225,传送控制信号TR被激活为逻辑H状态。 In S1225, the transmission control signal TR is activated to a logic H state. 因此,在S1225,响应于第二锁存数据DLT2,将第一锁存数据DLT1选择性地设置为逻辑H状态(参照图14a的B4与B4′)。 Therefore, in S1225, in response to the second latch data DLT2, the first latch data DLT1 is selectively set to a logic H state (B4 with reference to Figure 14a B4 '). 即,如果第二锁存数据DLT2当前为“1”,则第一锁存数据DLT1被维持在其先前状态上。 That is, if the second latch data DLT2 is currently "1", the first latch data DLT1 is maintained at its previous state. 相反,如果第二锁存数据DLT2为“0”,则第一锁存数据DLT1改变为逻辑H状态。 Conversely, if the second latch data DLT2 is "0", the first latch data DLT1 is logic H state change.

以下描述在进行了S1225之后,第一锁存数据DLT1与第二锁存数据DLT2的逻辑状态。 The following description After conducting S1225, the first latch data DLT1 and the second latch data of logic state DLT2.

即,如果第二比特数据BIT2为“1”,则第一锁存数据DLT1与第二锁存数据DLT2为逻辑H,而不管第一比特数据BIT1的值为何。 That is, if the second bit data BIT2 is "1", the first latch data DLT1 and the second latch data DLT2 is logic H, regardless of the value of the first bit data BIT1 is why.

另外,如果第一比特数据BIT1为“0”且第二比特数据BIT2为“0”,则第一锁存数据DLT1为逻辑L,而第二锁存数据DLT2为逻辑H。 Further, if the first bit data BIT1 is "0" and the second bit data BIT2 is "0", the first latch data DLT1 is logic L, and the second latch data DLT2 is logic H.

另外,如果第一比特数据BIT1为“1”且第二比特数据BIT2为“0”,则第一锁存数据DLT1为逻辑H,而第二锁存数据DLT2为逻辑L。 Further, if the first bit data BIT1 is "1" and the second bit data BIT2 is "0", the first latch data DLT1 is logic H, and the second latch data DLT2 is logic L.

此后,在S1230,利用第一锁存数据DLT1与第二锁存数据DLT2,对第一存储器单元MC1与第二存储器单元MC2进行编程(参照图16b的B5与B5′)。 Thereafter, in S1230, the use of the first latch data DLT1 and the second latch data DLT2, on the first memory cell MC1 and the second memory cell MC2 is programmed (see FIG. 16b, B5 and B5 '). 即,如果第二比特数据BIT2为“1”,则第一存储器单元MC1的门限电压被维持在其先前状态上。 That is, if the second bit data BIT2 is "1", the first memory cell MC1 of the threshold voltage is maintained at its previous state.

同时,如果第二比特数据BIT2为“0”,则将第一存储器单元MC1或第二存储器单元MC2的门限电压调整到第三门限电压组G3。 Meanwhile, if the second bit data BIT2 is "0", the first memory cell MC1 or the second memory cell MC2 is adjusted to the threshold voltage of the third threshold voltage group G3. 换言之,如果第一比特数据BIT1为“0”,则将第一存储器单元MC1的门限电压调整到第三门限电压组G3。 In other words, if the first bit data BIT1 is "0", the first memory cell MC1 is adjusted to the threshold voltage of the third threshold voltage group G3. 如果第一比特数据BIT1为“1”,则将第二存储器单元MC2的门限电压调整到第三门限电压组G3。 If the first bit data BIT1 is "1", the second memory cell MC2 is adjusted to the threshold voltage of the third threshold voltage group G3.

因此,如果作为第一页编程的结果、已经将第一存储器单元MC1的门限电压调整到第二门限电压组G2,则在第二页编程时,将第一存储器单元MC1的门限电压调整到第三门限电压组G3。 Therefore, if, as a result of the first page programming, the first memory cell MC1 has a threshold voltage adjusted to the second threshold voltage group G2, then the second page program, the first memory cell MC1 is adjusted to the threshold voltage of the first three threshold voltage group G3. 相反,当作为第一页编程的结果、已经将第一存储器单元MC1的门限电压维持在第一门限电压组G1上时,则在第二页编程时,响应于第二比特数据BIT2,将第二存储器单元MC2的门限电压调整到第三门限电压组G3。 In contrast, when as a result of the first page programming, the first memory cell MC1 has a threshold voltage is maintained at the first threshold voltage group G1, at the time of the second page program, in response to the second bit data BIT2, the first second memory cell MC2 is adjusted to the threshold voltage of the third threshold voltage group G3.

接着,在S1235,根据第二参考电压VR2,将第一存储器单元MC1的门限电压反映在读出节点NSEN上(参照图14b的B6)。 Subsequently, in S1235, according to the second reference voltage VR2, the first memory cell MC1 is reflected in the threshold voltage (B6 reference to FIG. 14b) is in the readout node NSEN. 即,在读出节点NSEN上反映第一存储器单元MC1的门限电压是否高于第二参考电压VR2。 That is, in the readout node NSEN reflect the first memory cell MC1 is higher than the threshold voltage of the second reference voltage VR2.

在S1240,生成第一锁存控制信号LCH1,作为H脉冲。 In the S1240, the first latch control signal is generated LCH1, as H pulses. 在这种情况下,根据读出节点NSEN的电压电平,第一锁存数据DLT1选择性地改变到逻辑H状态(参照图14b的B7)。 In this case, based on the read node NSEN voltage level, the first latch data DLT1 selectively changes to a logic H state (see Fig. 14b, B7).

另外,在S1245,根据第二参考电压VR2,将第二存储器单元MC2的门限电压反映在读出节点NSEN上(参照图14b的B8)。 Further, in S1245, according to the second reference voltage VR2, the second memory cell MC2 is reflected in the threshold voltage on the sense node NSEN (refer to FIG. 14b, B8). 即,在读出节点NSEN上反映第二存储器单元MC2的门限电压是否高于第二参考电压VR2。 That is, in the readout node NSEN reflect the second memory cell MC2 is higher than the threshold voltage of the second reference voltage VR2.

在S1250,生成第二锁存控制信号LCH2,作为H脉冲。 In S1250, the second latch control signal generating LCH2, as H pulse. 在这种情况下,根据读出节点NSEN的电压电平,第二锁存数据DLT2选择性地从逻辑L状态触发到逻辑H状态(参照图14b的B9)。 In this case, based on the read node NSEN voltage level, the second latch data DLT2 selectively triggered from a logic L state to a logic H state (see Fig. B9 14b of).

在S1255,同时或依次生成第一数据线控制信号DIO1与第二数据线控制信号DIO2,作为H脉冲,并且读出第一锁存数据DLT1与第二锁存数据DLT2的逻辑状态(参照图14b的B10)。 In S1255, simultaneously or sequentially to generate a first data line control signal DIO1 and second data line control signal DIO2, as an H pulse, and reads out the first latch data DLT1 and the second latch data DLT2 is logic state (see Fig. 14b The B10). 在S1260,验证编程是否成功。 In S1260, verify the programming is successful.

对于本领域技术人员来说,显然在该实施例的非易失半导体存储器设备中,可以使用如果第一存储器单元MC1与第二存储器单元MC2中任何一个的门限电压被调整为第三门限电压组G3、则能够验证编程是否成功的电路,作为编程验证电路,用来在S1260验证编程是否成功。 For the skilled person, it is clear in the nonvolatile semiconductor memory device of this embodiment may be used if the first memory cell MC1 and the second memory cell MC2 in any one of the threshold voltage is adjusted to the third threshold voltage group G3, it is possible to verify the success of the programming circuit, as a programming verification circuit for the S1260 verify the programming is successful.

如果编程失败,则重复S1230及以下步骤。 If the program fails, the S1230 and repeat the following steps. 此时,在S1230,选定字线或比特线的电压电平逐步增加。 In this case, in S1230, the selected word line or the bit line voltage level gradually increased.

当参照图10的S1140到S1150时,本领域技术人员可以明白图13b的S1235、S1240、S1245、以及S1250的读出节点NSEN电压电平以及第一锁存数据DLT1与第二锁存数据DLT2逻辑状态的变化,因此省略其详细描述。 When referring to S1140 to S1150 of Figure 10, the skilled in the art can appreciate 13b of FIG S1235, S1240, S1245, and S1250 of the read node NSEN voltage level and the first latch data DLT1 and the second latch data DLT2 logic change in state, and therefore detailed description is omitted.

图15为显示在根据实施例的非易失半导体存储器设备的编程方法中、在进行第二页编程之后、第一存储器单元MC1与第二存储器单元MC2的门限电压变化的视图。 Figure 15 is a programming method in accordance with an embodiment of the nonvolatile semiconductor memory device, after performing the second page programming, the first memory cell MC1 and the second memory cell MC2 of the threshold voltage variation of view.

当第一比特数据BIT1与第二比特数据BIT2都为“1”(情况21)时,第一存储器单元MC1与第二存储器单元MC2的门限电压都维持在擦除状态,即在第一门限电压组G1上。 When the first bit data and second bit data BIT1 BIT2 are "1" (the case 21), the first memory cell MC1 and the second memory cell MC2 is maintained at the threshold voltage of the erased state, i.e., a first threshold voltage the group G1.

当第一比特数据BIT1为“1”且第二比特数据BIT2为“0”(情况22)时,第一存储器单元MC1的门限电压被维持在第一门限电压组G1上,第二存储器单元MC2的门限电压被调整到第三门限电压组G3。 When the first bit data BIT1 is "1" and the second bit data BIT2 is "0" (case 22), the first memory cell MC1 of the threshold voltage is maintained at the first threshold voltage group G1, the second memory cell MC2 The threshold voltage is adjusted to the third threshold voltage group G3.

当第一比特数据BIT1为“0”且第二比特数据BIT2为“1”(情况23)时,第一存储器单元MC1的门限电压被维持在第二门限电压组G2上,第二存储器单元MC2的门限电压被维持在第一门限电压组G1上。 When the first bit data BIT1 is "0" and the second bit data BIT2 is "1" (case 23), the first memory cell MC1 of the threshold voltage is maintained at the second threshold voltage group G2, the second memory cell MC2 The threshold voltage is maintained at the first threshold voltage group G1.

当第一比特数据BIT1与第二比特数据BIT2都为“0”(情况24)时,第一存储器单元MC1的门限电压被调整到第三门限电压组G3,第二存储器单元MC2的门限电压被维持在第一门限电压组G1上。 When the first bit data and second bit data BIT1 BIT2 are "0" (case 24), the first memory cell MC1 of the threshold voltage is adjusted to the third threshold voltage group G3, the second memory cell MC2 is the threshold voltage maintained at the first threshold voltage group G1.

图16a与16b为显示根据实施例的非易失半导体存储器设备编程方法中第三页编程的流程图。 Figure 16a is a flowchart showing a non-volatile semiconductor memory device programming method of an embodiment of the third page programming in accordance with 16b. 图17a与17b为基于图16a与16b的流程图的数据流图。 Figure 17a and 17b is a flowchart based on Fig. 16a and 16b of the data flow diagram. 在第三页编程时,根据第三比特数据BIT3,将第一存储器单元MC1或第二存储器单元MC2的门限电压编程为第二门限电压组G2。 When the third page programming, according to the third bit data BIT3, the first memory cell MC1 or the second memory cell MC2 is programmed to the second threshold voltage threshold voltage group G2.

参照图16a与16b,在S1305,第一锁存数据DLT1与第二锁存数据DLT2被重置为逻辑H状态。 Referring to Figures 16a and 16b, at S1305, the first latch data DLT1 and the second latch data DLT2 are reset to a logic H state. 在S1310,通过内部数据线IDL,利用第三比特数据BIT3,装入第一锁存数据DLT1与第二锁存数据DLT2(参照图17a的C1)。 In S1310, via the internal data line IDL, using a third bit data BIT3, loaded into the first latch data DLT1 and the second latch data DLT2 (refer FIG. 17a, C1). 即,当第三比特数据BIT3为“0”时,第一锁存数据DLT1与第二锁存数据DLT2被锁存为逻辑L状态。 That is, when the third bit data BIT3 is "0", the first latch data DLT1 and the second latch data DLT2 are latched as a logic L state. 相反,当第三比特数据BIT3为“1”时,第一锁存数据DLT1与第二锁存数据DLT2被维持在逻辑H状态。 On the contrary, when the third bit data BIT3 is "1", the first latch data DLT1 and the second latch data DLT2 is maintained at a logic H state.

接着,在S1315与S1320,利用在第二页编程中在第二存储器单元MC2中编程的数据,控制第二锁存数据DLT2。 Subsequently, in S1315 and S1320, using the data in the second page program in the second memory cell MC2 in the programmed control of the second latch data DLT2.

详细地,在S1315,根据第二参考电压VR2,将在第二页编程步骤中编程的第二存储器单元MC2的数据反映在读出节点NSEN上(参照图17a的C2)。 In detail, at S1315, according to the second reference voltage VR2, the programming of the second page programming step, the second memory cell MC2 is reflected on the read node NSEN (refer to FIG. 17a, C2). 另外,在S1320,利用在步骤S1315获得的读出节点NSEN的电压电平,选择性地改变第二锁存数据DLT2(参照图17a的C3)。 Further, in S1320, the use of the read node NSEN obtained at step S1315 voltage level, selectively changing the second latch data DLT2 (refer FIG. 17a, C3). 因此,当第一比特数据BIT1为“1”且第二比特数据BIT2为“0”时,第二锁存数据DLT2触发至逻辑H状态。 Thus, when the first bit data BIT1 is "1" and the second bit data BIT2 is "0", the second latch data DLT2 to trigger the logic H state. 相反,在除第一比特数据BIT1为“1”且第二比特数据BIT2为“0”之外的其余情况下,第二锁存数据DLT2被维持在其先前状态上。 On the contrary, in addition to the first bit data BIT1 is "1" and the second bit data BIT2 is than "0" in the remaining cases, the second latch data DLT2 is maintained at its previous state.

另外,在S1325,传送控制信号TR被激活为逻辑H状态。 Further, in S1325, the transmission control signal TR is activated to a logic H state. 因此,在S1325,利用第二锁存数据DLT2,选择性地改变第一锁存数据DLT1(参照图17a的C4与C4′)。 Therefore, in S1325, using the second latch data DLT2, selectively changing the first latch data DLT1 (C4 with reference to Figure 17a, C4 '). 即,当第一比特数据BIT1为“1”且第二比特数据BIT2为“0”时,第一锁存数据DLT1被维持在其先前状态上。 That is, when the first bit data BIT1 is "1" and the second bit data BIT2 is "0", the first latch data DLT1 is maintained at its previous state.

相反,在其余情况下,第一锁存数据DLT1触发至逻辑H状态。 In contrast, in the remaining cases, the first latch data DLT1 trigger to a logic H state.

以下描述在进行了S1325之后,第一锁存数据DLT1与第二锁存数据DLT2的逻辑状态。 The following description After conducting S1325, the first latch data DLT1 and the second latch data of logic state DLT2.

即,当第三比特数据BIT3为“1”时,第一锁存数据DLT1与第二锁存数据DLT2为逻辑H,而不管第一比特数据BIT1与第二比特数据BIT2的值为何。 That is, when the third bit data BIT3 is "1", the first latch data DLT1 and the second latch data DLT2 is logic H, regardless of the value of the first bit data and second bit data BIT1 BIT2 why.

另外,当第一比特数据BIT1与第二比特数据BIT2为“0”且第三比特数据BIT3为“0”时,第一锁存数据DLT1为逻辑H,而第二锁存数据DLT2为逻辑L。 Further, when the first bit data and second bit data BIT1 BIT2 is "0" and the third bit data BIT3 is "0", the first latch data DLT1 is logic H, and the second latch data DLT2 is logic L .

另外,当第一比特数据BIT1为“1”且第二比特数据BIT2与第三比特数据BIT3为“0”时,第一锁存数据DLT1为逻辑L,而第二锁存数据DLT2为逻辑H。 Further, when the first bit data BIT1 is "1" and the second bit data BIT2 and third bit data BIT3 is "0", the first latch data DLT1 is logic L, and the second latch data DLT2 is logic H .

另外,当第一比特数据BIT1为“0”、第二比特数据BIT2为“1”、且第三比特数据BIT3为“0”时,第一锁存数据DLT1为逻辑H,而第二锁存数据DLT2为逻辑L。 Further, when the first bit data BIT1 is "0", the second bit data BIT2 is "1", and the third bit data BIT3 is "0", the first latch data DLT1 is logic H, and the second latch Data DLT2 logic L.

另外,当第一至第三比特数据BIT1至BIT3为“0”时,第一锁存数据DLT1为逻辑H,而第二锁存数据DLT2为逻辑L。 Further, when the BIT1 to BIT3 of the first through third bit data is "0", the first latch data DLT1 is logic H, and the second latch data DLT2 is logic L.

此后,在S1330,利用第一锁存数据DLT1与第二锁存数据DLT2,对第一存储器单元MC1与第二存储器单元MC2进行编程(参照图19b的C5)。 Thereafter, in S1330, the use of the first latch data DLT1 and the second latch data DLT2, on the first memory cell MC1 and the second memory cell MC2 is programmed (see FIG. 19b of C5). 当第三比特数据BIT3为“1”时,第一存储器单元MC1与第二存储器单元MC2的门限电压被维持在其先前状态上。 When the third bit data BIT3 is "1", the first memory cell MC1 and the second memory cell MC2 of the threshold voltage is maintained at its previous state.

相反,当第三比特数据BIT3为“0”时,则将第一存储器单元MC1或第二存储器单元MC2的门限电压调整到第二门限电压组G2。 On the contrary, when the third bit data BIT3 is "0", the first memory cell MC1 or the second memory cell MC2 is adjusted to the threshold voltage of the second threshold voltage group G2. 换言之,当第一比特数据BIT1为“1”且第二比特数据BIT2为“0”时,则将第一存储器单元MC1的门限电压调整到第二门限电压组G2。 In other words, when the first bit data BIT1 is "1" and the second bit data BIT2 is "0", the first memory cell MC1 is adjusted to the threshold voltage of the second threshold voltage group G2. 在其余情况下,将第二存储器单元MC2的门限电压调整到第二门限电压组G2。 In other cases, the second memory cell MC2 is adjusted to the threshold voltage of the second threshold voltage group G2.

因此,当作为第二页编程的结果、已经将第二存储器单元MC2的门限电压调整到第三门限电压组G3时,则在第三页编程时,响应于第三比特数据BIT3,将第一存储器单元MC1的门限电压调整到第二门限电压组G2。 Accordingly, when as a result of the second page programming, the second memory cell MC2 has a threshold voltage is adjusted to the third threshold voltage G3 group, at the time of the third page programming in response to the third bit data BIT3, the first the memory cell MC1 is adjusted to the threshold voltage of the second threshold voltage group G2. 相反,当作为第二页编程步骤的结果、已经将第二存储器单元MC2的门限电压维持在第一门限电压组G1上时,则在第三页编程时,响应于第三比特数据BIT3,将第二存储器单元MC2的门限电压调整到第二门限电压组G2。 On the contrary, when as a result of the second page programming step, the second memory cell MC2 has a threshold voltage is maintained at the first threshold voltage group G1, at the time of the third page programming in response to the third bit data BIT3, will second memory cell MC2 is adjusted to the threshold voltage of the second threshold voltage group G2.

接着,在S1335,根据第一参考电压VR1,将第一存储器单元MC1的门限电压反映在读出节点NSEN上(参照图17b的C6)。 Subsequently, in S1335, according to the first reference voltage VR1, the first memory cell MC1 is reflected on the threshold voltage read out node NSEN (refer FIG C6 17b of).

在步骤S1340,生成第一锁存控制信号LCH1,作为H脉冲。 In step S1340, generating a first latch control signal LCH1, as H pulse. 在这种情况下,根据读出节点NSEN的电压电平,第一锁存数据DLT1选择性地改变到逻辑H状态(参照图17b的C7)。 In this case, based on the read node NSEN voltage level, the first latch data DLT1 selectively changes to a logic H state (see Fig. 17b, C7).

另外,在S1345,根据第一参考电压VR1,将第二存储器单元MC2的门限电压反映在读出节点NSEN上(参照图17b的C8)。 Further, in S1345, according to the first reference voltage VR1, the second memory cell MC2 is reflected in the threshold voltage of the read node NSEN (refer to FIG. 17b, C8).

在S1350,生成第二锁存控制信号LCH2,作为H脉冲。 In S1350, the second latch control signal generating LCH2, as H pulse. 在这种情况下,根据读出节点NSEN的电压电平,第二锁存数据DLT2选择性地改变为逻辑H状态(参照图17b的C9)。 In this case, based on the read node NSEN voltage level, the second latch data DLT2 selectively changes to a logic H state (see Fig. 17b, C9).

在S1355,同时或依次生成第一数据线控制信号DIO1与第二数据线控制信号DIO2,作为H脉冲,从而读出第一锁存数据DLT1与第二锁存数据DLT2的逻辑状态(参照图17b的C10)。 In S1355, simultaneously or sequentially to generate a first data line control signal DIO1 and second data line control signal DIO2, as an H pulse, thereby reading out the first latch data DLT1 and the second latch data DLT2 is logic state (see Fig. 17b The C10). 在步骤S1360,验证编程是否成功。 In step S1360, verify that the programming is successful.

如果编程失败,则重复S1330及以下步骤。 If the program fails, the S1330 and repeat the following steps. 此时,在S1330,选定字线或比特线的电压电平逐步增加。 In this case, in S1330, the selected word line or the bit line voltage level gradually increased.

同时,当参照图10的S1140和S1150时,本领域技术人员可以明白图17b的S1335、S1340、S1345、以及S1350的读出节点NSEN电压电平以及第一锁存数据DLT1与第二锁存数据DLT2逻辑状态的变化,因此省略其详细描述。 Meanwhile, when referring to S1140 and S1150 of FIG. 10 when, skilled artisans will appreciate that FIG. 17b of S1335, S1340, S1345, and S1350 of the read node NSEN voltage level and the first latch data DLT1 and the second latch data Changes DLT2 logic state, and therefore a detailed description thereof is omitted.

图18为显示在根据实施例的非易失半导体存储器设备的编程方法中、在进行第三页编程步骤之后、第一存储器单元MC1与第二存储器单元MC2的门限电压变化的视图。 Figure 18 is a programming method in accordance with an embodiment of the nonvolatile semiconductor memory device, after performing the third page programming step, the first memory cell MC1 and the second memory cell MC2 of the threshold voltage variation of view.

当第一比特数据BIT1、第二比特数据BIT2、与第三比特数据BIT3都为“1”(情况31)时,第一存储器单元MC1与第二存储器单元MC2的门限电压都维持在擦除状态,即在第一门限电压组G1上。 When the first bit data BIT1, second bit data BIT2, and the third bit data BIT3 are "1" (case 31), a first memory cell MC1 and the second memory cell MC2 is maintained at the threshold voltage of the erased state , i.e., on the first threshold voltage group G1.

当第一比特数据BIT1与第二比特数据BIT2为“1”、且第三比特数据BIT3为“0”(情况32)时,第一存储器单元MC1的门限电压被维持在第一门限电压组G1上,第二存储器单元MC2的门限电压被调整到第二门限电压组G2。 When the first bit data and second bit data BIT1 BIT2 is "1", and the third bit data BIT3 is "0" (the case 32), the first memory cell MC1 of the threshold voltage is maintained at the first threshold voltage group G1 , the second memory cell MC2 is adjusted threshold voltage to a second threshold voltage group G2.

当第一比特数据BIT1为“1”、第二比特数据BIT2为“0”、且第三比特数据BIT3为“1”(情况33)时,第一存储器单元MC1的门限电压被维持在第一门限电压组G1上,第二存储器单元MC2的门限电压被维持在第三门限电压组G3上。 When the first bit data BIT1 is "1", the second bit data BIT2 is "0", and the third bit data BIT3 is "1" (the case 33), the first memory cell MC1 of the threshold voltage is maintained at the first threshold voltage group G1, the second memory cell MC2 of the threshold voltage is maintained at the third threshold voltage group G3.

当第一比特数据BIT1为“1”、第二比特数据BIT2为“0”、且第三比特数据BIT3为“0”(情况34)时,第一存储器单元MC1的门限电压被调整到第二门限电压组G2,第二存储器单元MC2的门限电压被维持在第三门限电压组G3上。 When the first bit data BIT1 is "1", the second bit data BIT2 is "0", and the third bit data BIT3 is "0" (case 34), the first memory cell MC1 is adjusted to the threshold voltage of the second threshold voltage group G2, the second memory cell MC2 of the threshold voltage is maintained at the third threshold voltage group G3.

当第一比特数据BIT1为“0”、第二比特数据BIT2为“1”、且第三比特数据BIT3为“1”(情况35)时,第一存储器单元MC1的门限电压被维持在第二门限电压组G2上,第二存储器单元MC2的门限电压被维持在第一门限电压组G1上。 When the first bit data BIT1 is "0", the second bit data BIT2 is "1", and the third bit data BIT3 is "1" (case 35), the first memory cell MC1 is maintained at the threshold voltage of the second threshold voltage group G2, the second memory cell MC2 of the threshold voltage is maintained at the first threshold voltage group G1.

当第一比特数据BIT1为“0”、第二比特数据BIT2为“1”、且第三比特数据BIT3为“0”(情况36)时,第一存储器单元MC1的门限电压被维持在第二门限电压组G2上,第二存储器单元MC2的门限电压被调整到第二门限电压组G2。 When the first bit data BIT1 is "0", the second bit data BIT2 is "1", and the third bit data BIT3 is "0" (case 36), the first memory cell MC1 is maintained at the threshold voltage of the second threshold voltage group G2, the second memory cell MC2 is adjusted to the threshold voltage of the second threshold voltage group G2.

当第一比特数据BIT1为“0”、第二比特数据BIT2为“0”、且第三比特数据BIT3为“1”(情况37)时,第一存储器单元MC1的门限电压被维持在第三门限电压组G3上,第二存储器单元MC2的门限电压被维持在第一门限电压组G1上。 When the first bit data BIT1 is "0", the second bit data BIT2 is "0", and the third bit data BIT3 is "1" (case 37), the first memory cell MC1 is maintained at the threshold voltage of the third threshold voltage group G3, the second memory cell MC2 of the threshold voltage is maintained at the first threshold voltage group G1.

当第一比特数据BIT1、第二比特数据BIT2、与第三比特数据BIT3都为“0”(情况38)时,第一存储器单元MC1的门限电压被维持在第三门限电压组G3上,第二存储器单元MC2的门限电压被调整到第二门限电压组G2。 When the first bit data BIT1, second bit data BIT2, and the third bit data BIT3 are "0" (case 38), the first memory cell MC1 of the threshold voltage is maintained at the third threshold voltage group G3, and The second memory cell MC2 is adjusted to the threshold voltage of the second threshold voltage group G2.

由此,在实施例的三级非易失半导体存储器设备的驱动方法中,可以根据三个依次提供的比特数据BIT1、BIT2、BIT3,同时控制第一存储器单元MC1与第二存储器单元MC2的门限电压。 Accordingly, in the driving method of the three non-volatile semiconductor memory device of the embodiment, according to the three-bit data BIT1 sequentially provided, BIT2, BIT3, while controlling the first memory cell MC1 and the second memory cell MC2 threshold Voltage. 另外,可以通过对于每个比特数据值的仅仅一或两次读取操作,验证编程是否成功。 In addition, for each bit of data values by only one or two read operations to verify the program is successful.

因此,根据实施例的三级非易失半导体存储器设备的编程方法,总体操作速度非常高。 Thus, according to the programming method of the nonvolatile semiconductor memory device of the third embodiment, the overall operating speed is very high.

此后,描述非易失半导体存储器设备的读取方法的实施例。 Thereafter, Example reading method of the nonvolatile semiconductor memory device is described. 在该例子中,即使可以随机地分别执行读取第一到第三比特数据BIT1到BIT3的第一到第三页读取步骤,进行存储器单元对的读取也没有问题。 In this example, even if it can be performed randomly reading the first to third, respectively, the first bit data BIT1 to BIT3 to the third page of a reading step of reading a memory cell is not a problem.

图19为显示在根据实施例的非易失半导体存储器设备的读取方法中、第一页读取的流程图。 Figure 19 is a reading method in the embodiment of the nonvolatile semiconductor memory device, according to the first page of a flowchart read. 图20a与20b为基于图19流程图的数据流图。 Figures 20a and 20b Figure 19 is a flowchart based on the data flow diagram. 在第一页读取时,验证第一门限电压组G1的第一存储器单元MC1与第三门限电压组G3的第二存储器单元MC2,从而读取第一比特数据BIT1。 When reading the first page, the first verify threshold voltage group G1 of the first memory cell MC1 and the third threshold voltage group G3 of the second memory cell MC2, thereby reading the first bit data BIT1.

参照图19,在S1410,第一锁存数据DLT1与第二锁存数据DLT2被设置为逻辑L状态(参照图20a的D1)。 Referring to Figure 19, at S1410, the first latch data DLT1 and the second latch data DLT2 are set to a logic L state (see Fig. D1 20a of).

另外,在S1420与S1430,利用依赖于基于第一参考电压VR1验证的第一存储器单元MC1门限电压的数据,进行控制第二锁存数据DLT2的数据获取(fetching)。 Further, in S1420 and S1430, in dependence on the verification based on a first reference voltage VR1 of the first memory cell MC1 threshold voltage data, controlling the second latch data DLT2 data acquisition (fetching).

详细地,在S1420,根据第一参考电压VR1,第一存储器单元MC1的门限电压被反映到读出节点NSEN上(参照图20a的D2)。 In detail, at S1420, in accordance with a first reference voltage VR1, the first memory cell MC1 is reflected in the threshold voltage read out to the node NSEN (refer Figure 20a is D2). 在S1430,生成第二锁存控制信号LCH2,作为H脉冲。 In S1430, the second latch control signal generating LCH2, as H pulse. 此时,根据读出节点NSEN的电压电平,第二锁存数据DLT2选择性地改变到逻辑H状态(参照图20a的D3)。 At this time, based on the read node NSEN voltage level, the second latch data DLT2 selectively changes to a logic H state (see Fig. 20a, D3).

另外,在S1440,传送控制信号TR被激活为逻辑H状态。 Further, in S1440, the transmission control signal TR is activated to a logic H state. 因此,在S1440,由S1430处的第二锁存数据DLT2选择性地控制第一锁存数据DLT1(参照图20a的D4与D4′)。 Therefore, in S1440, the second latch data DLT2 at S1430 selectively controlling the first latch data DLT1 (D4 with reference to Figure 20a, D4 ').

描述在执行步骤S1440之后的第一锁存数据DLT1的逻辑状态。 Description of the first latch data in step S1440 after performing the logic state DLT1. 即,当第一存储器单元MC1的门限电压属于第一门限电压组G1(图20的情况31、情况32、与情况33)时,将第一锁存数据DLT1从逻辑L状态调整到逻辑H状态。 That is, when the first memory cell MC1 belongs to the threshold voltage of the first threshold voltage group G1 (Fig. 20 31, the case 32, the case 33), the first latch data DLT1 from a logic L state to adjust to a logic H state . 相反,当第一存储器单元MC1的门限电压属于第二门限电压组G2或第三门限电压组G 3(图18的情况34至情况38)时,将第一锁存数据DLT1维持在逻辑L状态上。 In contrast, when the first memory cell MC1 belongs to the second threshold voltage threshold voltage group G2 or the third threshold voltage group G 3 (case of Fig. 34 to 18 of 38 cases), the first latch data DLT1 is maintained at a logic L state on.

另外,在S1450与S1460,利用依赖于基于第二参考电压VR2验证的第二存储器单元MC2的门限电压的数据,选择性地改变第一锁存数据DLT1。 Further, in S1450 and S1460, in dependence on the second memory cell based on a second reference voltage VR2 verified MC2 threshold voltage of the data, selectively changing the first latch data DLT1.

详细地,在S1450,根据第二参考电压VR2,第二存储器单元MC2的门限电压被反映到读出节点NSEN上(参照图20b的D5)。 In detail, at S1450, according to the second reference voltage VR2, the second memory cell MC2 is reflected in the threshold voltage on the sense node NSEN (refer Fig. 20b of D5). 在步骤S1460,生成第一锁存控制信号LCH1,作为H脉冲。 In step S1460, the first latch control signal is generated LCH1, as an H pulse. 在这种情况下,根据读出节点NSEN的电压电平,第一锁存数据DLT1选择性地改变到逻辑H状态(参照图20b的D6)。 In this case, based on the read node NSEN voltage level, the first latch data DLT1 selectively changes to a logic H state (see Fig. 20b, D6).

下面描述S1460处第一锁存数据DLT1的逻辑状态的变化。 Changes DLT1 logic state of the first latch data of S1460 described below. 即,当第二存储器单元MC2的门限电压属于第三门限电压组G3(图18的情况33与情况34)时,将第一锁存数据DLT1从逻辑L状态调整到逻辑H状态。 That is, when the second memory cell MC2 belongs to the third threshold voltage threshold voltage group G3 (the case 33 and the case of FIG. 18 34), the first latch data DLT1 from a logic L state to adjust a logic H state. 相反,在其余情况下,将第一锁存数据DLT1维持在其先前状态上。 In contrast, in the remaining cases, the first latch data DLT1 is maintained at its previous state.

因此,下面描述执行S1440与S1460之后的第一锁存数据DLT1的逻辑状态的变化。 Accordingly, the following describes changes in the logic state of the first latch data DLT1 execute S1440 and S1460 later. 当第一存储器单元MC1的门限电压属于第一门限电压组G1时、或者当第二存储器单元MC2的门限电压属于第三门限电压组G3(图18的情况31到情况34)时,即,当第一比特数据BIT1为“1”时,将第一锁存数据DLT1调整到逻辑H状态。 When the first memory cell MC1 belongs to the first threshold voltage threshold voltage group G1, or when the second memory cell MC2 gate threshold voltage belongs to the third threshold voltage group G3 (the case of FIG. 18 to the case 34 of 31), i.e., when the The first bit data BIT1 is "1", the first latch data DLT1 is adjusted to a logic H state. 相反,在其余情况下(图18的情况35到情况38),即,当第一比特数据BIT1为“0”时,将第一锁存数据DLT1维持在逻辑L状态上。 On the contrary, (case of Fig. 18 to 35 of the case 38), i.e., when the first bit data BIT1 is "0", the first latch data DLT1 is maintained at a logic L state in the remaining cases.

在S1470,执行数据验证步骤,即生成第一数据线控制信号DI01作为H脉冲,读出第一锁存数据DLT1的逻辑状态,并且验证第一比特数据BIT1(参照图20b的D7)。 In S1470, perform data validation step, which generates the first data line control signal DI01 as H pulse, reading out the logic state of the first latch data DLT1, and the first bit of data validation BIT1 (reference Figure 20b, D7).

在该实施例中,具有逻辑H状态的输出数据指示第一比特数据BIT1为“1”,而具有逻辑L状态的输出数据指示第一比特数据BIT1为“0”。 In this embodiment, the output data having a logic H state indicates that the first bit data BIT1 is "1", and the output data having a logic L state indicates that the first bit data BIT1 is "0."

由此,可以通过单个的读取操作读取第一比特数据BIT1。 This makes it possible to read the first bit data BIT1 through a single read operation.

图21为显示在根据实施例的非易失半导体存储器设备的读取方法中、第二页读取的流程图。 Figure 21 is displayed in the read method according to an embodiment of the nonvolatile semiconductor memory device, the second page of the flowchart is read. 图22a与22b为基于图21流程图的数据流图。 Figures 22a and 22b Figure 21 is a flowchart based on the data flow diagram. 在第二页读取时,验证第三门限电压组G3的第一存储器单元MC1或第二存储器单元MC2,从而读取第二比特数据BIT2。 In the second page read, verify third threshold voltage group G3 of the first memory cell MC1 or the second memory cell MC2, thereby reading the second bit data BIT2.

参照图21,在S1510,第一锁存数据DLT1与第二锁存数据DLT2被设置为逻辑L状态(参照图22a的E1)。 Referring to Figure 21, at S1510, the first latch data DLT1 and the second latch data DLT2 are set to a logic L state (see Fig E1 22a of).

另外,在S1520与S1530,利用依赖于基于第二参考电压VR2验证的第二存储器单元MC2的门限电压的数据,控制第二锁存数据DLT2。 Further, in S1520 and S1530, in dependence on the second memory cell based on a second reference voltage VR2 verified MC2 threshold voltage of the data, controlling the second latch data DLT2.

详细地,在S1520,根据第二参考电压VR2,第二存储器单元MC2的门限电压被反映到读出节点NSEN上(参照图22a的E2)。 In detail, at S1520, according to the second reference voltage VR2, the second memory cell MC2 is reflected in the threshold voltage on the sense node NSEN (refer FIG. 22a, E2). 在S1530,生成第二锁存控制信号LCH2,作为H脉冲。 In S1530, the second latch control signal generating LCH2, as H pulse. 在这种情况下,根据读出节点NSEN的电压电平,第二锁存数据DLT2选择性地改变到逻辑H状态(参照图22a的E3)。 In this case, based on the read node NSEN voltage level, the second latch data DLT2 selectively changes to a logic H state (see Fig. 22a, E3).

下面描述在执行S1530之后的第二锁存数据DLT2的逻辑状态。 Next, a second latch data S1530 after performing the logic state DLT2. 即,当第二存储器单元MC2的门限电压属于第三门限电压组G3(图18的情况33与情况34)时,将第二锁存数据DLT2从逻辑L状态调整到逻辑H状态。 That is, when the second memory cell MC2 belongs to the third threshold voltage threshold voltage group G3 (the case 33 and the case of FIG. 18 34), the second latch data DLT2 to adjust from a logic L state to a logic H state. 相反,在其余情况下(图18的情况31、情况32、以及情况35至情况38),将第二锁存数据DLT2维持在逻辑L状态上。 On the contrary, (the case 31 of FIG. 18, the case 32, and the case 35 to the case 38), the second latch data DLT2 is maintained at a logic L state in the remaining cases.

另外,在S1540与S1550,利用依赖于基于第二参考电压VR2验证的第一存储器单元MC1的门限电压的数据,控制第二锁存数据DLT2。 Further, in S1540 and S1550, in dependence on the first memory cell MC1 based on the second reference voltage VR2 verify threshold voltage of the data, controlling the second latch data DLT2.

详细地,在S1540,根据第二参考电压VR2,第一存储器单元MC1的门限电压被反映到读出节点NSEN上(参照图22b的E4)。 In detail, at S1540, according to the second reference voltage VR2, the first memory cell MC1 is reflected in the threshold voltage read out to the node NSEN (refer Fig. 22b, E4). 在S1550,生成第二锁存控制信号LCH2,作为H脉冲。 In S1550, second latch control signal is generated LCH2, as H pulses. 在这种情况下,根据读出节点NSEN的电压电平,第二锁存数据DLT2选择性地改变到逻辑H状态(参照图22b的E5)。 In this case, based on the read node NSEN voltage level, the second latch data DLT2 selectively changes to a logic H state (see Fig. 22b, E5).

下面描述在执行S1550之后的第二锁存数据DLT2的逻辑状态。 Next, a second latch data after performing logic state DLT2 of S1550. 即,当第一存储器单元MC1的门限电压属于第三门限电压组G3(图18的情况37与情况38)时,将第二锁存数据DLT2调整到逻辑H状态。 That is, when the first memory cell MC1 belongs to the third threshold voltage threshold voltage group G3 (the case 37 and the case of FIG. 18 38), the second latch data DLT2 is adjusted to a logic H state. 相反,在其余情况下(图18的情况31至情况36),将第二锁存数据DLT2维持在其先前逻辑状态上。 In contrast, in the remaining case (case of Fig. 31 to 18 of the case 36), the second latch data DLT2 is maintained at its previous logic state.

另外,在S1560,激活传送控制信号TR到逻辑H状态。 Further, in S1560, the transmission control signal TR is activated to a logic H state. 因此,在S1560,利用S1530与S1550处的第二锁存数据DLT2,控制在步骤S1550设置的第一锁存数据DLT1(参照图22b的E6和E6′)。 Therefore, in S1560, S1530 and using the second latch data at S1550 DLT2, controlling the first latch data DLT1 S1550 set at step (see Fig. 22b E6 and E6 ').

以下描述执行S1560之后的第一锁存数据DLT1的逻辑状态。 The following description of the first logic state of the latch data DLT1 after S1560 is executed. 即,当第一存储器单元MC1或者第二存储器单元MC2的门限电压属于第三门限电压组G3(图18的情况33、情况34、情况37与情况38)时,将第一锁存数据DLT1从逻辑L状态调整到逻辑H状态。 That is, when the first memory cell MC1 or the second memory cell MC2 belongs to the third threshold voltage threshold voltage group G3 (the case 33 in FIG. 18, the case 34, the case 37 and the case 38), the first latch data DLT1 from logic L state to adjust to the logic H state. 相反,在其余情况下(图18的情况31、情况32、情况35与情况36),将第一锁存数据DLT1维持在逻辑L状态上。 In contrast, in the remaining cases (Fig. 18 case 31, the case 32, the case 35 and the case 36), the first latch data DLT1 is maintained at a logic L state.

在S1570,生成第一数据线控制信号DIO1作为H脉冲,读出第一锁存数据DLT1的逻辑状态,并且验证第二比特数据BIT2(参照图22b的E7)。 In S1570, generating a first data line control signal DIO1 as an H pulse, reading out the logic state of the first latch data DLT1, and verify the second bit data BIT2 (with reference to FIG. 22b, E7). 在该实施例中,具有逻辑H状态的输出数据指示第二比特数据BIT2为“1”,而具有逻辑L状态的输出数据指示第二比特数据BIT2为“0”。 In this embodiment, the output data having a logic H state indicates that the second bit data BIT2 is "1", and the output data having a logic L state indicates that the second bit data BIT2 is "0."

如上所述,根据该实施例的非易失半导体存储器设备的驱动方法,可以通过单个读取操作读取第二比特数据BIT2的值。 As described above, according to the driving method of the nonvolatile semiconductor memory device according to this embodiment, the value of the second bit data BIT2 may be read through a single read operation.

图23a与23b为显示在根据实施例的非易失半导体存储器设备的读取方法中、第三页读取的流程图。 Figures 23a and 23b is displayed in the reading method of an embodiment of the nonvolatile semiconductor memory device, the page is read according to the third flowchart. 图24a与24b为基于图23a与23b流程图的数据流图。 Figures 24a and 24b Figures 23a and 23b based on the flowchart of the data flow diagram. 在第三页读取步骤,验证第一门限电压组G1或第三门限电压组G 3的第二存储器单元MC2,排除第二门限电压组G2的第一存储器单元MC1,从而读取第三比特数据BIT3。 In the third page reading step, a first verify threshold voltage group G1 or the third threshold voltage group G 3 of the second memory cell MC2, exclude the first memory cell MC1 second threshold voltage group G2, thereby reading the third bit Data BIT3.

参照图23a与23b,在步骤S1610,将第一锁存数据DLT1与第二锁存数据DLT2设置为逻辑L状态(参照图24a的F1)。 Referring to Figures 23a and 23b, in step S1610, the first latch data DLT1 and the second latch data DLT2 is set to a logic L state (see Fig F1 24a of).

另外,在S1620与S1630,利用依赖于基于第一参考电压VR1验证的第二存储器单元MC2的门限电压的数据,控制第二锁存数据DLT2。 Further, in S1620 and S1630, in dependence on the second memory cell based on a first reference voltage VR1 verified MC2 threshold voltage of the data, controlling the second latch data DLT2.

详细地,在S1620,根据第一参考电压VR1,第二存储器单元MC2的门限电压被反映到读出节点NSEN上(参照图24a的F2)。 In detail, at S1620, in accordance with a first reference voltage VR1, the second memory cell MC2 is reflected in the threshold voltage on the sense node NSEN (refer FIG. 24a, F2). 在步骤S1630,生成第二锁存控制信号LCH2,作为H脉冲。 In step S1630, the second latch control signal generating LCH2, as an H pulse. 此时,根据读出节点NSEN的电压电平,第二锁存数据DLT2选择性地改变到逻辑H状态(参照图24a的F3)。 At this time, based on the read node NSEN voltage level, the second latch data DLT2 selectively changes to a logic H state (see Fig. 24a, F3).

另外,在S1640,将传送控制信号TR激活到逻辑H状态。 Further, in S1640, the transfer control signal TR activated to a logic H state. 因此,在S1640,利用在S1630获得的第二锁存数据DLT2,控制在步骤S1610设置的第一锁存数据DLT1。 Therefore, in S1640, using the second latch data obtained in S1630 DLT2, control set at step S1610 a first latch data DLT1.

下面描述在执行步骤S1640之后的第一锁存数据DLT1的逻辑状态。 The following description of the first latch data in step S1640 after performing the logic state DLT1. 即,当第二存储器单元MC2的门限电压属于第一门限电压组G1(图18的情况31、情况35、与情况37)时,将第一锁存数据DLT1从逻辑L状态调整到逻辑H状态。 That is, when the second memory cell MC2 belongs to the threshold voltage of the first threshold voltage group G1 (Fig. 18 case 31, the case 35, the case 37), the first latch data DLT1 from a logic L state to adjust to a logic H state . 相反,当第一存储器单元MC1的门限电压属于第二或第三门限电压组G2或G3(图18的情况32、情况33、情况34、情况36、以及情况38)时,将第一锁存数据DLT1维持在逻辑L状态上。 In contrast, when the first memory cell MC1 belongs to the threshold voltage of the second or third threshold voltage group G2 or G3 (the case 32 of FIG. 18, the case 33, the case 34, the case 36 and the case 38), the first latch DLT1 maintain data on the logical L state.

另外,在S1650与S1660,利用依赖于基于第二参考电压VR2验证的第二存储器单元MC2的门限电压的数据,选择性地改变第一锁存数据DLT1。 Further, in S1650 and S1660, in dependence on the second memory cell based on a second reference voltage VR2 verified MC2 threshold voltage of the data, selectively changing the first latch data DLT1.

详细地,在S1650,根据第二参考电压VR2,第二存储器单元MC2的门限电压被反映到读出节点NSEN上(参照图24b的F5)。 In detail, at S1650, according to the second reference voltage VR2, the second memory cell MC2 is reflected in the threshold voltage on the sense node NSEN (refer Fig. 24b, F5). 在S1660,生成第一锁存控制信号LCH1,作为H脉冲。 In the S1660, the first latch control signal is generated LCH1, as H pulses. 在这种情况下,根据读出节点NSEN的电压电平,第一锁存数据DLT1选择性地改变到逻辑H状态(参照图24b的F6)。 In this case, based on the read node NSEN voltage level, the first latch data DLT1 selectively changes to a logic H state (see Fig. 24b, F6).

下面描述S1660处的第一锁存数据DLT1的逻辑状态的变化。 DLT1 changes logic state at the first latch data S1660 described below. 当第二存储器单元MC2的门限电压属于第三门限电压组G3(图18的情况33与情况34)时,将第一锁存数据DLT1从逻辑L状态调整到逻辑H状态。 When the second memory cell MC2 belongs to the third threshold voltage threshold voltage group G3 (the case 33 and the case of FIG. 18 34), the first latch data DLT1 from a logic L state to adjust a logic H state. 相反,在其余情况下,将第一锁存数据DLT1维持在其先前逻辑状态上。 In contrast, in the remaining cases, the first latch data DLT1 is maintained at its previous logic state.

以下描述这种情况下执行S1640与S1660之后的第一锁存数据DLT1的逻辑状态的变化。 The following describes variation of the first latch data execution S1640 and S1660 after the logic state of this case DLT1. 当第二存储器单元MC2的门限电压属于第一门限电压组G1或者第三门限电压组G3(图18的情况31、情况35、情况37、情况33与情况34)时,将第一锁存数据DLT1从逻辑L状态调整到逻辑H状态。 When the second memory cell MC2 belongs to the threshold voltage of the first threshold voltage group G1 or the third threshold voltage group G3 (Fig. 18 case 31, the case 35, the case 37, the case 33 and the case 34), the first latch data DLT1 adjustment from logic L state to a logic H state. 相反,在其余情况下(图18的情况32、情况36与情况38),将第一锁存数据DLT1维持在逻辑L状态上。 On the contrary, (the case 32 of FIG. 18, the case 36 and the case 38), the first latch data DLT1 is maintained at a logic L state in the remaining cases.

另外,在S1670与S1680,利用依赖于基于第一参考电压VR1验证的第一存储器单元MC1的门限电压的数据,选择性地改变第一锁存数据DLT1。 Further, in S1670 and S1680, in dependence on the verification based on a first reference voltage VR1 of the first memory cell MC1 of the threshold voltage of the data, selectively changing the first latch data DLT1. 在这种情况下,响应于在S1630触发的第二锁存数据DLT2,使能对第一锁存数据DLT1的翻转触发。 In this case, the second latch data in response to S1630 trigger DLT2, enable the first latch data DLT1 flip trigger.

详细地,在S1670,根据第一参考电压VR1,第一存储器单元MC1的门限电压被反映到读出节点NSEN上(参照图24b的F7)。 In detail, at S1670, in accordance with a first reference voltage VR1, the first memory cell MC1 is reflected in the threshold voltage read out to the node NSEN (refer Fig. 24b, F7). 在S1680,生成翻转锁存信号IVLCH,作为H脉冲。 In S1680, flip the latch signal is generated IVLCH, as H pulses. 在这种情况下,根据读出节点NSEN的电压电平以及第二锁存数据DLT2,第一锁存数据DLT1选择性地改变到逻辑L状态(参照图24b的F8与F8′)。 In this case, according to the read voltage level of node NSEN and the second latch data DLT2, the first latch data DLT1 selectively changes to a logic L state (see Fig. 24b of F8 and F8 ').

换言之,根据读出节点NSEN的电压电平,第一锁存数据DLT1选择性地从逻辑H状态翻转触发到逻辑L状态。 In other words, according to the readout node NSEN voltage level, the first latch data DLT1 selectively trigger flip state from logic H to logic L state. 此时,只有当第二锁存数据DLT2处于逻辑H状态时,才能进行对第一锁存数据DLT1的翻转触发。 At this time, only when the second latch data DLT2 in logic H state to carry out the first latch data DLT1 trigger the flip.

因此,只有当第一存储器单元MC1的门限电压属于第二门限电压组G2、且第二存储器单元MC2的门限电压属于第三门限电压组G3时(图18的情况34),才发生第一锁存数据DLT1从逻辑H状态到逻辑L状态的翻转触发。 Therefore, only when the first memory cell MC1 belongs to the threshold voltage of the second threshold voltage group G2, and the second memory cell MC2 belongs to the third threshold voltage group G3 when the threshold voltage (in the case of FIG. 18 34), before the occurrence of the first lock stored data DLT1 flipped from a logic H state to trigger logic L state.

以下描述执行步骤S1680之后的第一锁存数据DLT1的逻辑状态。 The following describes the steps of the first latch data DLT1 after S1680 logic state. 在图18的情况31、情况33、情况35、与情况37的情况下,第一锁存数据DLT1的逻辑状态为逻辑H。 In the case of 31 of FIG. 18, the case 33, the case 35, the case 37 of the case, the first latch data DLT1 is logic H. The logic state 另外,图18的情况32、情况34、情况36、与情况38的情况下,第一锁存数据DLT1的逻辑状态为逻辑L。 Further, the case 32 of FIG. 18, the case 34, the case 36, the case 38 of the case, the logic state of the first latch data DLT1 is logic L.

在S1690,生成第一数据线控制信号DIO1作为H脉冲,读出第一锁存数据DLT1的逻辑状态,并且验证第三比特数据BIT3(参照图24b的F9)。 In S1690, generating a first data line control signal DIO1 as an H pulse, reading out the logic state of the first latch data DLT1, and verify the third bit data BIT3 (with reference to FIG. 24b, F9).

如上所述,根据该实施例的非易失半导体存储器设备的驱动方法,可以通过单个读取操作读取第三比特数据BIT3。 As described above, according to the driving method of the nonvolatile semiconductor memory device according to this embodiment, the third bit of data can be read through a single read operation BIT3.

总之,根据该实施例的非易失半导体存储器设备的读取方法,可以在不用读取其他两个比特的情况下,读取第一到第三比特数据BIT1到BIT3中的每一个。 In short, according to the nonvolatile semiconductor memory device reading method of this embodiment, can not be read in the other two bits, read the first to third bit data BIT1 to BIT3 each. 因此,总体操作速度非常高。 Thus, the overall operating speed is very high.

以下接着描述由根据实施例的非易失半导体存储器设备执行的页解码方法。 The following will be described next page by the decoding method according to the nonvolatile semiconductor memory device to perform the embodiments.

图25为显示由根据实施例的非易失半导体存储器设备执行的页解码方法的图示。 25 is displayed by a non-volatile semiconductor memory device according to an embodiment of the execution of the page decoding method shown. 在图25的实施例中,第一串ST1与第二串ST2中的每一个都包括22个存储器单元。 In the embodiment of Figure 25, the first string ST1 and the second string ST2, each of which includes 22 memory cells. 在第一串ST1与第二串ST2中的每一个中包含的22个存储器单元中,20个存储器单元为可以按三级编程的存储器单元MC1b或MC2b,而剩余的两个存储器单元为可以按两级编程的存储器单元MC1a或MC2a。 22 memory cells in each of the first string ST1 and the second string ST2, contained in, 20 memory cells can be three programmed memory cells MC1b or MC2b, while the remaining two memory cells can be two programmed memory cells MC1a or MC2a. 为了描述方便,将可以按三级编程的存储器单元MC1b或MC2b称为“三级存储器单元”,将可以按两级编程的存储器单元MC1a或MC2a称为“两级存储器单元”。 For convenience of description, will be able to press the three programmed memory cells MC1b or MC2b called "three memory cells", will be able to press the two programmed memory cells MC1a or MC2a called "two memory cells."

首先,描述选择形成对的两个三级存储器单元MC1b和MC2b的方法。 First, the choice of the formation of two and three memory cells MC1b MC2b approach. 根据实施例,形成对的两个三级存储器单元MC1b和MC2b分别排列在第一串ST1与第二串ST2中,如图25所示。 According to two levels of memory cells MC1b and MC2b respectively arranged in the first string ST1 and the second string ST2, as shown in the illustrated embodiment, the formation 25. 在这种情况下,公知的是:利用排列在相同串中的、形成对的两个三级存储器单元MC1b与MC2b,在数据读取操作中可以获得益处。 In this case, it is known that: the use of the same string are arranged in the form of two three-level memory cells MC1b and MC2b, in the data read operation can benefit.

向第一串ST1与第二串ST2的存储器单元分配页地址。 The first string ST1 and ST2 of the memory cells of the second string assignment page address. 术语“页地址”指用来指定每个页的一系列号码。 The term "page address" means to specify a range of numbers for each page. 另外,在单个页间隔期间,可以从或向指定列中的存储器单元输入或输出一比特数据。 In addition, during the interval of a single page, you can specify the column from or to a memory unit input or output of a bit of data.

再次参照图25,以下描述向第一串ST1与第二串ST2的存储器单元分配页的方法。 Referring again to FIG. 25, the following description of the first string and second string ST2 ST1 memory unit allocation method page. 向每个两级存储器单元MC1a与MC2a分配单个页。 To each of the two memory unit MC1a and MC2a assign a single page. 因此,一比特数据被映射到每个两级存储器单元MC1a与MC2a。 Thus, one-bit data are mapped to each two memory cell MC1a and MC2a. 在图25的实施例中,页地址PAGE1、PAGE2、PAGE63、与PAGE64被分配给两级存储器单元MC1a与MC2a。 In the embodiment of Figure 25, the page address PAGE1, PAGE2, PAGE63, and PAGE64 is allocated to the memory unit MC1a levels and MC2a.

同时,在三级存储器单元MC1b与MC2b的情况下,向形成对的两个三级存储器单元MC1b或MC2b分配三个页。 Meanwhile, in the case where three memory cells MC1b and MC2b, and to the formation of two or three memory cells MC1b MC2b assigned three pages. 因此,实际向每个三级存储器单元MC1b与MC2b分配1.5个页。 Accordingly, the actual allocation to each 1.5 p tertiary storage unit MC1b and MC2b.

在图25所示的实施例中,向第一串ST1与第二串ST2分配60个页,每个使用20对三级存储器单元MC1b与MC2b,从而向每个串分配30个页。 In the embodiment shown in FIG. 25, the first string ST1 and the second string ST2 allocated 60 pages, each using 20 pairs of the three memory cells MC1b and MC2b, to dispense 30 pages to each string. 另外,向第一串ST1与第二串ST2分配4个页,每个使用两个两级存储器单元MC1a或MC2a,从而向每个串分配两个页。 In addition to the first string ST1 and ST2 second string allocated four pages, each with two levels of memory cells MC1a or MC2a, so as to allocate two pages to each string. 总共向总数为44的存储器单元分配了64个页。 The total number of memory cells to a total of 44 allocated 64 pages.

优选地,分配给对应成对三级存储器单元MC1b与MC2b的页地址具有顺序关系,如图25所示。 Preferably, three pairs assigned to the corresponding memory cell MC1b and MC2b page address having an order relationship, as shown in Fig.25. 由此,当非易失半导体存储器设备利用顺序页地址进行编程操作时,可以提高可靠性。 Thus, when the nonvolatile semiconductor memory device utilizing sequential page address programming operation, reliability can be improved.

再次参照图25,描述排列两级与三级存储器单元的方法。 Referring again to FIG. 25, describes a method and arrangement of the three levels of memory cells. 图25的每个串ST1与ST2通过地选择晶体管TR1g与TR2g分别耦合到共同来源线CSL。 FIG each string ST1 25 and through ground selection transistor ST2 and TR2g TR1g are coupled to a common source line CSL. 串ST1与ST2通过相应的串选择晶体管TR1s与TR2s分别耦合到第一与第二比特线BL1与BL2。 String ST1 and ST2 through the corresponding string selection transistor TR1s and TR2s respectively coupled to first and second bit lines BL1 and BL2. 另外,两级存储器单元MC1a和三级存储器单元MC1b被排列在串选择晶体管TR1s与地选择晶体管TR1g之间。 In addition, two memory unit MC1a and three memory cells are arranged in a string selection MC1b TR1s and choose between transistor transistor TR1g. 两级存储器单元MC2a以及三级存储器单元MC2b被排列在串选择晶体管TR2s与地选择晶体管TR2g之间。 Two memory unit MC2a and tertiary storage unit MC2b are arranged in a string selection transistor TR2s and choose between transistors TR2g.

根据实施例,在串ST1与ST2中,排列两级存储器单元MC1a与MC2a,以邻近相应的地选择晶体管TR1g与TR2g,并且邻近相应的串选择晶体管TR1s与TR2s。 According to an embodiment, the string ST1 and ST2, the arrangement of two memory cells MC1a and MC2a, corresponding to adjacent ground selection transistor TR1g and TR2g, and adjacent to the corresponding string selection transistor TR1s and TR2s. 即,在操作期间,供以比三级存储器单元MC1b与MC2b低的电压的两级存储器单元MC1a与MC2a被排列得邻近地选择晶体管TR1g与TR2g、以及串选择晶体管TR1s与TR2s。 That is, during operation, in order for the memory cell is lower than three and MC2b MC1b voltage level memory cells are arranged to give MC1a and MC2a adjacent ground selection transistor TR1g and TR2g, and the string selection transistor TR1s and TR2s. 由此,使由地选择晶体管TR1g与TR2g、以及串选择晶体管TR1s与TR2s的泄露电流而导致的可靠性下降最小化。 Thus, the reliability of the transistor by selecting TR1g and TR2g, and the string selection transistor leakage current TR2s TR1s and resulting decline minimized.

根据该实施例的非易失半导体存储器设备根据行地址XADD来确定待操作的页类型,并且根据对页类型的确定,进行编程或读取操作。 To determine the type of page to be operated according to the row address XADD according to the embodiment of the nonvolatile semiconductor memory device, and based on the determination of the page type, for programming or reading operation. 例如,如果行地址XADD指示要选择PAGE63,则页类型为两级存储器单元。 For example, if the row address XADD instructed to select PAGE63, the page type for two memory cells. 类似地,如果行地址XADD指示要选择PAGE62,则页类型为三级存储器单元。 Similarly, if the row address XADD instructed to select PAGE62, the page for the three types of memory cells. 相应地,使用对于该页类型的适当的编程或读取操作。 Accordingly, the use of appropriate programming for the type or page read operation.

图26为显示由非易失半导体存储器设备执行的编程操作的实施例的流程图。 Figure 26 is a flowchart showing an embodiment of a nonvolatile semiconductor memory device to perform the programming operation. 在S2110,输入用于命令编程操作的操作命令CMD。 In the S2110, the input for command programming operation command CMD. 另外,在S2120,输入待编程的行地址XADD与数据。 Further, in S2120, the input row address XADD to be programmed with the data. 在S2130,确定输入行地址XADD是否为对应于具有三级存储器单元的页的三级地址。 In S2130, determines whether the input row address XADD is having a page address corresponding to the three levels of memory cells. 如果确定输入行地址XADD不为三级地址,则在S2140执行典型的两级编程操作。 If it is determined not to enter the third row address XADD address, perform a typical two-stage programming operation in S2140. 如果确定输入行地址XADD为三级地址,则在S2160、S2170、或S2180,执行对相应页的编程操作。 If it is determined for the three input line address XADD address, in S2160, S2170, or S2180, to perform programming operations for the corresponding page.

图27为显示由非易失半导体存储器设备执行的读取操作的实施例的流程图。 Figure 27 is a flowchart of an embodiment of a nonvolatile semiconductor memory device performs a read operation of the display. 在S2210,输入用于命令读取操作的操作命令CMD。 In the S2210, the input for the command to read command operation CMD. 在S2220,输入行地址XADD。 In the S2220, the input line address XADD. 在S2230,确定输入的行地址XADD是否为对应于具有三级存储器单元的页的三级地址。 In S2230, the input row address XADD is determined whether the page having the address corresponding to the three levels of memory cells. 如果确定输入行地址XADD不为三级地址,则在S2240执行典型的两级读取操作。 If it is determined not to enter the third row address XADD address, perform a read operation in a typical two-S2240. 如果确定输入行地址XADD为三级地址,则在S2160、S2170、或S2180,执行对相应页的读取操作。 If it is determined for the three input line address XADD address, in S2160, S2170, or S2180, perform a read operation on the corresponding page.

另外,如图28所示,存储器单元对可以是来自一串的两个存储器单元。 Also, shown in Figure 28, the memory unit may be a unit derived from a series of two memory. 另外,如图29与图30所示,本领域技术人员可以明白:即使本发明的三级非易失半导体存储器设备以NAND型存储器设备实现,也可以适当地修改数据控制电路的结构,从而可以在其他类型的存储器设备(例如NOR或OR型存储器设备)中实现本发明的技术原理。 Further, as shown in FIG. 29 and FIG. 30, those skilled in the art can appreciate: Even three nonvolatile semiconductor memory device of the present invention to the NAND type memory device, or it may be suitably modified structure of the data control circuit, which can Technical realization of the principles of the present invention in other types of memory devices (e.g., NOR or OR type memory device).

虽然为了说明的目的公开了优选实施例,但是本领域技术人员可以理解:在不脱离权利要求限定的本发明的范围与精神的前提下,可以有各种修改、添加以及替换。 Although for purposes of illustration, discloses a preferred embodiment, those skilled in the art can understand: the premise without departing from the scope and spirit of the claims of the present invention, various modifications, additions and substitutions.

Classifications
International ClassificationG11C16/02, G11C16/10
Cooperative ClassificationG11C16/10, G11C11/5628, G11C16/24, G11C11/5642
European ClassificationG11C16/10, G11C16/24, G11C11/56D4, G11C11/56D2
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