CN1902711A - 用于对非易失性存储器阵列编程的方法、系统和电路 - Google Patents

用于对非易失性存储器阵列编程的方法、系统和电路 Download PDF

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CN1902711A
CN1902711A CNA2004800394008A CN200480039400A CN1902711A CN 1902711 A CN1902711 A CN 1902711A CN A2004800394008 A CNA2004800394008 A CN A2004800394008A CN 200480039400 A CN200480039400 A CN 200480039400A CN 1902711 A CN1902711 A CN 1902711A
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盖伊·科亨
博阿兹·埃坦
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Spansion Israel Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

本发明是一种用于编程NVM阵列(100)中的非易失性存储器(“NVM”)单元的多阶段方法、电路和系统。本发明可包括控制器(110)，用于在第一编程阶段(2000)，确定第一组单元的一个或多个单元何时达到或超过第一中间电压，并使电荷泵电路(130)向第一组中的一个或多个单元(100)的端子施加第二阶段编程(3000)脉冲，以便在具有较少储存电荷的单元中比在具有相对多储存电荷的单元中感应相对更大的阈值电压变化。

Description

用于对非易失性存储器阵列编程的方法、系统和电路
发明领域
本发明一般涉及非易失性存储器(“NVM”)单元的领域。更具体地说，本发明涉及使用多相编程序列或算法来编程一个或多个NVM单元的系统、电路和方法。
发明背景
非易失性存储器(NVM)单元在大量的各种结构中制造，包括但不限于如图2A所示的多晶硅浮栅和如图2B所示的氮化物只读存储器(“NROM”)。众所周知，NVM单元的状态可由其阈值电压即栅-源电压来定义和确定，在该阈值电压上，该单元开始明显导通电流。
不同的阈值电压范围与不同的逻辑状态相关，并且NVM单元的阈值电压电平(level)可能与该单元的电荷储存区中储存的电荷(例如电子)量相关。图1A是示出二进制非易失性存储器单元的可能阈值电压分布的电压分布曲线，其中垂直线表示与单元的每一个可能的状态相关的边界电压值。具有低于EV电平的Vt的单元被称为是被擦除验证的。具有高于PV的Vt的单元被称为是被编程验证的。这两个界限定义了可以在单元上进行的编程和擦除序列的完成。可使用编程脉冲的编程序列来驱动高于PV的单元的Vt，而擦除序列可驱动低于EV的单元的Vt。在图1A中还可以看到表示读取验证(RV)电平和中间编程验证电压PVI的垂直线，该中间编程验证电压PVI表示在编程验证阈值之前的区域的开始。
图1B是示出多电平非易失性存储器单元(“MLC”)的电荷储存区中的可能阈值电压分布的电压分布曲线，其中一组垂直线表示与单元的每一个可能的编程验证阈值电压(PV00、PV01等)相关的边界值，另一组垂直线表示与单元的每一个可能的编程状态(RV00、RV01等)的读取验证电平相关的边界值，并且再另外一组表示用于与每个状态相关的中间编程验证电压(PVI00、PVI01等)的边界值。
通过将一个或多个编程脉冲施加于NVM单元，可以增加储存在该NVM单元的电荷储存区中的电荷量。而通过将可以迫使减少该单元的电荷储存区中的电荷的擦除脉冲施加给NVM单元，可以减少该单元中的电荷量，并且因而可以减少NVM的阈值电压。
用于操作NVM单元(例如编程、读取和擦除)的简单方法使用一个或多个参考结构，如参考单元来产生参考电平(即PV、EV)。所述一个或多个参考结构中的每一个可以与正在操作的存储单元相比较，以便确定正在操作的存储单元的条件或状态。通常，为了确定NVM单元是否处于特定状态，例如擦除、编程、或在多电平单元(“MLC”)的多个可能编程状态中的一个状态下编程，将该单元的阈值电平与参考结构的阈值电平进行比较，所述参考结构的阈值电平被预设在或者公知为处于与正在测试的特定状态相关的电压电平上。。将NVM单元的阈值电压与参考单元的阈值电压进行比较通常是使用读出放大器来完成的。用于比较NVM的阈值电压与一个或多个参考单元的阈值电压以便确定NVM的单元状态的各种技术是公知的。
当将NVM单元编程到所希望的状态时，可以将具有被设置在定义为用于给定状态的“编程验证”电平的电压电平的阈值电压的参考单元与正在编程的单元的阈值电压相比较，以便确定该正在被编程的单元的电荷储存区或区域是否已经被充分充电，以便被认为是“被编程”在所希望的状态。如果编程脉冲已经施加于该单元之后，已经确定该单元没有被充分充电以使其阈值电压处于与目标编程状态相关的“编程验证”电平(即相关参考单元的阈值电压)或以上，该单元通常被施加另一编程脉冲，以设法将更多电荷注入到其电荷储存区中。一旦单元的阈值达到或超过其正在被编程的“编程验证”电平，则不应该给该单元施加另外的编程脉冲。
可以对NVM阵列内的多组单元进行同时编程。NVM单元组可由被编程到相同逻辑状态的单元构成，或者可以由被编程到几个可能状态的单元构成，例如，可以是具有MLC阵列的情况。由于不是所有单元都具有对被编程的相同敏感性，因此这些单元可能不以相同速率编程。有些单元可能在被一起编程的同组单元中的其它单元之前达到目标编程状态。
对于提高NVM的性能的需求要求(dictate)使用更强编程脉冲的更积极的编程算法。更强的脉冲可能使NVM单元的Vt明显改变，由此增加了不同单元对编程算法的响应的变化。这被反映在编程尾部(tail)中，使用更积极的算法使其变得更大。可能不希望更大的编程尾部，因为它们降低了NVM单元的耐久性和保持图形。
采用MLC阵列，情况更好。限定MLC单元中的给定逻辑状态的电压阈值边界(例如两个读取电平之间)通常远远小于二进制NVM单元的电压阈值边界。现在参照图1B，其示出了MLC的四个区域，其中每个区域与MLC的编程状态之一相关。由于在MLC中，潜在的阈值电压的固定范围(例如3V-9V)需要被分为几个子范围或区域，因此MLC中的每个子范围或区域的尺寸通常小于二进制NVM单元的区域，如从图1A与1B的比较看出的。用于MLC阵列的编程算法可以考虑编程尾部应该不超过其以上的读取验证参考电平。
将编程算法的步骤减少到越来越少的步骤的简单方案不能保证PGM尾部电压分布的类似减少。这是因为在很多参数(例如物理尺寸、电流路径的电阻、同时需要编程脉冲的单元数量等)中的阵列非均匀性的实际限制。由于单元成组地被编程，因此每个单元经历的施加电压可能在一定程度上不同于由电源输送的脉冲电压。
在半导体领域中，存在着对用于编程NVM阵列中的NVM单元的改进的系统、电路和方法的需求，所述NVM阵列具有对PGM速率更多的控制，由此具有对编程尾部(tail)的变化更多的控制。
用于对MLC单元进行编程的算法是已知的。授予与本发明相同受让人的、在2003年1月30日提交的美国专利申请系列号No.10/354050教导了用于MLC存储器阵列的几种编程算法。特此在本申请中引证这篇美国专利申请系列号No.10/354050的说明书的全文作为参考。
发明内容
本发明是一种用于对NVM阵列中的非易失性存储器(“NVM”)单元进行编程的方法、电路和系统。根据本发明的一些实施例，存储器阵列的一个或多个NVM单元可使用控制器或编程电路来进行编程，所述控制器或编程电路适于提供第一编程阶段和第二编程阶段，其中与第二编程阶段相关的编程脉冲可导致较低的编程速度，因此可以导致较低的编程变化。
根据本发明的一些实施例，存储器阵列的一个或多个NVM单元可使用控制器或编程电路来进行编程，所述控制器或编程电路适于提供第一编程阶段和第二编程阶段，其中与第二编程阶段相关的编程脉冲可以在具有较少的储存电荷的单元中感应出比在具有相对多的储存电荷的单元中感应的相对更大的阈值电压变化。根据本发明的一些实施例，第二编程阶段在第一阶段编程之后可在具有相对较低的阈值电压的单元中感应相对更大的阈值电压变化。
根据本发明的一些实施例，将要被编程到第一目标阈值电压电平的第一组NVM单元可以接收第一阶段编程脉冲，直到第一组中的一个或多个单元到达或超过第一中间阈值电压电平为止，之后第一组中的单元可接收第二阶段编程脉冲，直到第一组中的一个或多个单元或者基本上所有单元都达到第一目标阈值电压为止。
根据本发明的一些实施例，可以用第一阶段编程脉冲对将要编程到第二目标阈值电压电平的第二组NVM单元进行编程，其中第一阶段编程脉冲的初始电压电平可对应于与第一组单元的第二阶段编程相关的初始电压电平。第二组可以接收第一阶段编程脉冲，直到第二组中的一个或多个单元达到或超过第二中间阈值电压电平为止，之后第二组中的单元可以接收第二阶段编程脉冲，直到第二组中的一个或多个单元或者基本上所有单元都达到第二目标阈值电压为止。
根据本发明的一些实施例，可以以与对上述第一和第二组介绍的相似和对应的方式来将第三组NVM单元编程到第三目标阈值电压。这个过程可以扩展到任意大量的单元组，与任意大量的目标阈值电压相关。
根据本发明的一些实施例，第一阶段编程的特征在于：向一组NVM单元的一个或多个NVM单元的端子施加递增的编程脉冲，其与到该一个或多个NVM单元的栅极的基本上固定电压的脉冲相一致(in concert with)。根据本发明的一些实施例，第二阶段编程的特征在于：向该组的一个或多个单元的端子施加基本上固定电压的编程脉冲，其与递增电压的栅极脉冲相一致。根据本发明的可选择的实施例，第二阶段编程的特征在于：向一个或多个单元的端子施加递增电压的编程脉冲，其与相对减少并且基本上固定电压的栅极脉冲相一致。根据本发明的一些实施例，初始第二阶段栅极和漏极电压电平可以从第一阶段期间的单元的验证过程推断出来。
附图说明
在本说明书的结论部分中特别指出和明确申明了作为本发明的主题。但是，通过结合附图来阅读以下非限制性的详细说明可以更好地理解本发明的构造和操作方法，以及其目的、特征和优点，在附图中：
图1A是示出在二进制非易失性存储器单元的电荷储存区中的可能阈值电压分布的电压分布曲线，其中垂直线表示对于单元的每一个可能编程状态的与编程验证、读取验证和中间编程验证电平相关的边界值或电压阈值电平；
图1B是示出在多电平非易失性存储器单元(“MLC”)的电荷储存区中的可能阈值电压分布的电压分布曲线，其中多组垂直线表示对于单元的每一个可能状态的与编程验证、读取验证和中间编程验证电平相关的边界值或电压阈值电平；
图2A是示出浮栅存储器单元的侧向剖面图的方框图；
图2B是示出具有两个不同编程电荷储存区的氮化物只读存储器(“NROM”)单元的侧向剖面图的方框图；
图3示出用于编程NVM单元阵列中的存储器单元所需的控制器和相关电路的方框图；
图4A是示出根据本发明一些实施例在第一编程阶段期间将要施加于NVM单元的端子的编程脉冲(例如Vds)的可能设置的时域电压曲线；
图4B是基本上与图4A的曲线相对准并且示出根据本发明一些实施例的对应于第一阶段编程脉冲的第一阶段栅极脉冲(Vg)的可能设置的时域电压曲线；
图4C是基本上与图4A和4B的曲线在时间上相对准并且示出接收图4A和4B的脉冲(例如Vds和Vg)的第一NVM单元的阈值电压的变化的时域曲线；
图4D是基本上与图4A和4B的曲线在时间上相对准并且示出接收图4A和4B的脉冲的第二NVM单元的阈值电压的变化，由此示出单元之间对同一组脉冲的响应的可能变化的时域曲线；
图5A是示出作为根据本发明一些实施例的两个阶段编程方法的一部分的各个步骤的基本流程图，通过所述步骤可以将一组NVM单元编程到中间电压，然后编程到目标阈值电压；
图5B是示出作为图5A的第一和第二编程阶段的一部分的接收编程脉冲的第一NVM单元的阈值电压的变化的曲线；
图5C是示出作为图5A的第一和第二编程阶段的一部分的接收编程脉冲的第二NVM单元的阈值电压变化的曲线，并且该单元与图5B的单元相比在响应于第二阶段编程脉冲时Vt具有相对更大的变化；
图6A是示出根据本发明一些实施例的将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds)的两条在时间上对准的电压曲线；
图6B是示出根据本发明另一些实施例的将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds)的两条在时间上对准的电压曲线；
图7示出两组在时间上对准的电压曲线，每组表示根据本发明一些实施例将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds)，其中第一组曲线示出将要施加于正在被编程到第一目标阈值电压(即第一编程状态)的NVM单元的脉冲，而第二组曲线示出将要施加于正在被编程到第二中间阈值电压的NVM单元的脉冲，其中第二单元的初始Vds和Vg与第一单元的最终Vds和Vg相关；
图8是示出第一和第二NVM单元的阈值电压的可能变化的第一和第二在时间上对准的阈值电压曲线，其中用图7中的第一组曲线中示出的脉冲对第一NVM单元进行编程，并且用图7中的第二组曲线中示出的脉冲对第二NVM单元进行编程。每个单元的目标阈值电压是该单元正在被编程到的编程验证阈值电压，而中间阈值电压可以是，但不是必须是，与给定的编程验证阈值电压相关的读取验证阈值电压；
图9是示出根据本发明一些实施例的第一编程阶段的步骤的流程图；
图10A是示出根据本发明一些实施例的第二编程阶段的步骤的流程图；
图10B是示出根据本发明另一实施例的第二编程阶段的步骤的流程图。
应该理解，为了这些非限制性说明的简明和清楚，图中所示的元件不必按比例绘制。例如，为了清楚起见，有些元件的尺寸可能相对于其它元件放大了。此外，当适当地考虑时，参考标记可能在附图中重复出现，以表示相应或相似的元件。
发明的详细说明
在下面的详细说明中，为了提供发明的全面理解而阐述了大量的具体细节。但是，本领域普通技术人员应该理解，在不需要这些具体细节的情况下也可以实施本发明。在其他情况下，为了避免使本发明不明确，不详细介绍公知的方法和过程。
本发明是用于编程NVM阵列中的非易失性存储器(“NVM”)单元的方法、电路和系统。根据本发明的一些实施例，存储器阵列的一个或多个NVM单元可使用控制器或编程电路来编程，所述控制器或编程电路适于提供第一编程阶段和第二编程阶段，其中与第二编程阶段相关的编程脉冲在具有较少的储存电荷的单元中比在具有相对多的储存电荷的单元中感应相对更大的阈值电压变化。
根据本发明的一些实施例，将要被编程到第一目标阈值电压电平的第一组NVM单元可以接收第一阶段编程脉冲，直到第一组中的一个或多个单元达到或超过第一中间阈值电压电平为止，之后第一组中的单元可接收第二阶段编程脉冲，直到第一组中的一个或多个单元或者基本上所有单元都达到第一目标阈值电压为止。
根据本发明的一些实施例，可以用第一阶段编程脉冲对将要编程到第二目标阈值电压电平的第二组NVM单元进行编程，其中该第一阶段编程脉冲的初始电压电平可对应于与第一组单元的第二阶段编程相关的初始电压电平。第二组可以接收第一阶段编程脉冲，直到第二组中的一个或多个单元达到或超过第二中间阈值电压电平为止，之后第二组中的单元可接收第二阶段编程脉冲，直到第二组中的一个或多个单元或者基本上所有单元都达到第二目标阈值电压为止。
根据本发明的一些实施例，可以以与对上述第一和第二组介绍的相似和对应的方式来将第三组NVM单元编程到第三目标阈值电压。这个过程可以继续，以完成将要被编程的大量的单元组。
根据本发明的一些实施例，第一阶段编程的特征在于：向一组NVM单元的一个或多个NVM单元的端子施加递增的编程脉冲，其与到该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致。根据本发明的一些实施例，第二阶段编程的特征在于：向该组的一个或多个单元的端子施加基本上固定电压的编程脉冲，其与递增电压的栅极脉冲相一致。根据本发明的可选择的实施例，第二阶段编程的特征在于：向一个或多个单元的端子施加递增电压的编程脉冲，其与相对减少并且基本上固定电压的栅极脉冲相一致。
现在参照图3，其示出了根据本发明一些实施例的连接到控制器110和连接到编程存储器单元所需的相关电路的NVM单元阵列的方框图。阵列100可以由单个储存区NVM单元或多个储存区(例如双位)NVM单元构成。控制器110可适于操作阵列100中的每个单元的每个电荷储存区，如同双电平NVM单元或如同多电平NVM单元。此外，该阵列可以是每个上述结构中的多电平单元的阵列。
将被储存在NVM阵列100上的数据可以首先被接收到缓冲器120(例如，静态随机存取存储器-SRAM)中，然后可以被控制器110读取，该控制器110可以通过命令电荷泵电路130产生对应于将被储存的数据的第一和第二阶段编程脉冲来做出响应。控制器110可以确定将把该数据储存在NVM阵列100中的哪组NVM单元中以及将以哪种格式(例如双电平/二进制-电平，多电平格式)将该数据储存在所选的一组单元中。控制器110可命令单元选择和遮蔽电路140为电荷泵电路130提供对被选单元的存取。控制器110可使用编程验证电路150来确定单元何时到达或超过给定的阈值电压，例如，与二进制或MLC单元的逻辑状态相关的最终目标阈值电压电平，或者与上述逻辑状态相关的中间阈值电压。
现在参见图4A，其是示出了根据本发明一些实施例在第一编程阶段期间将要施加于NVM单元的端子的编程脉冲(例如，Vds等)的可能设置的时域电压曲线。而图4B示出了基本上与图4A的曲线相对准的时域电压曲线，表示根据本发明一些实施例的对应于第一阶段编程脉冲的第一阶段栅极脉冲(Vg)的可能设置。如从这些曲线中可以看出的，根据本发明一些实施例的第一阶段编程脉冲的特征在于：与基本固定的栅极电压(例如Vg＝9.5V)的脉冲相一致的递增编程脉冲(例如Vsd)。为了清楚起见，未示出端子Vds和Vg的验证条件，但是本领域技术人员应当理解它们的存在。对于这两组脉冲的上升和下降之间的准确时间关系保持相同。
现在参照图4C，其是基本上与图4A和4B的曲线在时间上相对准并示出接收图4A和4B的脉冲的第一NVM单元的阈值电压的变化的时域曲线。类似地，图4D是基本上与图4A和4B的曲线在时间上对准并示出接收图4A和4B的脉冲的第二NVM单元的阈值电压的变化的时域曲线。这些曲线，更具体地说是它们之间的差异，示出了两个单元如何不同地响应同一组编程脉冲。因此，根据本发明的一些实施例，第一阶段编程脉冲可施加于一个单元或一组单元，直到一个或多个单元达到中间阈值电平为止，如图4A和4B所示。
定义为一个单元或一组单元的“中间阈值电压电平”的实际阈值电压取决于该单元将被充电到的编程状态。例如，如果这个单元或这组单元将要被充电到由4.5V阈值电压(编程验证电压)定义的第一编程状态，则目标阈值电压可以是4.5V，而中间阈值电压可以是4.0V到4.5V之间的任意值。同样地，如果这个单元或这组单元将要被充电到由6V阈值电压(编程验证电压)定义的第二编程状态，则目标阈值电压可以是6V，而中间阈值电压可以是5.5V到6V之间的任何值。
如从图5A可以看到的，该图5A示出了根据本发明一些实施例的作为两阶段编程方法的一部分可以将一组NVM单元编程到目标阈值电压的步骤的基本流程图，一旦该组中的一个或多个单元已经达到或超过对应于这些单元将要被编程到的目标阈值电压电平的中间阈值电压电平，则可以在第一阶段编程脉冲之后跟随第二阶段编程脉冲。根据本发明一些实施例的第二阶段编程脉冲可以在具有较少储存电荷(即具有较低阈值电压)的单元中比在具有相对多储存电荷(即具有较高阈值电压)的单元中产生相对更大的阈值电压变化。
现在参照图5B，其中示出了表示作为图5A中所示方法的第一和第二编程阶段的一部分的接收编程脉冲的第一NVM单元的阈值电压的变化的曲线，而图5C是与图5B时间/脉冲对准的曲线，示出作为图5A所示方法的第一和第二编程阶段的一部分的接收编程脉冲的第二NVM单元的阈值电压的变化。根据本发明的一些实施例，尽管图5B所示的第一单元在第一编程阶段可以比图5C所示的第二单元更快地充电(即，响应于每个编程脉冲吸收更多的电荷)，但是图5C所示的第二单元在第二阶段编程期间可以比第一单元更快地充电。就是说，响应于第二阶段的每个编程脉冲，第二单元可以比第一单元吸收更多的电荷。根据本发明的一些实施例，第二阶段编程脉冲可以适于感应比第一阶段编程脉冲感应的场更弱的垂直场，并且由此第二阶段编程脉冲可以在具有较少内部储存电荷的单元中感应相对更多的电荷，所述内部储存的电荷可以用于抵消感应的垂直场的部分。
现在参见图6A，其中示出了根据本发明的一些实施例的两个阶段将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds)的两个在时间上对准的电压曲线。在第一编程阶段期间，将要被编程到目标阈值电压电平的一组单元中的一个或多个单元可以接收递增电压的编程脉冲(Vds)，其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致。一旦这组中的一个或多个单元达到或超过对应于该组的目标阈值电压的中间电压，则可以与递增电压的栅极脉冲相一致地施加基本固定电压的第二阶段编程脉冲。根据本发明的一些实施例，在第二阶段期间编程脉冲的基本固定电压可以处于与第一阶段期间施加的最后编程脉冲相同的电压电平上，或者处于与第一阶段期间施加的最后编程脉冲呈函数关系的电压电平上。
现在参见图6B，其中示出了根据本发明的另一些实施例的将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds)的两条在时间上对准的电压曲线。图6B的第一阶段编程脉冲与图6A的基本相同。然而，图6B所示的第二阶段编程脉冲示出了供替换的第二阶段编程方案，其中编程脉冲(Vds)继续增加，但是仅减少栅极脉冲的电压电平。第二阶段的Vg可以与第一阶段中的Vg相关，而Vd增量可以在第一和第二阶段之间变化。
根据本发明的一些实施例，将要被充电/编程到第一目标阈值电压的第一组单元接收第一阶段编程脉冲，直到第一组中的一个或多个单元达到或超过对应于第一目标阈值电压电平的第一中间阈值电压电平为止。一旦第一组中的一个或多个单元达到或超过第一中间阈值电压电平，则第一组中的一些单元或所有单元接收第二阶段编程脉冲。根据本发明的另一些实施例，将要被编程到第二目标阈值电压电平的第二组单元可接收第一阶段编程脉冲，其中第二组的编程第一阶段编程脉冲的电压电平是在第一阶段编程期间施加于第一组单元的最终编程脉冲的函数。现在参见图7，其中示出了两组在时间上对准的电压曲线，每组示出了根据本发明一些实施例的将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds)，其中第一组曲线示出将要施加于正被编程到第一目标阈值电压(即第一编程状态)的第一组单元中的NVM单元的脉冲，而第二组曲线示出将要施加于正被编程到第二目标阈值电压(即第二编程状态)的第二组单元中的NVM单元的脉冲。根据图7所示的本发明的实施例，在第一组中的第一单元已经完成其第一阶段编程之后，第二组的第二单元可以开始第一阶段编程，并且施加于第二组的第一编程脉冲可以是与在第一编程阶段期间施加于第一单元的最终编程脉冲基本相同的、或更小的、或更大的电压。属于第二组的单元可以被编程到接近于但不刚好是第一组的中间电平的电平上。
现在参见图8，其中示出了表示第一和第二NVM单元的阈值电压的可能变化的第一和第二在时间上对准的阈值电压曲线，其中第一NVM单元用图7中的第一组曲线所示的脉冲来编程，第二NVM单元用图7中的第二组曲线所示的脉冲来编程。如对于本领域任何普通技术人员来说应该是显然的，涉及图7和8的原理和方法由于它们涉及本发明而不限于两组单元。根据本发明的一些实施例，可以存在将被编程到第三目标阈值电压的第三组单元、第四、第五等等，其中每个阶段的第一阶段编程脉冲至少部分地是施加于前一组单元的最后一个第一阶段编程脉冲的函数。
现在参见图9，其中示出了根据本发明一些实施例的第一编程阶段的步骤的流程图。根据图9的示例性实施例，将要施加于第一组单元的第一阶段编程脉冲的初始电压电平可以被设置为Vg＝9.5V和Vd＝4V，其中该第一组单元将要被编程到第一中间阈值电压。在第一组的该一个或多个单元中的每个单元接收编程脉冲之后，该脉冲可由图4A和4B所示的Vd和Vg脉冲构成，可以检查该单元的Vt以便确定这些单元中的任何一个单元是否已经达到或超过第一中间阈值电压。如果没有单元已经达到中间Vt，则Vd值可以增加，例如增加100mV，另一编程脉冲可以施加于这些单元。这个循环可以继续进行，直到一个或多个单元达到第一中间Vt为止。
一旦第一组中的一个或多个单元达到第一中间Vt，则第一组单元可以开始接收第二阶段编程脉冲，并且第二组单元可以开始接收第一阶段编程脉冲，其中第二组的第一阶段编程脉冲的初始Vd可能与在第一阶段编程期间施加于第一组的最终(find)Vd相关(例如基本上相等)。根据本发明的一些实施例，第二组单元可继续接收具有增加Vd的编程脉冲，直到第二组中的一个或多个单元达到第二中间Vt为止。根据本发明的一些实施例，可以存在多个中间和目标阈值电压，其中每个目标阈值电压与MLC阵列的不同逻辑状态相关。因此，可以存在第三组、第四组、等等，其中每组单元的第一阶段编程脉冲的电压可以部分地是前一组单元的编程结果的函数。
图10A是示出根据本发明一些实施例的第二编程阶段的步骤的流程图。在一组单元中的一个或多个单元已经达到给定的中间阈值电压电平(例如第一中间Vt)之后，该组可接收第二阶段编程脉冲，以便将这些单元编程到与给定的中间电平相关的目标阈值电压电平。根据图10A的示例性第二阶段编程算法，Vg可以减少几伏(例如Vg＝Vg-2)，并且Vd可以继续增加或以不同增加梯度增加，并且被施加于这组的一个或多个单元(见图6B)，直到达到所希望的目标阈值电压为止。在每个单元达到目标Vt时，可以将其遮蔽并且可以阻挡其接收任何另外的编程脉冲。当所有的单元都被遮蔽时，对给定组的第二阶段编程可以结束。
现在参见图10B，其中示出了根据本发明另一实施例的第二编程阶段的步骤的流程图。根据图10B所示的算法，并且如图6A的曲线所示的，Vd可以固定在第一阶段编程期间施加于该组的最后Vd上，或者Vd可以相对于那个电压而改变，并且Vg基本上减小。然后可以在脉冲之间增加Vg(例如Vg＝Vg+200mV)，直到这组中的单元已经达到相关目标阈值电压电平为止，之后结束用于这个阶段的第二阶段编程，并且对第二组的第二阶段编程可以开始。
尽管这里已经说明和介绍了本发明的某些特征，但是本领域的普通技术人员现在将可以想到很多修改、替换、改变和等价物。因此，应该理解，所附权利要求书趋于覆盖落入本发明的实质内的所有这种修改和变化。

Claims (33)

1、一种对非易失性存储器(“NVM”)单元的阵列进行编程的多阶段方法，所述方法包括：
向第一组NVM单元施加第一阶段编程脉冲；并且
在该第一组单元中的一个或多个NVM单元达到或超过第一中间阈值电压电平之后，向该第一组单元中的一个或多个单元的端子施加第二阶段编程脉冲，该第二阶段编程脉冲适于在具有较少储存电荷的单元中比在具有相对更多储存电荷的单元引起相对更大的阈值电压变化。
2、根据权利要求1的方法，其中向所述第一组单元中的一个或多个NVM单元施加第一阶段编程脉冲包括向所述第一组NVM单元中的一个或多个NVM单元的端子施加递增的编程脉冲，其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致；并且
其中施加第二阶段编程脉冲包括向所述一个或多个单元的端子施加基本固定电压的编程脉冲，其与递增电压的栅极脉冲相一致。
3、根据权利要求2的方法，其中重复进行向所述第一组中的一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲，其与递增电压的栅极脉冲相一致，直到所述第一组中的一个或多个单元达到第一目标阈值电压电平为止。
4、根据权利要求3的方法，其中所述基本固定电压的第二阶段编程脉冲处于与第一次成功地使所述第一组中的一个或多个单元的阈值电压升高到或超过该第一中间阈值电压的编程脉冲的电压相对应的电压。
5、根据权利要求3的方法，其中所述第二阶段栅极脉冲的初始值处于与第一次成功地使所述第一组的一个或多个单元的阈值电压升高到或超过该第一中间阈值电压的编程脉冲的栅极电压相对应的电压。
6、根据权利要求4的方法，其中该NVM单元是多电平单元。
7、根据权利要求6的方法，还包括向将要被编程到第二目标阈值电压的第二组NVM单元的一个或多个NVM单元的端子施加递增电压的第一阶段编程脉冲，其与施加于所述第二组的所述NVM单元中的每个单元的栅极的基本固定电压的脉冲相一致，其中施加于该第二组的一个或多个NVM单元的端子的所述第一编程脉冲具有与第一次成功地使所述第一组中的单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的电压相对应的电压。
8、根据权利要求7的方法，还包括：在所述第二组中的一个或多个NVM单元达到或超过第二中间阈值电压之后，向所述第二组的一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲，其与递增电压的栅极脉冲相一致。
9、根据权利要求8的方法，其中重复进行向所述第二组中的一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲，其与递增电压的栅极脉冲相一致，直到所述第二组的所述单元达到该第二目标阈值电压为止。
10、根据权利要求1的方法，其中第一阶段编程包括向第一组NVM单元的一个或多个NVM单元的端子施加递增的编程脉冲，其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致；和
其中向所述第一组中的一个或多个单元施加第二阶段编程脉冲包括向该一个或多个单元的端子施加递增电压的编程脉冲，其与相对减少且基本固定电压的栅极脉冲相一致。
11、根据权利要求10的方法，其中向第一组的一个或多个单元的端子施加递增电压的编程脉冲重复进行，直到所述第一组的该一个或多个单元都达到第一目标阈值电压为止。
12、根据权利要求11的方法，其中该NVM单元是多电平单元。
13、根据权利要求12的方法，还包括向将要被编程到第二目标阈值电压的第二组NVM单元的一个或多个NVM单元的端子施加递增电压的第一阶段编程脉冲，其与施加于该第二组的一个或多个单元的栅极的基本固定电压的脉冲相一致，其中施加于该第二组的该一个或多个NVM单元的端子的所述第一阶段编程脉冲具有与第一次成功地使所述第一组的一个或多个单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的电压相对应的电压。
14、根据权利要求1的方法，其中所述NVM单元选自氮化物只读存储器(“NROM”)、多电平单元(“MLC”)、双电荷捕获区NROM、和双电荷捕获区MLC NROM构成的组。
15、一种编程非易失性存储器(“NVM”)单元的阵列的多阶段方法，所述方法包括：
向第一组NVM单元施加第一阶段编程脉冲；和
在该第一组单元的一个或多个NVM单元达到或超过第一中间阈值电压电平之后，向所述第一组单元施加第二阶段编程脉冲，该第二阶段编程脉冲具有的特性使得在接收基本相同数量的第二阶段编程脉冲之后，所述第一组单元中的基本上所有单元都基本上达到了目标阈值电压。
16、根据权利要求15的方法，其中向所述第一组单元的一个或多个NVM单元施加第一阶段编程脉冲包括向所述第一组NVM单元的一个或多个NVM单元的端子施加递增的编程脉冲，其与施加于所述一个或多个NVM单元的栅极的基本固定电压的脉冲相一致；和
其中施加第二阶段编程脉冲包括向所述一个或多个单元的端子施加基本固定电压的编程脉冲，其与递增电压的栅极脉冲相一致。
17、根据权利要求16的方法，其中重复进行向所述第一组的所述一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲，其与递增电压的栅极脉冲相一致，直到所述第一组的一个或多个单元达到第一目标阈值电压电平为止。
18、根据权利要求17的方法，其中基本固定电压的所述第二阶段编程脉冲处于与第一次成功地使所述第一组的一个或多个单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的电压相对应的电压。
19、根据权利要求17的方法，其中所述第二阶段栅极脉冲的初始值处于与第一次成功地使所述第一组的一个或多个单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的栅极电压相对应的电压。
20、根据权利要求18的方法，其中所述NVM单元是多电平单元。
21、根据权利要求20的方法，还包括向将要被编程到第二目标阈值电压的第二组NVM单元的一个或多个NVM单元的端子施加递增电压的第一阶段编程脉冲，其与施加于所述第二组的所述NVM单元中的每一个的栅极的基本固定电压的脉冲相一致，其中施加于该第二组的该一个或多个NVM单元的端子的第一编程脉冲具有与第一次成功地使所述第一组的单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的电压相对应的电压。
22、根据权利要求21的方法，还包括：在所述第二组的一个或多个NVM单元达到或超过第二中间阈值电压之后，向该第二组的一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲，其与递增电压的栅极脉冲相一致。
23、根据权利要求22的方法，其中重复进行向所述第二组的一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲，其与递增电压的栅极脉冲相一致，直到所述第二组的所述单元达到所述第二目标阈值电压为止。
24、根据权利要求15的方法，其中第一阶段编程包括向第一组NVM单元的一个或多个NVM单元的端子施加递增的编程脉冲，其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致：和
其中向所述第一组的一个或多个单元施加第二阶段编程脉冲包括向所述一个或多个单元的端子施加递增电压的编程脉冲，其与相对减少且基本固定电压的栅极脉冲相一致。
25、根据权利要求24的方法，其中向第一组的一个或多个单元的端子施加递增电压的编程脉冲重复进行，直到所述第一组的所述一个或多个单元都达到第一目标阈值电压为止。
26、根据权利要求25的方法，其中该NVM单元是多电平单元。
27、根据权利要求26的方法，还包括向将要被编程到第二目标阈值电压的第二组NVM单元的一个或多个NVM单元的端子施加递增电压的第一阶段编程脉冲，其与施加于所述第二组的一个或多个单元的栅极的基本固定电压的脉冲相一致，其中施加于所述第二组中的一个或多个NVM单元的端子的第一阶段编程脉冲具有与第一次成功地使所述第一组的一个或多个单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的电压相对应的电压。
28、根据权利要求15的方法，其中所述NVM单元选自氮化物只读存储器(“NROM”)、多电平单元(“MLC”)、双电荷捕获区NROM、和双电荷捕获区MLC NROM构成的组。
29、一种用于编程非易失性存储器(“NVM”)单元的阵列的系统，所述系统包括：
控制器，适于使电荷电路产生第一阶段编程脉冲和确定接收该第一阶段编程脉冲的第一组单元的一个或多个NVM单元何时达到或超过第一中间电压，然后使所述电荷泵电路向该第一组中的一个或多个单元的端子施加第二阶段编程脉冲，所述第二阶段编程脉冲适于在具有较少储存电荷的单元中比在具有相对更多储存电荷的单元中引起相对更大的阈值电压变化。
30、根据权利要求29的系统，其中所述控制器适于使所述电荷泵电路初始向所述第一组NVM单元的一个或多个NVM单元的端子施加具有递增电压电平的第一阶段编程脉冲，其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致，并且一旦一个或多个单元的阈值电压达到或超过中间阈值电压电平，则所述控制器适于使所述电荷泵电路向一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲，其与递增电压的栅极脉冲相一致。
31、根据权利要求30的系统，其中所述控制器适于使所述电荷泵电路初始向所述第一组NVM单元的一个或多个NVM单元的端子施加递增电压的第一阶段编程脉冲，其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致，并且一旦一个或多个单元的阈值电压达到或超过中间阈值电压电平，则所述控制器适于使所述电荷泵电路向一个或多个单元的端子施加递增电压的第二阶段编程脉冲，其与基本固定且减少电压的栅极脉冲相一致。
32、一种编程非易失性存储器(“NVM”)单元的阵列的多阶段方法，所述方法包括：
向第一组NVM单元施加第一阶段编程脉冲；和
在该第一组单元的一个或多个NVM单元达到或超过第一中间阈值电压电平之后，向所述第一组单元的一个或多个单元的端子施加第二阶段编程脉冲，该第二阶段编程脉冲适于对第一组中的所有单元引起确定较低的编程速度。
33、一种用于编程非易失性存储器(“NVM”)单元的阵列的系统，所述系统包括：
控制器，适于使电荷电路产生第一阶段编程脉冲和确定接收该第一阶段编程脉冲的第一组单元的一个或多个NVM单元何时达到或超过第一中间电压，然后使所述电荷电路向所述第一组中的一个或多个单元的端子施加第二阶段编程脉冲，所述第二阶段编程脉冲适于引起确定减少的编程速度。
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CN102203874A (zh) * 2008-10-24 2011-09-28 桑迪士克股份有限公司 以高分辨率可变初始编程脉冲对非易失性存储器编程
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