CN1902711A - 用于对非易失性存储器阵列编程的方法、系统和电路 - Google Patents
用于对非易失性存储器阵列编程的方法、系统和电路 Download PDFInfo
- Publication number
- CN1902711A CN1902711A CNA2004800394008A CN200480039400A CN1902711A CN 1902711 A CN1902711 A CN 1902711A CN A2004800394008 A CNA2004800394008 A CN A2004800394008A CN 200480039400 A CN200480039400 A CN 200480039400A CN 1902711 A CN1902711 A CN 1902711A
- Authority
- CN
- China
- Prior art keywords
- unit
- group
- voltage
- programming pulse
- nvm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
本发明是一种用于编程NVM阵列(100)中的非易失性存储器(“NVM”)单元的多阶段方法、电路和系统。本发明可包括控制器(110),用于在第一编程阶段(2000),确定第一组单元的一个或多个单元何时达到或超过第一中间电压,并使电荷泵电路(130)向第一组中的一个或多个单元(100)的端子施加第二阶段编程(3000)脉冲,以便在具有较少储存电荷的单元中比在具有相对多储存电荷的单元中感应相对更大的阈值电压变化。
Description
发明领域
本发明一般涉及非易失性存储器(“NVM”)单元的领域。更具体地说,本发明涉及使用多相编程序列或算法来编程一个或多个NVM单元的系统、电路和方法。
发明背景
非易失性存储器(NVM)单元在大量的各种结构中制造,包括但不限于如图2A所示的多晶硅浮栅和如图2B所示的氮化物只读存储器(“NROM”)。众所周知,NVM单元的状态可由其阈值电压即栅-源电压来定义和确定,在该阈值电压上,该单元开始明显导通电流。
不同的阈值电压范围与不同的逻辑状态相关,并且NVM单元的阈值电压电平(level)可能与该单元的电荷储存区中储存的电荷(例如电子)量相关。图1A是示出二进制非易失性存储器单元的可能阈值电压分布的电压分布曲线,其中垂直线表示与单元的每一个可能的状态相关的边界电压值。具有低于EV电平的Vt的单元被称为是被擦除验证的。具有高于PV的Vt的单元被称为是被编程验证的。这两个界限定义了可以在单元上进行的编程和擦除序列的完成。可使用编程脉冲的编程序列来驱动高于PV的单元的Vt,而擦除序列可驱动低于EV的单元的Vt。在图1A中还可以看到表示读取验证(RV)电平和中间编程验证电压PVI的垂直线,该中间编程验证电压PVI表示在编程验证阈值之前的区域的开始。
图1B是示出多电平非易失性存储器单元(“MLC”)的电荷储存区中的可能阈值电压分布的电压分布曲线,其中一组垂直线表示与单元的每一个可能的编程验证阈值电压(PV00、PV01等)相关的边界值,另一组垂直线表示与单元的每一个可能的编程状态(RV00、RV01等)的读取验证电平相关的边界值,并且再另外一组表示用于与每个状态相关的中间编程验证电压(PVI00、PVI01等)的边界值。
通过将一个或多个编程脉冲施加于NVM单元,可以增加储存在该NVM单元的电荷储存区中的电荷量。而通过将可以迫使减少该单元的电荷储存区中的电荷的擦除脉冲施加给NVM单元,可以减少该单元中的电荷量,并且因而可以减少NVM的阈值电压。
用于操作NVM单元(例如编程、读取和擦除)的简单方法使用一个或多个参考结构,如参考单元来产生参考电平(即PV、EV)。所述一个或多个参考结构中的每一个可以与正在操作的存储单元相比较,以便确定正在操作的存储单元的条件或状态。通常,为了确定NVM单元是否处于特定状态,例如擦除、编程、或在多电平单元(“MLC”)的多个可能编程状态中的一个状态下编程,将该单元的阈值电平与参考结构的阈值电平进行比较,所述参考结构的阈值电平被预设在或者公知为处于与正在测试的特定状态相关的电压电平上。。将NVM单元的阈值电压与参考单元的阈值电压进行比较通常是使用读出放大器来完成的。用于比较NVM的阈值电压与一个或多个参考单元的阈值电压以便确定NVM的单元状态的各种技术是公知的。
当将NVM单元编程到所希望的状态时,可以将具有被设置在定义为用于给定状态的“编程验证”电平的电压电平的阈值电压的参考单元与正在编程的单元的阈值电压相比较,以便确定该正在被编程的单元的电荷储存区或区域是否已经被充分充电,以便被认为是“被编程”在所希望的状态。如果编程脉冲已经施加于该单元之后,已经确定该单元没有被充分充电以使其阈值电压处于与目标编程状态相关的“编程验证”电平(即相关参考单元的阈值电压)或以上,该单元通常被施加另一编程脉冲,以设法将更多电荷注入到其电荷储存区中。一旦单元的阈值达到或超过其正在被编程的“编程验证”电平,则不应该给该单元施加另外的编程脉冲。
可以对NVM阵列内的多组单元进行同时编程。NVM单元组可由被编程到相同逻辑状态的单元构成,或者可以由被编程到几个可能状态的单元构成,例如,可以是具有MLC阵列的情况。由于不是所有单元都具有对被编程的相同敏感性,因此这些单元可能不以相同速率编程。有些单元可能在被一起编程的同组单元中的其它单元之前达到目标编程状态。
对于提高NVM的性能的需求要求(dictate)使用更强编程脉冲的更积极的编程算法。更强的脉冲可能使NVM单元的Vt明显改变,由此增加了不同单元对编程算法的响应的变化。这被反映在编程尾部(tail)中,使用更积极的算法使其变得更大。可能不希望更大的编程尾部,因为它们降低了NVM单元的耐久性和保持图形。
采用MLC阵列,情况更好。限定MLC单元中的给定逻辑状态的电压阈值边界(例如两个读取电平之间)通常远远小于二进制NVM单元的电压阈值边界。现在参照图1B,其示出了MLC的四个区域,其中每个区域与MLC的编程状态之一相关。由于在MLC中,潜在的阈值电压的固定范围(例如3V-9V)需要被分为几个子范围或区域,因此MLC中的每个子范围或区域的尺寸通常小于二进制NVM单元的区域,如从图1A与1B的比较看出的。用于MLC阵列的编程算法可以考虑编程尾部应该不超过其以上的读取验证参考电平。
将编程算法的步骤减少到越来越少的步骤的简单方案不能保证PGM尾部电压分布的类似减少。这是因为在很多参数(例如物理尺寸、电流路径的电阻、同时需要编程脉冲的单元数量等)中的阵列非均匀性的实际限制。由于单元成组地被编程,因此每个单元经历的施加电压可能在一定程度上不同于由电源输送的脉冲电压。
在半导体领域中,存在着对用于编程NVM阵列中的NVM单元的改进的系统、电路和方法的需求,所述NVM阵列具有对PGM速率更多的控制,由此具有对编程尾部(tail)的变化更多的控制。
用于对MLC单元进行编程的算法是已知的。授予与本发明相同受让人的、在2003年1月30日提交的美国专利申请系列号No.10/354050教导了用于MLC存储器阵列的几种编程算法。特此在本申请中引证这篇美国专利申请系列号No.10/354050的说明书的全文作为参考。
发明内容
本发明是一种用于对NVM阵列中的非易失性存储器(“NVM”)单元进行编程的方法、电路和系统。根据本发明的一些实施例,存储器阵列的一个或多个NVM单元可使用控制器或编程电路来进行编程,所述控制器或编程电路适于提供第一编程阶段和第二编程阶段,其中与第二编程阶段相关的编程脉冲可导致较低的编程速度,因此可以导致较低的编程变化。
根据本发明的一些实施例,存储器阵列的一个或多个NVM单元可使用控制器或编程电路来进行编程,所述控制器或编程电路适于提供第一编程阶段和第二编程阶段,其中与第二编程阶段相关的编程脉冲可以在具有较少的储存电荷的单元中感应出比在具有相对多的储存电荷的单元中感应的相对更大的阈值电压变化。根据本发明的一些实施例,第二编程阶段在第一阶段编程之后可在具有相对较低的阈值电压的单元中感应相对更大的阈值电压变化。
根据本发明的一些实施例,将要被编程到第一目标阈值电压电平的第一组NVM单元可以接收第一阶段编程脉冲,直到第一组中的一个或多个单元到达或超过第一中间阈值电压电平为止,之后第一组中的单元可接收第二阶段编程脉冲,直到第一组中的一个或多个单元或者基本上所有单元都达到第一目标阈值电压为止。
根据本发明的一些实施例,可以用第一阶段编程脉冲对将要编程到第二目标阈值电压电平的第二组NVM单元进行编程,其中第一阶段编程脉冲的初始电压电平可对应于与第一组单元的第二阶段编程相关的初始电压电平。第二组可以接收第一阶段编程脉冲,直到第二组中的一个或多个单元达到或超过第二中间阈值电压电平为止,之后第二组中的单元可以接收第二阶段编程脉冲,直到第二组中的一个或多个单元或者基本上所有单元都达到第二目标阈值电压为止。
根据本发明的一些实施例,可以以与对上述第一和第二组介绍的相似和对应的方式来将第三组NVM单元编程到第三目标阈值电压。这个过程可以扩展到任意大量的单元组,与任意大量的目标阈值电压相关。
根据本发明的一些实施例,第一阶段编程的特征在于:向一组NVM单元的一个或多个NVM单元的端子施加递增的编程脉冲,其与到该一个或多个NVM单元的栅极的基本上固定电压的脉冲相一致(in concert with)。根据本发明的一些实施例,第二阶段编程的特征在于:向该组的一个或多个单元的端子施加基本上固定电压的编程脉冲,其与递增电压的栅极脉冲相一致。根据本发明的可选择的实施例,第二阶段编程的特征在于:向一个或多个单元的端子施加递增电压的编程脉冲,其与相对减少并且基本上固定电压的栅极脉冲相一致。根据本发明的一些实施例,初始第二阶段栅极和漏极电压电平可以从第一阶段期间的单元的验证过程推断出来。
附图说明
在本说明书的结论部分中特别指出和明确申明了作为本发明的主题。但是,通过结合附图来阅读以下非限制性的详细说明可以更好地理解本发明的构造和操作方法,以及其目的、特征和优点,在附图中:
图1A是示出在二进制非易失性存储器单元的电荷储存区中的可能阈值电压分布的电压分布曲线,其中垂直线表示对于单元的每一个可能编程状态的与编程验证、读取验证和中间编程验证电平相关的边界值或电压阈值电平;
图1B是示出在多电平非易失性存储器单元(“MLC”)的电荷储存区中的可能阈值电压分布的电压分布曲线,其中多组垂直线表示对于单元的每一个可能状态的与编程验证、读取验证和中间编程验证电平相关的边界值或电压阈值电平;
图2A是示出浮栅存储器单元的侧向剖面图的方框图;
图2B是示出具有两个不同编程电荷储存区的氮化物只读存储器(“NROM”)单元的侧向剖面图的方框图;
图3示出用于编程NVM单元阵列中的存储器单元所需的控制器和相关电路的方框图;
图4A是示出根据本发明一些实施例在第一编程阶段期间将要施加于NVM单元的端子的编程脉冲(例如Vds)的可能设置的时域电压曲线;
图4B是基本上与图4A的曲线相对准并且示出根据本发明一些实施例的对应于第一阶段编程脉冲的第一阶段栅极脉冲(Vg)的可能设置的时域电压曲线;
图4C是基本上与图4A和4B的曲线在时间上相对准并且示出接收图4A和4B的脉冲(例如Vds和Vg)的第一NVM单元的阈值电压的变化的时域曲线;
图4D是基本上与图4A和4B的曲线在时间上相对准并且示出接收图4A和4B的脉冲的第二NVM单元的阈值电压的变化,由此示出单元之间对同一组脉冲的响应的可能变化的时域曲线;
图5A是示出作为根据本发明一些实施例的两个阶段编程方法的一部分的各个步骤的基本流程图,通过所述步骤可以将一组NVM单元编程到中间电压,然后编程到目标阈值电压;
图5B是示出作为图5A的第一和第二编程阶段的一部分的接收编程脉冲的第一NVM单元的阈值电压的变化的曲线;
图5C是示出作为图5A的第一和第二编程阶段的一部分的接收编程脉冲的第二NVM单元的阈值电压变化的曲线,并且该单元与图5B的单元相比在响应于第二阶段编程脉冲时Vt具有相对更大的变化;
图6A是示出根据本发明一些实施例的将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds)的两条在时间上对准的电压曲线;
图6B是示出根据本发明另一些实施例的将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds)的两条在时间上对准的电压曲线;
图7示出两组在时间上对准的电压曲线,每组表示根据本发明一些实施例将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds),其中第一组曲线示出将要施加于正在被编程到第一目标阈值电压(即第一编程状态)的NVM单元的脉冲,而第二组曲线示出将要施加于正在被编程到第二中间阈值电压的NVM单元的脉冲,其中第二单元的初始Vds和Vg与第一单元的最终Vds和Vg相关;
图8是示出第一和第二NVM单元的阈值电压的可能变化的第一和第二在时间上对准的阈值电压曲线,其中用图7中的第一组曲线中示出的脉冲对第一NVM单元进行编程,并且用图7中的第二组曲线中示出的脉冲对第二NVM单元进行编程。每个单元的目标阈值电压是该单元正在被编程到的编程验证阈值电压,而中间阈值电压可以是,但不是必须是,与给定的编程验证阈值电压相关的读取验证阈值电压;
图9是示出根据本发明一些实施例的第一编程阶段的步骤的流程图;
图10A是示出根据本发明一些实施例的第二编程阶段的步骤的流程图;
图10B是示出根据本发明另一实施例的第二编程阶段的步骤的流程图。
应该理解,为了这些非限制性说明的简明和清楚,图中所示的元件不必按比例绘制。例如,为了清楚起见,有些元件的尺寸可能相对于其它元件放大了。此外,当适当地考虑时,参考标记可能在附图中重复出现,以表示相应或相似的元件。
发明的详细说明
在下面的详细说明中,为了提供发明的全面理解而阐述了大量的具体细节。但是,本领域普通技术人员应该理解,在不需要这些具体细节的情况下也可以实施本发明。在其他情况下,为了避免使本发明不明确,不详细介绍公知的方法和过程。
本发明是用于编程NVM阵列中的非易失性存储器(“NVM”)单元的方法、电路和系统。根据本发明的一些实施例,存储器阵列的一个或多个NVM单元可使用控制器或编程电路来编程,所述控制器或编程电路适于提供第一编程阶段和第二编程阶段,其中与第二编程阶段相关的编程脉冲在具有较少的储存电荷的单元中比在具有相对多的储存电荷的单元中感应相对更大的阈值电压变化。
根据本发明的一些实施例,将要被编程到第一目标阈值电压电平的第一组NVM单元可以接收第一阶段编程脉冲,直到第一组中的一个或多个单元达到或超过第一中间阈值电压电平为止,之后第一组中的单元可接收第二阶段编程脉冲,直到第一组中的一个或多个单元或者基本上所有单元都达到第一目标阈值电压为止。
根据本发明的一些实施例,可以用第一阶段编程脉冲对将要编程到第二目标阈值电压电平的第二组NVM单元进行编程,其中该第一阶段编程脉冲的初始电压电平可对应于与第一组单元的第二阶段编程相关的初始电压电平。第二组可以接收第一阶段编程脉冲,直到第二组中的一个或多个单元达到或超过第二中间阈值电压电平为止,之后第二组中的单元可接收第二阶段编程脉冲,直到第二组中的一个或多个单元或者基本上所有单元都达到第二目标阈值电压为止。
根据本发明的一些实施例,可以以与对上述第一和第二组介绍的相似和对应的方式来将第三组NVM单元编程到第三目标阈值电压。这个过程可以继续,以完成将要被编程的大量的单元组。
根据本发明的一些实施例,第一阶段编程的特征在于:向一组NVM单元的一个或多个NVM单元的端子施加递增的编程脉冲,其与到该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致。根据本发明的一些实施例,第二阶段编程的特征在于:向该组的一个或多个单元的端子施加基本上固定电压的编程脉冲,其与递增电压的栅极脉冲相一致。根据本发明的可选择的实施例,第二阶段编程的特征在于:向一个或多个单元的端子施加递增电压的编程脉冲,其与相对减少并且基本上固定电压的栅极脉冲相一致。
现在参照图3,其示出了根据本发明一些实施例的连接到控制器110和连接到编程存储器单元所需的相关电路的NVM单元阵列的方框图。阵列100可以由单个储存区NVM单元或多个储存区(例如双位)NVM单元构成。控制器110可适于操作阵列100中的每个单元的每个电荷储存区,如同双电平NVM单元或如同多电平NVM单元。此外,该阵列可以是每个上述结构中的多电平单元的阵列。
将被储存在NVM阵列100上的数据可以首先被接收到缓冲器120(例如,静态随机存取存储器-SRAM)中,然后可以被控制器110读取,该控制器110可以通过命令电荷泵电路130产生对应于将被储存的数据的第一和第二阶段编程脉冲来做出响应。控制器110可以确定将把该数据储存在NVM阵列100中的哪组NVM单元中以及将以哪种格式(例如双电平/二进制-电平,多电平格式)将该数据储存在所选的一组单元中。控制器110可命令单元选择和遮蔽电路140为电荷泵电路130提供对被选单元的存取。控制器110可使用编程验证电路150来确定单元何时到达或超过给定的阈值电压,例如,与二进制或MLC单元的逻辑状态相关的最终目标阈值电压电平,或者与上述逻辑状态相关的中间阈值电压。
现在参见图4A,其是示出了根据本发明一些实施例在第一编程阶段期间将要施加于NVM单元的端子的编程脉冲(例如,Vds等)的可能设置的时域电压曲线。而图4B示出了基本上与图4A的曲线相对准的时域电压曲线,表示根据本发明一些实施例的对应于第一阶段编程脉冲的第一阶段栅极脉冲(Vg)的可能设置。如从这些曲线中可以看出的,根据本发明一些实施例的第一阶段编程脉冲的特征在于:与基本固定的栅极电压(例如Vg=9.5V)的脉冲相一致的递增编程脉冲(例如Vsd)。为了清楚起见,未示出端子Vds和Vg的验证条件,但是本领域技术人员应当理解它们的存在。对于这两组脉冲的上升和下降之间的准确时间关系保持相同。
现在参照图4C,其是基本上与图4A和4B的曲线在时间上相对准并示出接收图4A和4B的脉冲的第一NVM单元的阈值电压的变化的时域曲线。类似地,图4D是基本上与图4A和4B的曲线在时间上对准并示出接收图4A和4B的脉冲的第二NVM单元的阈值电压的变化的时域曲线。这些曲线,更具体地说是它们之间的差异,示出了两个单元如何不同地响应同一组编程脉冲。因此,根据本发明的一些实施例,第一阶段编程脉冲可施加于一个单元或一组单元,直到一个或多个单元达到中间阈值电平为止,如图4A和4B所示。
定义为一个单元或一组单元的“中间阈值电压电平”的实际阈值电压取决于该单元将被充电到的编程状态。例如,如果这个单元或这组单元将要被充电到由4.5V阈值电压(编程验证电压)定义的第一编程状态,则目标阈值电压可以是4.5V,而中间阈值电压可以是4.0V到4.5V之间的任意值。同样地,如果这个单元或这组单元将要被充电到由6V阈值电压(编程验证电压)定义的第二编程状态,则目标阈值电压可以是6V,而中间阈值电压可以是5.5V到6V之间的任何值。
如从图5A可以看到的,该图5A示出了根据本发明一些实施例的作为两阶段编程方法的一部分可以将一组NVM单元编程到目标阈值电压的步骤的基本流程图,一旦该组中的一个或多个单元已经达到或超过对应于这些单元将要被编程到的目标阈值电压电平的中间阈值电压电平,则可以在第一阶段编程脉冲之后跟随第二阶段编程脉冲。根据本发明一些实施例的第二阶段编程脉冲可以在具有较少储存电荷(即具有较低阈值电压)的单元中比在具有相对多储存电荷(即具有较高阈值电压)的单元中产生相对更大的阈值电压变化。
现在参照图5B,其中示出了表示作为图5A中所示方法的第一和第二编程阶段的一部分的接收编程脉冲的第一NVM单元的阈值电压的变化的曲线,而图5C是与图5B时间/脉冲对准的曲线,示出作为图5A所示方法的第一和第二编程阶段的一部分的接收编程脉冲的第二NVM单元的阈值电压的变化。根据本发明的一些实施例,尽管图5B所示的第一单元在第一编程阶段可以比图5C所示的第二单元更快地充电(即,响应于每个编程脉冲吸收更多的电荷),但是图5C所示的第二单元在第二阶段编程期间可以比第一单元更快地充电。就是说,响应于第二阶段的每个编程脉冲,第二单元可以比第一单元吸收更多的电荷。根据本发明的一些实施例,第二阶段编程脉冲可以适于感应比第一阶段编程脉冲感应的场更弱的垂直场,并且由此第二阶段编程脉冲可以在具有较少内部储存电荷的单元中感应相对更多的电荷,所述内部储存的电荷可以用于抵消感应的垂直场的部分。
现在参见图6A,其中示出了根据本发明的一些实施例的两个阶段将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds)的两个在时间上对准的电压曲线。在第一编程阶段期间,将要被编程到目标阈值电压电平的一组单元中的一个或多个单元可以接收递增电压的编程脉冲(Vds),其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致。一旦这组中的一个或多个单元达到或超过对应于该组的目标阈值电压的中间电压,则可以与递增电压的栅极脉冲相一致地施加基本固定电压的第二阶段编程脉冲。根据本发明的一些实施例,在第二阶段期间编程脉冲的基本固定电压可以处于与第一阶段期间施加的最后编程脉冲相同的电压电平上,或者处于与第一阶段期间施加的最后编程脉冲呈函数关系的电压电平上。
现在参见图6B,其中示出了根据本发明的另一些实施例的将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds)的两条在时间上对准的电压曲线。图6B的第一阶段编程脉冲与图6A的基本相同。然而,图6B所示的第二阶段编程脉冲示出了供替换的第二阶段编程方案,其中编程脉冲(Vds)继续增加,但是仅减少栅极脉冲的电压电平。第二阶段的Vg可以与第一阶段中的Vg相关,而Vd增量可以在第一和第二阶段之间变化。
根据本发明的一些实施例,将要被充电/编程到第一目标阈值电压的第一组单元接收第一阶段编程脉冲,直到第一组中的一个或多个单元达到或超过对应于第一目标阈值电压电平的第一中间阈值电压电平为止。一旦第一组中的一个或多个单元达到或超过第一中间阈值电压电平,则第一组中的一些单元或所有单元接收第二阶段编程脉冲。根据本发明的另一些实施例,将要被编程到第二目标阈值电压电平的第二组单元可接收第一阶段编程脉冲,其中第二组的编程第一阶段编程脉冲的电压电平是在第一阶段编程期间施加于第一组单元的最终编程脉冲的函数。现在参见图7,其中示出了两组在时间上对准的电压曲线,每组示出了根据本发明一些实施例的将要施加于NVM单元的栅极脉冲(Vg)和编程脉冲(Vds),其中第一组曲线示出将要施加于正被编程到第一目标阈值电压(即第一编程状态)的第一组单元中的NVM单元的脉冲,而第二组曲线示出将要施加于正被编程到第二目标阈值电压(即第二编程状态)的第二组单元中的NVM单元的脉冲。根据图7所示的本发明的实施例,在第一组中的第一单元已经完成其第一阶段编程之后,第二组的第二单元可以开始第一阶段编程,并且施加于第二组的第一编程脉冲可以是与在第一编程阶段期间施加于第一单元的最终编程脉冲基本相同的、或更小的、或更大的电压。属于第二组的单元可以被编程到接近于但不刚好是第一组的中间电平的电平上。
现在参见图8,其中示出了表示第一和第二NVM单元的阈值电压的可能变化的第一和第二在时间上对准的阈值电压曲线,其中第一NVM单元用图7中的第一组曲线所示的脉冲来编程,第二NVM单元用图7中的第二组曲线所示的脉冲来编程。如对于本领域任何普通技术人员来说应该是显然的,涉及图7和8的原理和方法由于它们涉及本发明而不限于两组单元。根据本发明的一些实施例,可以存在将被编程到第三目标阈值电压的第三组单元、第四、第五等等,其中每个阶段的第一阶段编程脉冲至少部分地是施加于前一组单元的最后一个第一阶段编程脉冲的函数。
现在参见图9,其中示出了根据本发明一些实施例的第一编程阶段的步骤的流程图。根据图9的示例性实施例,将要施加于第一组单元的第一阶段编程脉冲的初始电压电平可以被设置为Vg=9.5V和Vd=4V,其中该第一组单元将要被编程到第一中间阈值电压。在第一组的该一个或多个单元中的每个单元接收编程脉冲之后,该脉冲可由图4A和4B所示的Vd和Vg脉冲构成,可以检查该单元的Vt以便确定这些单元中的任何一个单元是否已经达到或超过第一中间阈值电压。如果没有单元已经达到中间Vt,则Vd值可以增加,例如增加100mV,另一编程脉冲可以施加于这些单元。这个循环可以继续进行,直到一个或多个单元达到第一中间Vt为止。
一旦第一组中的一个或多个单元达到第一中间Vt,则第一组单元可以开始接收第二阶段编程脉冲,并且第二组单元可以开始接收第一阶段编程脉冲,其中第二组的第一阶段编程脉冲的初始Vd可能与在第一阶段编程期间施加于第一组的最终(find)Vd相关(例如基本上相等)。根据本发明的一些实施例,第二组单元可继续接收具有增加Vd的编程脉冲,直到第二组中的一个或多个单元达到第二中间Vt为止。根据本发明的一些实施例,可以存在多个中间和目标阈值电压,其中每个目标阈值电压与MLC阵列的不同逻辑状态相关。因此,可以存在第三组、第四组、等等,其中每组单元的第一阶段编程脉冲的电压可以部分地是前一组单元的编程结果的函数。
图10A是示出根据本发明一些实施例的第二编程阶段的步骤的流程图。在一组单元中的一个或多个单元已经达到给定的中间阈值电压电平(例如第一中间Vt)之后,该组可接收第二阶段编程脉冲,以便将这些单元编程到与给定的中间电平相关的目标阈值电压电平。根据图10A的示例性第二阶段编程算法,Vg可以减少几伏(例如Vg=Vg-2),并且Vd可以继续增加或以不同增加梯度增加,并且被施加于这组的一个或多个单元(见图6B),直到达到所希望的目标阈值电压为止。在每个单元达到目标Vt时,可以将其遮蔽并且可以阻挡其接收任何另外的编程脉冲。当所有的单元都被遮蔽时,对给定组的第二阶段编程可以结束。
现在参见图10B,其中示出了根据本发明另一实施例的第二编程阶段的步骤的流程图。根据图10B所示的算法,并且如图6A的曲线所示的,Vd可以固定在第一阶段编程期间施加于该组的最后Vd上,或者Vd可以相对于那个电压而改变,并且Vg基本上减小。然后可以在脉冲之间增加Vg(例如Vg=Vg+200mV),直到这组中的单元已经达到相关目标阈值电压电平为止,之后结束用于这个阶段的第二阶段编程,并且对第二组的第二阶段编程可以开始。
尽管这里已经说明和介绍了本发明的某些特征,但是本领域的普通技术人员现在将可以想到很多修改、替换、改变和等价物。因此,应该理解,所附权利要求书趋于覆盖落入本发明的实质内的所有这种修改和变化。
Claims (33)
1、一种对非易失性存储器(“NVM”)单元的阵列进行编程的多阶段方法,所述方法包括:
向第一组NVM单元施加第一阶段编程脉冲;并且
在该第一组单元中的一个或多个NVM单元达到或超过第一中间阈值电压电平之后,向该第一组单元中的一个或多个单元的端子施加第二阶段编程脉冲,该第二阶段编程脉冲适于在具有较少储存电荷的单元中比在具有相对更多储存电荷的单元引起相对更大的阈值电压变化。
2、根据权利要求1的方法,其中向所述第一组单元中的一个或多个NVM单元施加第一阶段编程脉冲包括向所述第一组NVM单元中的一个或多个NVM单元的端子施加递增的编程脉冲,其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致;并且
其中施加第二阶段编程脉冲包括向所述一个或多个单元的端子施加基本固定电压的编程脉冲,其与递增电压的栅极脉冲相一致。
3、根据权利要求2的方法,其中重复进行向所述第一组中的一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲,其与递增电压的栅极脉冲相一致,直到所述第一组中的一个或多个单元达到第一目标阈值电压电平为止。
4、根据权利要求3的方法,其中所述基本固定电压的第二阶段编程脉冲处于与第一次成功地使所述第一组中的一个或多个单元的阈值电压升高到或超过该第一中间阈值电压的编程脉冲的电压相对应的电压。
5、根据权利要求3的方法,其中所述第二阶段栅极脉冲的初始值处于与第一次成功地使所述第一组的一个或多个单元的阈值电压升高到或超过该第一中间阈值电压的编程脉冲的栅极电压相对应的电压。
6、根据权利要求4的方法,其中该NVM单元是多电平单元。
7、根据权利要求6的方法,还包括向将要被编程到第二目标阈值电压的第二组NVM单元的一个或多个NVM单元的端子施加递增电压的第一阶段编程脉冲,其与施加于所述第二组的所述NVM单元中的每个单元的栅极的基本固定电压的脉冲相一致,其中施加于该第二组的一个或多个NVM单元的端子的所述第一编程脉冲具有与第一次成功地使所述第一组中的单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的电压相对应的电压。
8、根据权利要求7的方法,还包括:在所述第二组中的一个或多个NVM单元达到或超过第二中间阈值电压之后,向所述第二组的一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲,其与递增电压的栅极脉冲相一致。
9、根据权利要求8的方法,其中重复进行向所述第二组中的一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲,其与递增电压的栅极脉冲相一致,直到所述第二组的所述单元达到该第二目标阈值电压为止。
10、根据权利要求1的方法,其中第一阶段编程包括向第一组NVM单元的一个或多个NVM单元的端子施加递增的编程脉冲,其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致;和
其中向所述第一组中的一个或多个单元施加第二阶段编程脉冲包括向该一个或多个单元的端子施加递增电压的编程脉冲,其与相对减少且基本固定电压的栅极脉冲相一致。
11、根据权利要求10的方法,其中向第一组的一个或多个单元的端子施加递增电压的编程脉冲重复进行,直到所述第一组的该一个或多个单元都达到第一目标阈值电压为止。
12、根据权利要求11的方法,其中该NVM单元是多电平单元。
13、根据权利要求12的方法,还包括向将要被编程到第二目标阈值电压的第二组NVM单元的一个或多个NVM单元的端子施加递增电压的第一阶段编程脉冲,其与施加于该第二组的一个或多个单元的栅极的基本固定电压的脉冲相一致,其中施加于该第二组的该一个或多个NVM单元的端子的所述第一阶段编程脉冲具有与第一次成功地使所述第一组的一个或多个单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的电压相对应的电压。
14、根据权利要求1的方法,其中所述NVM单元选自氮化物只读存储器(“NROM”)、多电平单元(“MLC”)、双电荷捕获区NROM、和双电荷捕获区MLC NROM构成的组。
15、一种编程非易失性存储器(“NVM”)单元的阵列的多阶段方法,所述方法包括:
向第一组NVM单元施加第一阶段编程脉冲;和
在该第一组单元的一个或多个NVM单元达到或超过第一中间阈值电压电平之后,向所述第一组单元施加第二阶段编程脉冲,该第二阶段编程脉冲具有的特性使得在接收基本相同数量的第二阶段编程脉冲之后,所述第一组单元中的基本上所有单元都基本上达到了目标阈值电压。
16、根据权利要求15的方法,其中向所述第一组单元的一个或多个NVM单元施加第一阶段编程脉冲包括向所述第一组NVM单元的一个或多个NVM单元的端子施加递增的编程脉冲,其与施加于所述一个或多个NVM单元的栅极的基本固定电压的脉冲相一致;和
其中施加第二阶段编程脉冲包括向所述一个或多个单元的端子施加基本固定电压的编程脉冲,其与递增电压的栅极脉冲相一致。
17、根据权利要求16的方法,其中重复进行向所述第一组的所述一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲,其与递增电压的栅极脉冲相一致,直到所述第一组的一个或多个单元达到第一目标阈值电压电平为止。
18、根据权利要求17的方法,其中基本固定电压的所述第二阶段编程脉冲处于与第一次成功地使所述第一组的一个或多个单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的电压相对应的电压。
19、根据权利要求17的方法,其中所述第二阶段栅极脉冲的初始值处于与第一次成功地使所述第一组的一个或多个单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的栅极电压相对应的电压。
20、根据权利要求18的方法,其中所述NVM单元是多电平单元。
21、根据权利要求20的方法,还包括向将要被编程到第二目标阈值电压的第二组NVM单元的一个或多个NVM单元的端子施加递增电压的第一阶段编程脉冲,其与施加于所述第二组的所述NVM单元中的每一个的栅极的基本固定电压的脉冲相一致,其中施加于该第二组的该一个或多个NVM单元的端子的第一编程脉冲具有与第一次成功地使所述第一组的单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的电压相对应的电压。
22、根据权利要求21的方法,还包括:在所述第二组的一个或多个NVM单元达到或超过第二中间阈值电压之后,向该第二组的一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲,其与递增电压的栅极脉冲相一致。
23、根据权利要求22的方法,其中重复进行向所述第二组的一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲,其与递增电压的栅极脉冲相一致,直到所述第二组的所述单元达到所述第二目标阈值电压为止。
24、根据权利要求15的方法,其中第一阶段编程包括向第一组NVM单元的一个或多个NVM单元的端子施加递增的编程脉冲,其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致:和
其中向所述第一组的一个或多个单元施加第二阶段编程脉冲包括向所述一个或多个单元的端子施加递增电压的编程脉冲,其与相对减少且基本固定电压的栅极脉冲相一致。
25、根据权利要求24的方法,其中向第一组的一个或多个单元的端子施加递增电压的编程脉冲重复进行,直到所述第一组的所述一个或多个单元都达到第一目标阈值电压为止。
26、根据权利要求25的方法,其中该NVM单元是多电平单元。
27、根据权利要求26的方法,还包括向将要被编程到第二目标阈值电压的第二组NVM单元的一个或多个NVM单元的端子施加递增电压的第一阶段编程脉冲,其与施加于所述第二组的一个或多个单元的栅极的基本固定电压的脉冲相一致,其中施加于所述第二组中的一个或多个NVM单元的端子的第一阶段编程脉冲具有与第一次成功地使所述第一组的一个或多个单元的阈值电压升高到或超过所述第一中间阈值电压的编程脉冲的电压相对应的电压。
28、根据权利要求15的方法,其中所述NVM单元选自氮化物只读存储器(“NROM”)、多电平单元(“MLC”)、双电荷捕获区NROM、和双电荷捕获区MLC NROM构成的组。
29、一种用于编程非易失性存储器(“NVM”)单元的阵列的系统,所述系统包括:
控制器,适于使电荷电路产生第一阶段编程脉冲和确定接收该第一阶段编程脉冲的第一组单元的一个或多个NVM单元何时达到或超过第一中间电压,然后使所述电荷泵电路向该第一组中的一个或多个单元的端子施加第二阶段编程脉冲,所述第二阶段编程脉冲适于在具有较少储存电荷的单元中比在具有相对更多储存电荷的单元中引起相对更大的阈值电压变化。
30、根据权利要求29的系统,其中所述控制器适于使所述电荷泵电路初始向所述第一组NVM单元的一个或多个NVM单元的端子施加具有递增电压电平的第一阶段编程脉冲,其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致,并且一旦一个或多个单元的阈值电压达到或超过中间阈值电压电平,则所述控制器适于使所述电荷泵电路向一个或多个单元的端子施加基本固定电压的第二阶段编程脉冲,其与递增电压的栅极脉冲相一致。
31、根据权利要求30的系统,其中所述控制器适于使所述电荷泵电路初始向所述第一组NVM单元的一个或多个NVM单元的端子施加递增电压的第一阶段编程脉冲,其与施加于该一个或多个NVM单元的栅极的基本固定电压的脉冲相一致,并且一旦一个或多个单元的阈值电压达到或超过中间阈值电压电平,则所述控制器适于使所述电荷泵电路向一个或多个单元的端子施加递增电压的第二阶段编程脉冲,其与基本固定且减少电压的栅极脉冲相一致。
32、一种编程非易失性存储器(“NVM”)单元的阵列的多阶段方法,所述方法包括:
向第一组NVM单元施加第一阶段编程脉冲;和
在该第一组单元的一个或多个NVM单元达到或超过第一中间阈值电压电平之后,向所述第一组单元的一个或多个单元的端子施加第二阶段编程脉冲,该第二阶段编程脉冲适于对第一组中的所有单元引起确定较低的编程速度。
33、一种用于编程非易失性存储器(“NVM”)单元的阵列的系统,所述系统包括:
控制器,适于使电荷电路产生第一阶段编程脉冲和确定接收该第一阶段编程脉冲的第一组单元的一个或多个NVM单元何时达到或超过第一中间电压,然后使所述电荷电路向所述第一组中的一个或多个单元的端子施加第二阶段编程脉冲,所述第二阶段编程脉冲适于引起确定减少的编程速度。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/695,449 US7136304B2 (en) | 2002-10-29 | 2003-10-29 | Method, system and circuit for programming a non-volatile memory array |
US10/695,449 | 2003-10-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN1902711A true CN1902711A (zh) | 2007-01-24 |
Family
ID=34522797
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2004800394008A Pending CN1902711A (zh) | 2003-10-29 | 2004-10-27 | 用于对非易失性存储器阵列编程的方法、系统和电路 |
Country Status (6)
Country | Link |
---|---|
US (2) | US7136304B2 (zh) |
EP (1) | EP1683159A4 (zh) |
JP (1) | JP2007510252A (zh) |
CN (1) | CN1902711A (zh) |
TW (1) | TWI371755B (zh) |
WO (1) | WO2005041206A2 (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101620888A (zh) * | 2008-07-03 | 2010-01-06 | 旺宏电子股份有限公司 | 多位阶单元存储器的读取方法及应用其的读取电路 |
CN102203874A (zh) * | 2008-10-24 | 2011-09-28 | 桑迪士克股份有限公司 | 以高分辨率可变初始编程脉冲对非易失性存储器编程 |
CN102483953A (zh) * | 2009-06-26 | 2012-05-30 | 桑迪士克技术有限公司 | 检测对非易失性储存器的编程的完成 |
CN103310839A (zh) * | 2012-03-15 | 2013-09-18 | 旺宏电子股份有限公司 | 缩短擦除操作的方法与装置 |
CN103928042A (zh) * | 2013-01-16 | 2014-07-16 | 旺宏电子股份有限公司 | 一种操作多位存储单元的方法 |
CN105989879A (zh) * | 2015-02-06 | 2016-10-05 | 华邦电子股份有限公司 | 高可靠性非易失性半导体存储装置及其数据抹除方法 |
Families Citing this family (101)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4170952B2 (ja) * | 2004-01-30 | 2008-10-22 | 株式会社東芝 | 半導体記憶装置 |
US7652930B2 (en) * | 2004-04-01 | 2010-01-26 | Saifun Semiconductors Ltd. | Method, circuit and system for erasing one or more non-volatile memory cells |
JP4167640B2 (ja) * | 2004-10-14 | 2008-10-15 | シャープ株式会社 | 不揮発性メモリのプログラム電圧決定方法 |
US7130210B2 (en) * | 2005-01-13 | 2006-10-31 | Spansion Llc | Multi-level ONO flash program algorithm for threshold width control |
US7339826B2 (en) * | 2005-04-11 | 2008-03-04 | Saifun Semiconductors Ltd. | Threshold voltage shift in NROM cells |
ITVA20050024A1 (it) * | 2005-04-13 | 2006-10-14 | St Microelectronics Srl | Metodo e circuito di programmazione simultanea di celle di memoria |
KR100719368B1 (ko) * | 2005-06-27 | 2007-05-17 | 삼성전자주식회사 | 플래시 메모리 장치의 적응적 프로그램 방법 및 장치 |
US7656710B1 (en) | 2005-07-14 | 2010-02-02 | Sau Ching Wong | Adaptive operations for nonvolatile memories |
JP4638544B2 (ja) * | 2005-12-29 | 2011-02-23 | サンディスク コーポレイション | 不揮発性メモリにおける改善されたプログラムベリファイ操作のための方法および装置 |
KR100683858B1 (ko) * | 2006-01-12 | 2007-02-15 | 삼성전자주식회사 | 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리의 프로그램 방법 |
KR100683856B1 (ko) * | 2006-01-12 | 2007-02-15 | 삼성전자주식회사 | 고온 스트레스로 인한 읽기 마진의 감소를 보상할 수 있는플래시 메모리의 프로그램 방법 |
US7426137B2 (en) * | 2006-04-12 | 2008-09-16 | Sandisk Corporation | Apparatus for reducing the impact of program disturb during read |
US7436713B2 (en) * | 2006-04-12 | 2008-10-14 | Sandisk Corporation | Reducing the impact of program disturb |
US7499326B2 (en) * | 2006-04-12 | 2009-03-03 | Sandisk Corporation | Apparatus for reducing the impact of program disturb |
US7515463B2 (en) * | 2006-04-12 | 2009-04-07 | Sandisk Corporation | Reducing the impact of program disturb during read |
WO2007132456A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Memory device with adaptive capacity |
KR101202537B1 (ko) | 2006-05-12 | 2012-11-19 | 애플 인크. | 메모리 디바이스를 위한 결합된 왜곡 추정 및 에러 보정 코딩 |
CN103280239B (zh) * | 2006-05-12 | 2016-04-06 | 苹果公司 | 存储设备中的失真估计和消除 |
WO2008026203A2 (en) | 2006-08-27 | 2008-03-06 | Anobit Technologies | Estimation of non-linear distortion in memory devices |
WO2008032326A2 (en) * | 2006-09-12 | 2008-03-20 | Saifun Semiconductors Ltd. | Methods, circuits and systems for reading non-volatile memory cells |
WO2008045805A1 (en) * | 2006-10-10 | 2008-04-17 | Sandisk Corporation | Variable program voltage increment values in non-volatile memory program operations |
US7450426B2 (en) | 2006-10-10 | 2008-11-11 | Sandisk Corporation | Systems utilizing variable program voltage increment values in non-volatile memory program operations |
US7474561B2 (en) | 2006-10-10 | 2009-01-06 | Sandisk Corporation | Variable program voltage increment values in non-volatile memory program operations |
WO2008053472A2 (en) | 2006-10-30 | 2008-05-08 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US8151163B2 (en) | 2006-12-03 | 2012-04-03 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
US7397705B1 (en) * | 2007-02-01 | 2008-07-08 | Macronix International Co., Ltd. | Method for programming multi-level cell memory array |
KR101147522B1 (ko) * | 2007-02-20 | 2012-05-21 | 샌디스크 테크놀로지스, 인코포레이티드 | 임계전압 분포에 기반한 동적 검증 |
US20080205140A1 (en) * | 2007-02-26 | 2008-08-28 | Aplus Flash Technology, Inc. | Bit line structure for a multilevel, dual-sided nonvolatile memory cell array |
CN101715595A (zh) | 2007-03-12 | 2010-05-26 | 爱诺彼得技术有限责任公司 | 存储器单元读取阈的自适应估计 |
US7830713B2 (en) * | 2007-03-14 | 2010-11-09 | Aplus Flash Technology, Inc. | Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array |
US7447068B2 (en) * | 2007-03-19 | 2008-11-04 | Macronix International Co., Ltd. | Method for programming a multilevel memory |
ITRM20070167A1 (it) * | 2007-03-27 | 2008-09-29 | Micron Technology Inc | Non-volatile multilevel memory cell programming |
US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
WO2008139441A2 (en) | 2007-05-12 | 2008-11-20 | Anobit Technologies Ltd. | Memory device with internal signal processing unit |
US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
US7978520B2 (en) | 2007-09-27 | 2011-07-12 | Sandisk Corporation | Compensation of non-volatile memory chip non-idealities by program pulse adjustment |
WO2009050703A2 (en) | 2007-10-19 | 2009-04-23 | Anobit Technologies | Data storage in analog memory cell arrays having erase failures |
US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
US8000141B1 (en) * | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
WO2009063450A2 (en) | 2007-11-13 | 2009-05-22 | Anobit Technologies | Optimized selection of memory units in multi-unit memory devices |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
KR101448851B1 (ko) * | 2008-02-26 | 2014-10-13 | 삼성전자주식회사 | 비휘발성 메모리 장치에서의 프로그래밍 방법 |
US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
CN102089827B (zh) * | 2008-06-12 | 2017-05-17 | 桑迪士克科技有限责任公司 | 非易失性存储器和关联多遍编程的方法 |
US8498151B1 (en) | 2008-08-05 | 2013-07-30 | Apple Inc. | Data storage in analog memory cells using modified pass voltages |
US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
KR101468100B1 (ko) * | 2008-09-23 | 2014-12-04 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 페이지 버퍼 |
US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
US8261159B1 (en) | 2008-10-30 | 2012-09-04 | Apple, Inc. | Data scrambling schemes for memory devices |
US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
US7821840B2 (en) * | 2008-11-24 | 2010-10-26 | Spansion Llc | Multi-phase programming of multi-level memory |
US8397131B1 (en) | 2008-12-31 | 2013-03-12 | Apple Inc. | Efficient readout schemes for analog memory cell devices |
US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
KR101005117B1 (ko) * | 2009-01-23 | 2011-01-04 | 주식회사 하이닉스반도체 | 불휘발성 메모리 장치의 동작 방법 |
US8223551B2 (en) * | 2009-02-19 | 2012-07-17 | Micron Technology, Inc. | Soft landing for desired program threshold voltage |
US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
US8223556B2 (en) * | 2009-11-25 | 2012-07-17 | Sandisk Technologies Inc. | Programming non-volatile memory with a reduced number of verify operations |
US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
US8677203B1 (en) | 2010-01-11 | 2014-03-18 | Apple Inc. | Redundant data storage schemes for multi-die memory systems |
US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
US8471328B2 (en) | 2010-07-26 | 2013-06-25 | United Microelectronics Corp. | Non-volatile memory and manufacturing method thereof |
US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
KR101143472B1 (ko) | 2010-07-28 | 2012-05-08 | 에스케이하이닉스 주식회사 | 반도체 장치 및 제어전압 전달방법 |
US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
US8797802B2 (en) * | 2012-03-15 | 2014-08-05 | Macronix International Co., Ltd. | Method and apparatus for shortened erase operation |
US8824214B2 (en) | 2012-12-10 | 2014-09-02 | Apple Inc. | Inter-word-line programming in arrays of analog memory cells |
US8837214B2 (en) | 2012-12-10 | 2014-09-16 | Apple Inc. | Applications for inter-word-line programming |
US8908445B2 (en) | 2013-03-15 | 2014-12-09 | Freescale Semiconductor, Inc. | Non-volatile memory (NVM) with block-size-aware program/erase |
JP5669903B2 (ja) * | 2013-09-05 | 2015-02-18 | ラピスセミコンダクタ株式会社 | 半導体不揮発性メモリ、半導体不揮発性メモリの電荷蓄積方法、及び電荷蓄積プログラム |
KR102452994B1 (ko) * | 2016-09-06 | 2022-10-12 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그 동작 방법 |
US10381094B2 (en) | 2016-10-11 | 2019-08-13 | Macronix International Co., Ltd. | 3D memory with staged-level multibit programming |
US10146460B1 (en) | 2017-06-01 | 2018-12-04 | Apple Inc. | Programming schemes for avoidance or recovery from cross-temperature read failures |
EP3454318B1 (en) | 2017-09-12 | 2022-05-11 | eMemory Technology Inc. | Security system with entropy bits generated by a puf |
US11244734B2 (en) * | 2019-12-27 | 2022-02-08 | Sandisk Technologies Llc | Modified verify scheme for programming a memory apparatus |
US11837299B2 (en) | 2021-04-13 | 2023-12-05 | Jmem Technology Co., Ltd | Operation method of multi-bits read only memory |
TWI747784B (zh) * | 2021-04-28 | 2021-11-21 | 國立陽明交通大學 | 多位元唯讀記憶體的操作方法 |
US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Family Cites Families (568)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US604099A (en) | 1898-05-17 | Wire-fence-weaving machine | ||
GB1297899A (zh) | 1970-10-02 | 1972-11-29 | ||
GB1392599A (en) | 1971-07-28 | 1975-04-30 | Mullard Ltd | Semiconductor memory elements |
US3881180A (en) | 1971-11-30 | 1975-04-29 | Texas Instruments Inc | Non-volatile memory cell |
US3895360A (en) | 1974-01-29 | 1975-07-15 | Westinghouse Electric Corp | Block oriented random access memory |
US4016588A (en) | 1974-12-27 | 1977-04-05 | Nippon Electric Company, Ltd. | Non-volatile semiconductor memory device |
US4017888A (en) | 1975-12-31 | 1977-04-12 | International Business Machines Corporation | Non-volatile metal nitride oxide semiconductor device |
US4151021A (en) | 1977-01-26 | 1979-04-24 | Texas Instruments Incorporated | Method of making a high density floating gate electrically programmable ROM |
US4145703A (en) | 1977-04-15 | 1979-03-20 | Supertex, Inc. | High power MOS device and fabrication method therefor |
US4173766A (en) | 1977-09-16 | 1979-11-06 | Fairchild Camera And Instrument Corporation | Insulated gate field-effect transistor read-only memory cell |
US4173791A (en) | 1977-09-16 | 1979-11-06 | Fairchild Camera And Instrument Corporation | Insulated gate field-effect transistor read-only memory array |
US4373248A (en) | 1978-07-12 | 1983-02-15 | Texas Instruments Incorporated | Method of making high density semiconductor device such as floating gate electrically programmable ROM or the like |
DE2832388C2 (de) | 1978-07-24 | 1986-08-14 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zum Herstellen von MNOS- und MOS-Transistoren in Silizium-Gate-Technologie auf einem Halbleitersubstrat |
US4360900A (en) | 1978-11-27 | 1982-11-23 | Texas Instruments Incorporated | Non-volatile semiconductor memory elements |
US4247861A (en) | 1979-03-09 | 1981-01-27 | Rca Corporation | High performance electrically alterable read-only memory (EAROM) |
DE2923995C2 (de) | 1979-06-13 | 1985-11-07 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum Herstellen von integrierten MOS-Schaltungen mit MOS-Transistoren und MNOS-Speichertransistoren in Silizium-Gate-Technologie |
JPS5656677A (en) | 1979-10-13 | 1981-05-18 | Toshiba Corp | Semiconductor memory device |
US4281397A (en) | 1979-10-29 | 1981-07-28 | Texas Instruments Incorporated | Virtual ground MOS EPROM or ROM matrix |
DE2947350A1 (de) | 1979-11-23 | 1981-05-27 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von mnos-speichertransistoren mit sehr kurzer kanallaenge in silizium-gate-technologie |
JPS56120166A (en) | 1980-02-27 | 1981-09-21 | Hitachi Ltd | Semiconductor ic device and manufacture thereof |
US4342102A (en) | 1980-06-18 | 1982-07-27 | Signetics Corporation | Semiconductor memory array |
US4380057A (en) | 1980-10-27 | 1983-04-12 | International Business Machines Corporation | Electrically alterable double dense memory |
US4521796A (en) | 1980-12-11 | 1985-06-04 | General Instrument Corporation | Memory implant profile for improved channel shielding in electrically alterable read only memory semiconductor device |
DE3174858D1 (en) | 1980-12-25 | 1986-07-24 | Fujitsu Ltd | Nonvolatile semiconductor memory device |
US4448400A (en) | 1981-07-13 | 1984-05-15 | Eliyahou Harari | Highly scalable dynamic RAM cell with self-signal amplification |
US4404747A (en) | 1981-07-29 | 1983-09-20 | Schur, Inc. | Knife and sheath assembly |
US4389705A (en) | 1981-08-21 | 1983-06-21 | Mostek Corporation | Semiconductor memory circuit with depletion data transfer transistor |
US4388705A (en) | 1981-10-01 | 1983-06-14 | Mostek Corporation | Semiconductor memory circuit |
US4435786A (en) | 1981-11-23 | 1984-03-06 | Fairchild Camera And Instrument Corporation | Self-refreshing memory cell |
US4494016A (en) | 1982-07-26 | 1985-01-15 | Sperry Corporation | High performance MESFET transistor for VLSI implementation |
US4527257A (en) | 1982-08-25 | 1985-07-02 | Westinghouse Electric Corp. | Common memory gate non-volatile transistor memory |
JPS5949022A (ja) | 1982-09-13 | 1984-03-21 | Toshiba Corp | 多値論理回路 |
US4613956A (en) | 1983-02-23 | 1986-09-23 | Texas Instruments Incorporated | Floating gate memory with improved dielectric |
US4769340A (en) | 1983-11-28 | 1988-09-06 | Exel Microelectronics, Inc. | Method for making electrically programmable memory device by doping the floating gate by implant |
US4725984A (en) | 1984-02-21 | 1988-02-16 | Seeq Technology, Inc. | CMOS eprom sense amplifier |
JPS60182174A (ja) | 1984-02-28 | 1985-09-17 | Nec Corp | 不揮発性半導体メモリ |
GB2157489A (en) | 1984-03-23 | 1985-10-23 | Hitachi Ltd | A semiconductor integrated circuit memory device |
US5352620A (en) | 1984-05-23 | 1994-10-04 | Hitachi, Ltd. | Method of making semiconductor device with memory cells and peripheral transistors |
KR930007195B1 (ko) | 1984-05-23 | 1993-07-31 | 가부시끼가이샤 히다찌세이사꾸쇼 | 반도체 장치와 그 제조 방법 |
US4665426A (en) | 1985-02-01 | 1987-05-12 | Advanced Micro Devices, Inc. | EPROM with ultraviolet radiation transparent silicon nitride passivation layer |
DE3684351D1 (de) | 1985-04-18 | 1992-04-23 | Nec Corp | Programmierbarer festwertspeicher mit reduzierter programmierspeisespannung. |
US4667217A (en) | 1985-04-19 | 1987-05-19 | Ncr Corporation | Two bit vertically/horizontally integrated memory cell |
JPH0831789B2 (ja) | 1985-09-04 | 1996-03-27 | 沖電気工業株式会社 | 出力回路 |
US4742491A (en) | 1985-09-26 | 1988-05-03 | Advanced Micro Devices, Inc. | Memory cell having hot-hole injection erase mode |
US4760555A (en) | 1986-04-21 | 1988-07-26 | Texas Instruments Incorporated | Memory array with an array reorganizer |
JPH0828431B2 (ja) | 1986-04-22 | 1996-03-21 | 日本電気株式会社 | 半導体記憶装置 |
US4758869A (en) | 1986-08-29 | 1988-07-19 | Waferscale Integration, Inc. | Nonvolatile floating gate transistor structure |
US5168334A (en) | 1987-07-31 | 1992-12-01 | Texas Instruments, Incorporated | Non-volatile semiconductor memory |
US4780424A (en) | 1987-09-28 | 1988-10-25 | Intel Corporation | Process for fabricating electrically alterable floating gate memory devices |
US4870470A (en) | 1987-10-16 | 1989-09-26 | International Business Machines Corporation | Non-volatile memory cell having Si rich silicon nitride charge trapping layer |
US4839705A (en) | 1987-12-16 | 1989-06-13 | Texas Instruments Incorporated | X-cell EEPROM array |
JPH07120720B2 (ja) | 1987-12-17 | 1995-12-20 | 三菱電機株式会社 | 不揮発性半導体記憶装置 |
US5159570A (en) | 1987-12-22 | 1992-10-27 | Texas Instruments Incorporated | Four memory state EEPROM |
US4888735A (en) | 1987-12-30 | 1989-12-19 | Elite Semiconductor & Systems Int'l., Inc. | ROM cell and array configuration |
US5677867A (en) | 1991-06-12 | 1997-10-14 | Hazani; Emanuel | Memory with isolatable expandable bit lines |
US4857770A (en) | 1988-02-29 | 1989-08-15 | Advanced Micro Devices, Inc. | Output buffer arrangement for reducing chip noise without speed penalty |
US5268870A (en) | 1988-06-08 | 1993-12-07 | Eliyahou Harari | Flash EEPROM system and intelligent programming and erasing methods therefor |
US4941028A (en) | 1988-08-10 | 1990-07-10 | Actel Corporation | Structure for protecting thin dielectrics during processing |
JPH0271493A (ja) | 1988-09-06 | 1990-03-12 | Mitsubishi Electric Corp | 半導体メモリ装置 |
US5042009A (en) | 1988-12-09 | 1991-08-20 | Waferscale Integration, Inc. | Method for programming a floating gate memory device |
US5293563A (en) | 1988-12-29 | 1994-03-08 | Sharp Kabushiki Kaisha | Multi-level memory cell with increased read-out margin |
US5844842A (en) | 1989-02-06 | 1998-12-01 | Hitachi, Ltd. | Nonvolatile semiconductor memory device |
US5120672A (en) | 1989-02-22 | 1992-06-09 | Texas Instruments Incorporated | Fabricating a single level merged EEPROM cell having an ONO memory stack substantially spaced from the source region |
US5142495A (en) | 1989-03-10 | 1992-08-25 | Intel Corporation | Variable load for margin mode |
DE3931596A1 (de) | 1989-03-25 | 1990-10-04 | Eurosil Electronic Gmbh | Spannungsvervielfacherschaltung |
US5172338B1 (en) | 1989-04-13 | 1997-07-08 | Sandisk Corp | Multi-state eeprom read and write circuits and techniques |
DE69033262T2 (de) | 1989-04-13 | 2000-02-24 | Sandisk Corp | EEPROM-Karte mit Austauch von fehlerhaften Speicherzellen und Zwischenspeicher |
US4961010A (en) | 1989-05-19 | 1990-10-02 | National Semiconductor Corporation | Output buffer for reducing switching induced noise |
US5104819A (en) | 1989-08-07 | 1992-04-14 | Intel Corporation | Fabrication of interpoly dielctric for EPROM-related technologies |
US5027321A (en) | 1989-11-21 | 1991-06-25 | Intel Corporation | Apparatus and method for improved reading/programming of virtual ground EPROM arrays |
US4992391A (en) | 1989-11-29 | 1991-02-12 | Advanced Micro Devices, Inc. | Process for fabricating a control gate for a floating gate FET |
KR100199258B1 (ko) | 1990-02-09 | 1999-06-15 | 가나이 쓰도무 | 반도체집적회로장치 |
JP2733796B2 (ja) | 1990-02-13 | 1998-03-30 | セイコーインスツルメンツ株式会社 | スイッチ回路 |
US5204835A (en) | 1990-06-13 | 1993-04-20 | Waferscale Integration Inc. | Eprom virtual ground array |
EP0461904A3 (en) | 1990-06-14 | 1992-09-09 | Creative Integrated Systems, Inc. | An improved semiconductor read-only vlsi memory |
US5075245A (en) | 1990-08-03 | 1991-12-24 | Intel Corporation | Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps |
US5289406A (en) | 1990-08-28 | 1994-02-22 | Mitsubishi Denki Kabushiki Kaisha | Read only memory for storing multi-data |
US5117389A (en) | 1990-09-05 | 1992-05-26 | Macronix International Co., Ltd. | Flat-cell read-only-memory integrated circuit |
KR920006991A (ko) | 1990-09-25 | 1992-04-28 | 김광호 | 반도체메모리 장치의 고전압발생회로 |
US5081371A (en) | 1990-11-07 | 1992-01-14 | U.S. Philips Corp. | Integrated charge pump circuit with back bias voltage reduction |
JP3002309B2 (ja) | 1990-11-13 | 2000-01-24 | ウエハスケール インテグレーション, インコーポレイテッド | 高速epromアレイ |
JP2987193B2 (ja) | 1990-11-20 | 1999-12-06 | 富士通株式会社 | 半導体記憶装置 |
US5094968A (en) | 1990-11-21 | 1992-03-10 | Atmel Corporation | Fabricating a narrow width EEPROM with single diffusion electrode formation |
US5086325A (en) | 1990-11-21 | 1992-02-04 | Atmel Corporation | Narrow width EEPROM with single diffusion electrode formation |
JP2612969B2 (ja) | 1991-02-08 | 1997-05-21 | シャープ株式会社 | 半導体装置の製造方法 |
US5218569A (en) | 1991-02-08 | 1993-06-08 | Banks Gerald J | Electrically alterable non-volatile memory with n-bits per memory cell |
US6002614A (en) | 1991-02-08 | 1999-12-14 | Btg International Inc. | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell |
JPH04311900A (ja) | 1991-04-10 | 1992-11-04 | Sharp Corp | 半導体読み出し専用メモリ |
JP2930440B2 (ja) | 1991-04-15 | 1999-08-03 | 沖電気工業株式会社 | 半導体集積回路 |
US5424567A (en) | 1991-05-15 | 1995-06-13 | North American Philips Corporation | Protected programmable transistor with reduced parasitic capacitances and method of fabrication |
US5142496A (en) | 1991-06-03 | 1992-08-25 | Advanced Micro Devices, Inc. | Method for measuring VT 's less than zero without applying negative voltages |
US5245572A (en) | 1991-07-30 | 1993-09-14 | Intel Corporation | Floating gate nonvolatile memory with reading while writing capability |
JP2965415B2 (ja) | 1991-08-27 | 1999-10-18 | 松下電器産業株式会社 | 半導体記憶装置 |
EP0740854B1 (en) | 1991-08-29 | 2003-04-23 | Hyundai Electronics Industries Co., Ltd. | A self-aligned dual-bit split gate (dsg) flash eeprom cell |
US5305262A (en) | 1991-09-11 | 1994-04-19 | Kawasaki Steel Corporation | Semiconductor integrated circuit |
US5175120A (en) | 1991-10-11 | 1992-12-29 | Micron Technology, Inc. | Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors |
JPH05110114A (ja) | 1991-10-17 | 1993-04-30 | Rohm Co Ltd | 不揮発性半導体記憶素子 |
JP3358663B2 (ja) | 1991-10-25 | 2002-12-24 | ローム株式会社 | 半導体記憶装置およびその記憶情報読出方法 |
US5357134A (en) | 1991-10-31 | 1994-10-18 | Rohm Co., Ltd. | Nonvolatile semiconductor device having charge trap film containing silicon crystal grains |
US5338954A (en) | 1991-10-31 | 1994-08-16 | Rohm Co., Ltd. | Semiconductor memory device having an insulating film and a trap film joined in a channel region |
JPH05129284A (ja) | 1991-11-06 | 1993-05-25 | Sony Corp | プラズマSiN成膜条件の設定方法及び半導体装置の製造方法 |
US5260593A (en) | 1991-12-10 | 1993-11-09 | Micron Technology, Inc. | Semiconductor floating gate device having improved channel-floating gate interaction |
US5490107A (en) | 1991-12-27 | 1996-02-06 | Fujitsu Limited | Nonvolatile semiconductor memory |
JP2564067B2 (ja) | 1992-01-09 | 1996-12-18 | 株式会社東芝 | センス回路を有する読み出し出力回路 |
US6222762B1 (en) | 1992-01-14 | 2001-04-24 | Sandisk Corporation | Multi-state memory |
US5293328A (en) | 1992-01-15 | 1994-03-08 | National Semiconductor Corporation | Electrically reprogrammable EPROM cell with merged transistor and optiumum area |
US5654568A (en) | 1992-01-17 | 1997-08-05 | Rohm Co., Ltd. | Semiconductor device including nonvolatile memories |
JP2851962B2 (ja) | 1992-01-21 | 1999-01-27 | シャープ株式会社 | 半導体読み出し専用メモリ |
EP0552531B1 (en) | 1992-01-22 | 2000-08-16 | Macronix International Co., Ltd. | Non-volatile memory cell and array architecture |
US5324675A (en) | 1992-03-31 | 1994-06-28 | Kawasaki Steel Corporation | Method of producing semiconductor devices of a MONOS type |
JPH05290584A (ja) | 1992-04-08 | 1993-11-05 | Nec Corp | 半導体記憶装置 |
US5557221A (en) | 1992-06-15 | 1996-09-17 | Fujitsu Limited | Semiconductor integrated circuit with input/output interface adapted for small-amplitude operation |
US5657332A (en) | 1992-05-20 | 1997-08-12 | Sandisk Corporation | Soft errors handling in EEPROM devices |
JP2904645B2 (ja) | 1992-05-28 | 1999-06-14 | 株式会社東芝 | 不揮発性半導体メモリ |
US5496753A (en) | 1992-05-29 | 1996-03-05 | Citizen Watch, Co., Ltd. | Method of fabricating a semiconductor nonvolatile storage device |
US5289412A (en) | 1992-06-19 | 1994-02-22 | Intel Corporation | High-speed bias-stabilized current-mirror referencing circuit for non-volatile memories |
JPH065823A (ja) | 1992-06-19 | 1994-01-14 | Toshiba Corp | 不揮発性半導体記憶装置及びその使用方法 |
US5315541A (en) | 1992-07-24 | 1994-05-24 | Sundisk Corporation | Segmented column memory array |
GB9217743D0 (en) | 1992-08-19 | 1992-09-30 | Philips Electronics Uk Ltd | A semiconductor memory device |
JP3036565B2 (ja) | 1992-08-28 | 2000-04-24 | 日本電気株式会社 | 不揮発性半導体記憶装置の製造方法 |
US5450341A (en) | 1992-08-31 | 1995-09-12 | Nippon Steel Corporation | Non-volatile semiconductor memory device having memory cells, each for at least three different data writable thereinto selectively and a method of using the same |
US5412601A (en) | 1992-08-31 | 1995-05-02 | Nippon Steel Corporation | Non-volatile semiconductor memory device capable of storing multi-value data in each memory cell |
US5450354A (en) | 1992-08-31 | 1995-09-12 | Nippon Steel Corporation | Non-volatile semiconductor memory device detachable deterioration of memory cells |
US5412238A (en) | 1992-09-08 | 1995-05-02 | National Semiconductor Corporation | Source-coupling, split-gate, virtual ground flash EEPROM array |
US5280420A (en) | 1992-10-02 | 1994-01-18 | National Semiconductor Corporation | Charge pump which operates on a low voltage power supply |
US5579199A (en) | 1992-11-26 | 1996-11-26 | Sharp Kabushiki Kaisha | Non-volatile memory device and a method for producing the same |
US5377153A (en) | 1992-11-30 | 1994-12-27 | Sgs-Thomson Microelectronics, Inc. | Virtual ground read only memory circuit |
US5418743A (en) | 1992-12-07 | 1995-05-23 | Nippon Steel Corporation | Method of writing into non-volatile semiconductor memory |
US5319593A (en) | 1992-12-21 | 1994-06-07 | National Semiconductor Corp. | Memory array with field oxide islands eliminated and method |
JPH07114792A (ja) | 1993-10-19 | 1995-05-02 | Mitsubishi Electric Corp | 半導体記憶装置 |
US5436481A (en) | 1993-01-21 | 1995-07-25 | Nippon Steel Corporation | MOS-type semiconductor device and method of making the same |
WO1994018703A1 (en) | 1993-02-01 | 1994-08-18 | National Semiconductor Corporation | Ultra-high-density alternate metal virtual ground rom |
US5424978A (en) | 1993-03-15 | 1995-06-13 | Nippon Steel Corporation | Non-volatile semiconductor memory cell capable of storing more than two different data and method of using the same |
DE69311091T2 (de) | 1993-03-25 | 1998-01-08 | Charlatte | Luftkontrollsystem für hydropneumatischen Behälter |
US5393701A (en) | 1993-04-08 | 1995-02-28 | United Microelectronics Corporation | Layout design to eliminate process antenna effect |
DE9305576U1 (zh) | 1993-04-14 | 1993-07-08 | Holzrichter, Dieter, Dr.Med., 2000 Hamburg, De | |
JP3317459B2 (ja) | 1993-04-30 | 2002-08-26 | ローム株式会社 | 不揮発性記憶素子およびこれを利用した不揮発性記憶装置、この記憶装置の駆動方法、ならびにこの記憶素子の製造方法 |
US5335198A (en) | 1993-05-06 | 1994-08-02 | Advanced Micro Devices, Inc. | Flash EEPROM array with high endurance |
US5463586A (en) | 1993-05-28 | 1995-10-31 | Macronix International Co., Ltd. | Erase and program verification circuit for non-volatile memory |
JP3156447B2 (ja) | 1993-06-17 | 2001-04-16 | 富士通株式会社 | 半導体集積回路 |
EP0631369A1 (en) | 1993-06-21 | 1994-12-28 | STMicroelectronics S.r.l. | Voltage multiplier for high output current with a stabilized output voltage |
US5350710A (en) | 1993-06-24 | 1994-09-27 | United Microelectronics Corporation | Device for preventing antenna effect on circuit |
US5400286A (en) | 1993-08-17 | 1995-03-21 | Catalyst Semiconductor Corp. | Self-recovering erase scheme to enhance flash memory endurance |
JP3463030B2 (ja) | 1993-08-27 | 2003-11-05 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US5563823A (en) | 1993-08-31 | 1996-10-08 | Macronix International Co., Ltd. | Fast FLASH EPROM programming and pre-programming circuit design |
US5553030A (en) | 1993-09-10 | 1996-09-03 | Intel Corporation | Method and apparatus for controlling the output voltage provided by a charge pump circuit |
US5477499A (en) | 1993-10-13 | 1995-12-19 | Advanced Micro Devices, Inc. | Memory architecture for a three volt flash EEPROM |
US5828601A (en) | 1993-12-01 | 1998-10-27 | Advanced Micro Devices, Inc. | Programmed reference |
JP3076185B2 (ja) | 1993-12-07 | 2000-08-14 | 日本電気株式会社 | 半導体メモリ装置及びその検査方法 |
US5440505A (en) | 1994-01-21 | 1995-08-08 | Intel Corporation | Method and circuitry for storing discrete amounts of charge in a single memory element |
FR2715758B1 (fr) | 1994-01-31 | 1996-03-22 | Sgs Thomson Microelectronics | Bascule bistable non volatile programmable par la source, notamment pour circuit de redondance de mémoire. |
FR2715782B1 (fr) | 1994-01-31 | 1996-03-22 | Sgs Thomson Microelectronics | Bascule bistable non volatile programmable, à état initial prédéfini, notamment pour circuit de redondance de mémoire. |
JP3397427B2 (ja) | 1994-02-02 | 2003-04-14 | 株式会社東芝 | 半導体記憶装置 |
US6005423A (en) | 1994-02-10 | 1999-12-21 | Xilinx, Inc. | Low current power-on reset circuit |
US5418176A (en) | 1994-02-17 | 1995-05-23 | United Microelectronics Corporation | Process for producing memory devices having narrow buried N+ lines |
DE69530527T2 (de) | 1994-03-03 | 2004-04-08 | Rohm Corp., San Jose | Niederspannungs-Eintransistor-FLASH-EEPROM-Zelle mit Fowler-Nordheim Programmier- und Löschung |
US5436478A (en) | 1994-03-16 | 1995-07-25 | National Semiconductor Corporation | Fast access AMG EPROM with segment select transistors which have an increased width |
DE69424771T2 (de) | 1994-03-22 | 2000-10-26 | St Microelectronics Srl | Anordnung zum Lesen einer Speicherzellenmatrix |
US5467308A (en) | 1994-04-05 | 1995-11-14 | Motorola Inc. | Cross-point eeprom memory array |
US5530803A (en) | 1994-04-14 | 1996-06-25 | Advanced Micro Devices, Inc. | Method and apparatus for programming memory devices |
US5568085A (en) | 1994-05-16 | 1996-10-22 | Waferscale Integration Inc. | Unit for stabilizing voltage on a capacitive node |
TW241394B (en) | 1994-05-26 | 1995-02-21 | Aplus Integrated Circuits Inc | Flat-cell ROM and decoder |
US5608679A (en) * | 1994-06-02 | 1997-03-04 | Intel Corporation | Fast internal reference cell trimming for flash EEPROM memory |
JP3725911B2 (ja) | 1994-06-02 | 2005-12-14 | 株式会社ルネサステクノロジ | 半導体装置 |
US5523972A (en) | 1994-06-02 | 1996-06-04 | Intel Corporation | Method and apparatus for verifying the programming of multi-level flash EEPROM memory |
EP0691729A3 (en) | 1994-06-30 | 1996-08-14 | Sgs Thomson Microelectronics | Charge pump circuit with feedback control |
EP0693781B1 (en) | 1994-07-13 | 2002-10-02 | United Microelectronics Corporation | Grounding method for eliminating process antenna effect |
EP0696050B1 (en) | 1994-07-18 | 1998-10-14 | STMicroelectronics S.r.l. | EPROM and Flash-EEPROM non-volatile memory and method of manufacturing the same |
US5508968A (en) | 1994-08-12 | 1996-04-16 | International Business Machines Corporation | Dynamic random access memory persistent page implemented as processor register sets |
US5822256A (en) | 1994-09-06 | 1998-10-13 | Intel Corporation | Method and circuitry for usage of partially functional nonvolatile memory |
JPH08181284A (ja) | 1994-09-13 | 1996-07-12 | Hewlett Packard Co <Hp> | 保護素子およびその製造方法 |
US5583808A (en) | 1994-09-16 | 1996-12-10 | National Semiconductor Corporation | EPROM array segmented for high performance and method for controlling same |
JP3730272B2 (ja) | 1994-09-17 | 2005-12-21 | 株式会社東芝 | 不揮発性半導体記憶装置 |
DE4434725C1 (de) | 1994-09-28 | 1996-05-30 | Siemens Ag | Festwert-Speicherzellenanordnung und Verfahren zu deren Herstellung |
US5619052A (en) | 1994-09-29 | 1997-04-08 | Macronix International Co., Ltd. | Interpoly dielectric structure in EEPROM device |
US5523251A (en) | 1994-10-05 | 1996-06-04 | United Microelectronics Corp. | Method for fabricating a self aligned mask ROM |
US5612642A (en) | 1995-04-28 | 1997-03-18 | Altera Corporation | Power-on reset circuit with hysteresis |
US5581252A (en) | 1994-10-13 | 1996-12-03 | Linear Technology Corporation | Analog-to-digital conversion using comparator coupled capacitor digital-to-analog converters |
JPH08124395A (ja) | 1994-10-25 | 1996-05-17 | Nkk Corp | メモリ装置 |
US5694356A (en) | 1994-11-02 | 1997-12-02 | Invoice Technology, Inc. | High resolution analog storage EPROM and flash EPROM |
US5537358A (en) | 1994-12-06 | 1996-07-16 | National Semiconductor Corporation | Flash memory having adaptive sensing and method |
US5599727A (en) | 1994-12-15 | 1997-02-04 | Sharp Kabushiki Kaisha | Method for producing a floating gate memory device including implanting ions through an oxidized portion of the silicon film from which the floating gate is formed |
US5661060A (en) | 1994-12-28 | 1997-08-26 | National Semiconductor Corporation | Method for forming field oxide regions |
US5534804A (en) | 1995-02-13 | 1996-07-09 | Advanced Micro Devices, Inc. | CMOS power-on reset circuit using hysteresis |
DE19505293A1 (de) | 1995-02-16 | 1996-08-22 | Siemens Ag | Mehrwertige Festwertspeicherzelle mit verbessertem Störabstand |
CA2142644C (en) | 1995-02-16 | 1996-11-26 | Marc Etienne Bonneville | Standby power circuit arrangement |
US5801076A (en) | 1995-02-21 | 1998-09-01 | Advanced Micro Devices, Inc. | Method of making non-volatile memory device having a floating gate with enhanced charge retention |
US5518942A (en) | 1995-02-22 | 1996-05-21 | Alliance Semiconductor Corporation | Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant |
US6353554B1 (en) | 1995-02-27 | 2002-03-05 | Btg International Inc. | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell |
US5666365A (en) | 1995-03-16 | 1997-09-09 | Bell Atlantic Network Services, Inc. | Simulcast transmission of digital programs to shared antenna receiving systems |
US5617357A (en) | 1995-04-07 | 1997-04-01 | Advanced Micro Devices, Inc. | Flash EEPROM memory with improved discharge speed using substrate bias and method therefor |
EP0740307B1 (en) | 1995-04-28 | 2001-12-12 | STMicroelectronics S.r.l. | Sense amplifier circuit for semiconductor memory devices |
KR100187656B1 (ko) | 1995-05-16 | 1999-06-01 | 김주용 | 플래쉬 이이피롬 셀의 제조방법 및 그 프로그램 방법 |
US5656513A (en) | 1995-06-07 | 1997-08-12 | Advanced Micro Devices, Inc. | Nonvolatile memory cell formed using self aligned source implant |
WO1996041346A1 (en) | 1995-06-07 | 1996-12-19 | Macronix International Co., Ltd. | Automatic programming algorithm for page mode flash memory with variable programming pulse height and pulse width |
DE69528971D1 (de) | 1995-06-30 | 2003-01-09 | St Microelectronics Srl | Herstellungsverfahren eines Schaltkreises, der nichtflüchtige Speicherzellen und Randtransistoren von mindestens zwei unterschiedlichen Typen enthält, und entsprechender IC |
US6034896A (en) | 1995-07-03 | 2000-03-07 | The University Of Toronto, Innovations Foundation | Method of fabricating a fast programmable flash E2 PROM cell |
KR970008496A (ko) | 1995-07-04 | 1997-02-24 | 모리시다 요이치 | Mis 반도체 장치와 그 제조방법 및 그 진단방법 |
EP0753859B1 (en) | 1995-07-14 | 2000-01-26 | STMicroelectronics S.r.l. | Method for setting the threshold voltage of a reference memory cell |
JP3424427B2 (ja) | 1995-07-27 | 2003-07-07 | ソニー株式会社 | 不揮発性半導体メモリ装置 |
US5631606A (en) | 1995-08-01 | 1997-05-20 | Information Storage Devices, Inc. | Fully differential output CMOS power amplifier |
US5721781A (en) | 1995-09-13 | 1998-02-24 | Microsoft Corporation | Authentication system and method for smart card transactions |
US5835935A (en) | 1995-09-13 | 1998-11-10 | Lexar Media, Inc. | Method of and architecture for controlling system data with automatic wear leveling in a semiconductor non-volatile mass storage memory |
US5604804A (en) | 1996-04-23 | 1997-02-18 | Micali; Silvio | Method for certifying public keys in a digital signature scheme |
US5696929A (en) | 1995-10-03 | 1997-12-09 | Intel Corporation | Flash EEPROM main memory in a computer system |
US5815435A (en) | 1995-10-10 | 1998-09-29 | Information Storage Devices, Inc. | Storage cell for analog recording and playback |
AU7475196A (en) | 1995-10-25 | 1997-05-15 | Nvx Corporation | Semiconductor non-volatile memory device having a nand cell structure |
US5644531A (en) | 1995-11-01 | 1997-07-01 | Advanced Micro Devices, Inc. | Program algorithm for low voltage single power supply flash memories |
JPH09191111A (ja) | 1995-11-07 | 1997-07-22 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
KR100253868B1 (ko) | 1995-11-13 | 2000-05-01 | 니시무로 타이죠 | 불휘발성 반도체기억장치 |
JP2982670B2 (ja) | 1995-12-12 | 1999-11-29 | 日本電気株式会社 | 不揮発性半導体記憶装置および記憶方法 |
US5677869A (en) | 1995-12-14 | 1997-10-14 | Intel Corporation | Programming flash memory using strict ordering of states |
JP3251164B2 (ja) | 1995-12-14 | 2002-01-28 | シャープ株式会社 | 半導体装置及びその製造方法 |
US5633603A (en) | 1995-12-26 | 1997-05-27 | Hyundai Electronics Industries Co., Ltd. | Data output buffer using pass transistors biased with a reference voltage and a precharged data input |
KR100223747B1 (ko) | 1995-12-28 | 1999-10-15 | 김영환 | 고속 저잡음 출력 버퍼 |
US5748534A (en) | 1996-03-26 | 1998-05-05 | Invox Technology | Feedback loop for reading threshold voltage |
US5920503A (en) | 1996-03-29 | 1999-07-06 | Aplus Flash Technology, Inc. | Flash memory with novel bitline decoder and sourceline latch |
US5777923A (en) | 1996-06-17 | 1998-07-07 | Aplus Integrated Circuits, Inc. | Flash memory read/write controller |
US5672959A (en) | 1996-04-12 | 1997-09-30 | Micro Linear Corporation | Low drop-out voltage regulator having high ripple rejection and low power consumption |
DE69630107D1 (de) | 1996-04-15 | 2003-10-30 | St Microelectronics Srl | Mit einem EEPROM integrierter FLASH-EPROM |
JP3200012B2 (ja) | 1996-04-19 | 2001-08-20 | 株式会社東芝 | 記憶システム |
US5712815A (en) | 1996-04-22 | 1998-01-27 | Advanced Micro Devices, Inc. | Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells |
US5663907A (en) | 1996-04-25 | 1997-09-02 | Bright Microelectronics, Inc. | Switch driver circuit for providing small sector sizes for negative gate erase flash EEPROMS using a standard twin-well CMOS process |
US5706292A (en) | 1996-04-25 | 1998-01-06 | Micron Technology, Inc. | Layout for a semiconductor memory device having redundant elements |
US5847441A (en) | 1996-05-10 | 1998-12-08 | Micron Technology, Inc. | Semiconductor junction antifuse circuit |
US5715193A (en) | 1996-05-23 | 1998-02-03 | Micron Quantum Devices, Inc. | Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks |
US5886927A (en) | 1996-06-11 | 1999-03-23 | Nkk Corporation | Nonvolatile memory device with verify function |
US5683925A (en) | 1996-06-13 | 1997-11-04 | Waferscale Integration Inc. | Manufacturing method for ROM array with minimal band-to-band tunneling |
DE69702256T2 (de) | 1996-06-24 | 2001-01-18 | Advanced Micro Devices Inc | Verfahren für einen merhfachen, bits pro zelle flash eeprom, speicher mit seitenprogrammierungsmodus und leseverfahren |
JP2882370B2 (ja) | 1996-06-28 | 1999-04-12 | 日本電気株式会社 | 半導体記憶装置 |
US6156149A (en) | 1997-05-07 | 2000-12-05 | Applied Materials, Inc. | In situ deposition of a dielectric oxide layer and anti-reflective coating |
KR100265574B1 (ko) | 1996-06-29 | 2000-09-15 | 김영환 | 반도체 메모리장치의 감지증폭기 |
US5793079A (en) | 1996-07-22 | 1998-08-11 | Catalyst Semiconductor, Inc. | Single transistor non-volatile electrically alterable semiconductor memory device |
US5768192A (en) | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
JP2917924B2 (ja) | 1996-07-30 | 1999-07-12 | 日本電気株式会社 | 不揮発性半導体記憶装置 |
KR20000005467A (ko) | 1996-08-01 | 2000-01-25 | 칼 하인쯔 호르닝어 | 저장 셀 장치의 동작 방법 |
US6037627A (en) | 1996-08-02 | 2000-03-14 | Seiko Instruments Inc. | MOS semiconductor device |
US5787484A (en) | 1996-08-08 | 1998-07-28 | Micron Technology, Inc. | System and method which compares data preread from memory cells to data to be written to the cells |
US5717635A (en) | 1996-08-27 | 1998-02-10 | International Business Machines Corporation | High density EEPROM for solid state file |
JP3709246B2 (ja) | 1996-08-27 | 2005-10-26 | 株式会社日立製作所 | 半導体集積回路 |
TW338165B (en) | 1996-09-09 | 1998-08-11 | Sony Co Ltd | Semiconductor nand type flash memory with incremental step pulse programming |
US5760634A (en) | 1996-09-12 | 1998-06-02 | United Microelectronics Corporation | High speed, low noise output buffer |
US5777919A (en) | 1996-09-13 | 1998-07-07 | Holtek Microelectronics, Inc. | Select gate enhanced high density read-only-memory device |
FR2753579B1 (fr) | 1996-09-19 | 1998-10-30 | Sgs Thomson Microelectronics | Circuit electronique pourvu d'un dispositif de neutralisation |
US5873113A (en) | 1996-09-24 | 1999-02-16 | Altera Corporation | System and method for programming eprom cells using shorter duration pulse(s) in repeating the programming process of a particular cell |
JP3930074B2 (ja) | 1996-09-30 | 2007-06-13 | 株式会社ルネサステクノロジ | 半導体集積回路及びデータ処理システム |
US5808506A (en) | 1996-10-01 | 1998-09-15 | Information Storage Devices, Inc. | MOS charge pump generation and regulation method and apparatus |
US5812456A (en) | 1996-10-01 | 1998-09-22 | Microchip Technology Incorporated | Switched ground read for EPROM memory array |
EP0836268B1 (en) | 1996-10-11 | 2002-02-06 | STMicroelectronics S.r.l. | Improved positive charge pump |
US6078518A (en) | 1998-02-25 | 2000-06-20 | Micron Technology, Inc. | Apparatus and method for reading state of multistate non-volatile memory cells |
US5764568A (en) | 1996-10-24 | 1998-06-09 | Micron Quantum Devices, Inc. | Method for performing analog over-program and under-program detection for a multistate memory cell |
JPH10133754A (ja) | 1996-10-28 | 1998-05-22 | Fujitsu Ltd | レギュレータ回路及び半導体集積回路装置 |
US5886561A (en) | 1996-11-18 | 1999-03-23 | Waferscale Integration, Inc. | Backup battery switch |
US5774395A (en) | 1996-11-27 | 1998-06-30 | Advanced Micro Devices, Inc. | Electrically erasable reference cell for accurately determining threshold voltage of a non-volatile memory at a plurality of threshold voltage levels |
US5717632A (en) | 1996-11-27 | 1998-02-10 | Advanced Micro Devices, Inc. | Apparatus and method for multiple-level storage in non-volatile memories |
TW367503B (en) | 1996-11-29 | 1999-08-21 | Sanyo Electric Co | Non-volatile semiconductor device |
TW318283B (en) | 1996-12-09 | 1997-10-21 | United Microelectronics Corp | Multi-level read only memory structure and manufacturing method thereof |
US6418506B1 (en) | 1996-12-31 | 2002-07-09 | Intel Corporation | Integrated circuit memory and method for transferring data using a volatile memory to buffer data for a nonvolatile memory array |
US5837584A (en) | 1997-01-15 | 1998-11-17 | Macronix International Co., Ltd. | Virtual ground flash cell with asymmetrically placed source and drain and method of fabrication |
EP0855788B1 (en) | 1997-01-23 | 2005-06-22 | STMicroelectronics S.r.l. | NMOS negative charge pump |
US6130574A (en) | 1997-01-24 | 2000-10-10 | Siemens Aktiengesellschaft | Circuit configuration for producing negative voltages, charge pump having at least two circuit configurations and method of operating a charge pump |
TW347581B (en) | 1997-02-05 | 1998-12-11 | United Microelectronics Corp | Process for fabricating read-only memory cells |
JPH10228784A (ja) * | 1997-02-12 | 1998-08-25 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
US5872848A (en) | 1997-02-18 | 1999-02-16 | Arcanvs | Method and apparatus for witnessed authentication of electronic documents |
IT1289933B1 (it) | 1997-02-20 | 1998-10-19 | Sgs Thomson Microelectronics | Dispositivo di memoria con matrice di celle di memoria in triplo well e relativo procedimento di fabbricazione |
JP3532725B2 (ja) | 1997-02-27 | 2004-05-31 | 株式会社東芝 | 半導体集積回路 |
US6107862A (en) | 1997-02-28 | 2000-08-22 | Seiko Instruments Inc. | Charge pump circuit |
US5870335A (en) | 1997-03-06 | 1999-02-09 | Agate Semiconductor, Inc. | Precision programming of nonvolatile memory cells |
US6028324A (en) | 1997-03-07 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company | Test structures for monitoring gate oxide defect densities and the plasma antenna effect |
JPH10261292A (ja) | 1997-03-18 | 1998-09-29 | Nec Corp | 不揮発性半導体記憶装置の消去方法 |
US6190966B1 (en) | 1997-03-25 | 2001-02-20 | Vantis Corporation | Process for fabricating semiconductor memory device with high data retention including silicon nitride etch stop layer formed at high temperature with low hydrogen ion concentration |
JP3920415B2 (ja) | 1997-03-31 | 2007-05-30 | 三洋電機株式会社 | 不揮発性半導体メモリ装置 |
JP4253052B2 (ja) | 1997-04-08 | 2009-04-08 | 株式会社東芝 | 半導体装置 |
US6252799B1 (en) | 1997-04-11 | 2001-06-26 | Programmable Silicon Solutions | Device with embedded flash and EEPROM memories |
TW381325B (en) | 1997-04-15 | 2000-02-01 | United Microelectronics Corp | Three dimensional high density deep trench ROM and the manufacturing method thereof |
US5880620A (en) | 1997-04-22 | 1999-03-09 | Xilinx, Inc. | Pass gate circuit with body bias control |
US5966603A (en) | 1997-06-11 | 1999-10-12 | Saifun Semiconductors Ltd. | NROM fabrication method with a periphery portion |
US6297096B1 (en) | 1997-06-11 | 2001-10-02 | Saifun Semiconductors Ltd. | NROM fabrication method |
US5805500A (en) | 1997-06-18 | 1998-09-08 | Sgs-Thomson Microelectronics S.R.L. | Circuit and method for generating a read reference signal for nonvolatile memory cells |
JP3189740B2 (ja) | 1997-06-20 | 2001-07-16 | 日本電気株式会社 | 不揮発性半導体メモリのデータ修復方法 |
US6335990B1 (en) | 1997-07-03 | 2002-01-01 | Cisco Technology, Inc. | System and method for spatial temporal-filtering for improving compressed digital video |
JP3039458B2 (ja) | 1997-07-07 | 2000-05-08 | 日本電気株式会社 | 不揮発性半導体メモリ |
JP3765163B2 (ja) | 1997-07-14 | 2006-04-12 | ソニー株式会社 | レベルシフト回路 |
US6031263A (en) | 1997-07-29 | 2000-02-29 | Micron Technology, Inc. | DEAPROM and transistor with gallium nitride or gallium aluminum nitride gate |
IL125604A (en) | 1997-07-30 | 2004-03-28 | Saifun Semiconductors Ltd | Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6000006A (en) | 1997-08-25 | 1999-12-07 | Bit Microsystems, Inc. | Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage |
US6064251A (en) | 1997-08-27 | 2000-05-16 | Integrated Silicon Solution, Inc. | System and method for a low voltage charge pump with large output voltage range |
JP3951443B2 (ja) | 1997-09-02 | 2007-08-01 | ソニー株式会社 | 不揮発性半導体記憶装置及びその書き込み方法 |
US5926409A (en) | 1997-09-05 | 1999-07-20 | Information Storage Devices, Inc. | Method and apparatus for an adaptive ramp amplitude controller in nonvolatile memory application |
US5825683A (en) | 1997-10-29 | 1998-10-20 | Utron Technology Inc. | Folded read-only memory |
JP3322828B2 (ja) | 1997-10-31 | 2002-09-09 | シャープ株式会社 | 半導体記憶装置 |
EP1029374B1 (en) | 1997-11-12 | 2004-02-25 | Deka Products Limited Partnership | Piezo-electric actuator operable in an electrolytic fluid |
US5963412A (en) | 1997-11-13 | 1999-10-05 | Advanced Micro Devices, Inc. | Process induced charging damage control device |
US5940332A (en) | 1997-11-13 | 1999-08-17 | Stmicroelectronics, Inc. | Programmed memory with improved speed and power consumption |
US5867429A (en) | 1997-11-19 | 1999-02-02 | Sandisk Corporation | High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates |
US6281545B1 (en) | 1997-11-20 | 2001-08-28 | Taiwan Semiconductor Manufacturing Company | Multi-level, split-gate, flash memory cell |
IT1296486B1 (it) | 1997-11-21 | 1999-06-25 | Ses Thomson Microelectronics S | Regolatore di tensione per circuiti di memoria a singola tensione di alimentazione, in particolare per memorie di tipo flash. |
JP3599541B2 (ja) | 1997-11-27 | 2004-12-08 | シャープ株式会社 | 不揮発性半導体記憶装置 |
US5949728A (en) | 1997-12-12 | 1999-09-07 | Scenix Semiconductor, Inc. | High speed, noise immune, single ended sensing scheme for non-volatile memories |
US6633499B1 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Method for reducing voltage drops in symmetric array architectures |
US5963465A (en) | 1997-12-12 | 1999-10-05 | Saifun Semiconductors, Ltd. | Symmetric segmented memory array architecture |
US6633496B2 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Symmetric architecture for memory cells having widely spread metal bit lines |
DE69839959D1 (de) | 1997-12-19 | 2008-10-16 | Texas Instruments Inc | Vorspannungsstrommessschaltung für Mikrofon |
US6020241A (en) | 1997-12-22 | 2000-02-01 | Taiwan Semiconductor Manufacturing Company | Post metal code engineering for a ROM |
US6034433A (en) | 1997-12-23 | 2000-03-07 | Intel Corporation | Interconnect structure for protecting a transistor gate from charge damage |
KR100327421B1 (ko) | 1997-12-31 | 2002-07-27 | 주식회사 하이닉스반도체 | 비휘발성 메모리 소자의 프로그램 시스템 및 그의 프로그램 방법 |
US6306653B1 (en) | 1998-01-20 | 2001-10-23 | Codon Diagnostics, Llc | Detection and treatment of breast disease |
US6195196B1 (en) | 1998-03-13 | 2001-02-27 | Fuji Photo Film Co., Ltd. | Array-type exposing device and flat type display incorporating light modulator and driving method thereof |
US5946258A (en) | 1998-03-16 | 1999-08-31 | Intel Corporation | Pump supply self regulation for flash memory cell pair reference circuit |
US6064226A (en) | 1998-03-17 | 2000-05-16 | Vanguard International Semiconductor Corporation | Multiple input/output level interface input receiver |
JP3580693B2 (ja) | 1998-03-19 | 2004-10-27 | シャープ株式会社 | チャージ・ポンプ回路 |
KR100339024B1 (ko) | 1998-03-28 | 2002-09-18 | 주식회사 하이닉스반도체 | 플래쉬메모리장치의센스앰프회로 |
US6243289B1 (en) | 1998-04-08 | 2001-06-05 | Micron Technology Inc. | Dual floating gate programmable read only memory cell structure and method for its fabrication and operation |
US5991201A (en) * | 1998-04-27 | 1999-11-23 | Motorola Inc. | Non-volatile memory with over-program protection and method therefor |
JP3346274B2 (ja) | 1998-04-27 | 2002-11-18 | 日本電気株式会社 | 不揮発性半導体記憶装置 |
FR2778012B1 (fr) | 1998-04-28 | 2001-09-28 | Sgs Thomson Microelectronics | Dispositif et procede de lecture de cellules de memoire eeprom |
US6344959B1 (en) | 1998-05-01 | 2002-02-05 | Unitrode Corporation | Method for sensing the output voltage of a charge pump circuit without applying a load to the output stage |
US6030871A (en) | 1998-05-05 | 2000-02-29 | Saifun Semiconductors Ltd. | Process for producing two bit ROM cell utilizing angled implant |
US6188211B1 (en) | 1998-05-13 | 2001-02-13 | Texas Instruments Incorporated | Current-efficient low-drop-out voltage regulator with improved load regulation and frequency response |
US6215148B1 (en) | 1998-05-20 | 2001-04-10 | Saifun Semiconductors Ltd. | NROM cell with improved programming, erasing and cycling |
US6348711B1 (en) | 1998-05-20 | 2002-02-19 | Saifun Semiconductors Ltd. | NROM cell with self-aligned programming and erasure areas |
US6063666A (en) | 1998-06-16 | 2000-05-16 | Advanced Micro Devices, Inc. | RTCVD oxide and N2 O anneal for top oxide of ONO film |
US6034403A (en) | 1998-06-25 | 2000-03-07 | Acer Semiconductor Manufacturing, Inc. | High density flat cell mask ROM |
US6308485B1 (en) | 1998-06-29 | 2001-10-30 | Stora Kopparbergs Bergslags Ab | Panel and method for mounting the same |
US6094095A (en) | 1998-06-29 | 2000-07-25 | Cypress Semiconductor Corp. | Efficient pump for generating voltages above and/or below operating voltages |
TW379399B (en) | 1998-07-08 | 2000-01-11 | United Microelectronics Corp | Structure for monitoring antenna effect |
JP3999900B2 (ja) | 1998-09-10 | 2007-10-31 | 株式会社東芝 | 不揮発性半導体メモリ |
DE69828966D1 (de) | 1998-09-15 | 2005-03-17 | St Microelectronics Srl | Verfahren zum Schutz des Inhalts nichtflüchtiger Speicherzellen |
US6285246B1 (en) | 1998-09-15 | 2001-09-04 | California Micro Devices, Inc. | Low drop-out regulator capable of functioning in linear and saturated regions of output driver |
JP3456904B2 (ja) | 1998-09-16 | 2003-10-14 | 松下電器産業株式会社 | 突入電流抑制手段を備えた電源回路、およびこの電源回路を備えた集積回路 |
US5991202A (en) | 1998-09-24 | 1999-11-23 | Advanced Micro Devices, Inc. | Method for reducing program disturb during self-boosting in a NAND flash memory |
US6205059B1 (en) | 1998-10-05 | 2001-03-20 | Advanced Micro Devices | Method for erasing flash electrically erasable programmable read-only memory (EEPROM) |
US6219290B1 (en) | 1998-10-14 | 2001-04-17 | Macronix International Co., Ltd. | Memory cell sense amplifier |
US6044019A (en) | 1998-10-23 | 2000-03-28 | Sandisk Corporation | Non-volatile memory with improved sensing and method therefor |
US6040996A (en) * | 1998-11-16 | 2000-03-21 | Chartered Semiconductor Manufacturing, Ltd. | Constant current programming waveforms for non-volatile memories |
AU1729100A (en) | 1998-11-17 | 2000-06-05 | Lexar Media, Inc. | Method and apparatus for memory control circuit |
JP3554497B2 (ja) | 1998-12-08 | 2004-08-18 | シャープ株式会社 | チャージポンプ回路 |
US6214666B1 (en) | 1998-12-18 | 2001-04-10 | Vantis Corporation | Method of forming a non-volatile memory device |
US6215697B1 (en) | 1999-01-14 | 2001-04-10 | Macronix International Co., Ltd. | Multi-level memory cell device and method for self-converged programming |
US6282145B1 (en) | 1999-01-14 | 2001-08-28 | Silicon Storage Technology, Inc. | Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system |
US6133095A (en) | 1999-02-04 | 2000-10-17 | Saifun Semiconductors Ltd. | Method for creating diffusion areas for sources and drains without an etch step |
US6108240A (en) | 1999-02-04 | 2000-08-22 | Tower Semiconductor Ltd. | Implementation of EEPROM using intermediate gate voltage to avoid disturb conditions |
US6181597B1 (en) | 1999-02-04 | 2001-01-30 | Tower Semiconductor Ltd. | EEPROM array using 2-bit non-volatile memory cells with serial read operations |
US6081456A (en) | 1999-02-04 | 2000-06-27 | Tower Semiconductor Ltd. | Bit line control circuit for a memory array using 2-bit non-volatile memory cells |
US6128226A (en) | 1999-02-04 | 2000-10-03 | Saifun Semiconductors Ltd. | Method and apparatus for operating with a close to ground signal |
US6256231B1 (en) | 1999-02-04 | 2001-07-03 | Tower Semiconductor Ltd. | EEPROM array using 2-bit non-volatile memory cells and method of implementing same |
US6233180B1 (en) | 1999-02-04 | 2001-05-15 | Saifun Semiconductors Ltd. | Device for determining the validity of word line conditions and for delaying data sensing operation |
US6346442B1 (en) | 1999-02-04 | 2002-02-12 | Tower Semiconductor Ltd. | Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array |
US6157570A (en) | 1999-02-04 | 2000-12-05 | Tower Semiconductor Ltd. | Program/erase endurance of EEPROM memory cells |
US6147904A (en) | 1999-02-04 | 2000-11-14 | Tower Semiconductor Ltd. | Redundancy method and structure for 2-bit non-volatile memory cells |
US6134156A (en) | 1999-02-04 | 2000-10-17 | Saifun Semiconductors Ltd. | Method for initiating a retrieval procedure in virtual ground arrays |
US6075724A (en) | 1999-02-22 | 2000-06-13 | Vantis Corporation | Method for sorting semiconductor devices having a plurality of non-volatile memory cells |
US6044022A (en) | 1999-02-26 | 2000-03-28 | Tower Semiconductor Ltd. | Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays |
US6208557B1 (en) | 1999-05-21 | 2001-03-27 | National Semiconductor Corporation | EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming |
US6084794A (en) | 1999-05-28 | 2000-07-04 | Winbond Electronics Corp. | High speed flat-cell mask ROM structure with select lines |
US6154081A (en) | 1999-06-15 | 2000-11-28 | Delphi Technologies, Inc. | Load circuit having extended reverse voltage protection |
US6337502B1 (en) | 1999-06-18 | 2002-01-08 | Saifun Semicinductors Ltd. | Method and circuit for minimizing the charging effect during manufacture of semiconductor devices |
KR100328359B1 (ko) * | 1999-06-22 | 2002-03-13 | 윤종용 | 기판 전압 바운싱을 최소화할 수 있는 플래시 메모리 장치 및그것의 프로그램 방법 |
US6218695B1 (en) | 1999-06-28 | 2001-04-17 | Tower Semiconductor Ltd. | Area efficient column select circuitry for 2-bit non-volatile memory cells |
US6108241A (en) | 1999-07-01 | 2000-08-22 | Micron Technology, Inc. | Leakage detection in flash memory cell |
US6175519B1 (en) | 1999-07-22 | 2001-01-16 | Macronix International Co., Ltd. | Virtual ground EPROM structure |
DE69911591D1 (de) | 1999-07-22 | 2003-10-30 | St Microelectronics Srl | Leseschaltung für einen nichtflüchtigen Speicher |
JP2001051730A (ja) | 1999-08-05 | 2001-02-23 | Fujitsu Ltd | スイッチ回路及びシリーズレギュレータ |
US6469935B2 (en) | 1999-08-05 | 2002-10-22 | Halo Lsi Design & Device Technology, Inc. | Array architecture nonvolatile memory and its operation methods |
JP3912937B2 (ja) | 1999-08-10 | 2007-05-09 | スパンション インク | 非導電性のチャージトラップゲートを利用した多ビット不揮発性メモリ |
US6122198A (en) | 1999-08-13 | 2000-09-19 | Advanced Micro Devices, Inc. | Bit by bit APDE verify for flash memory applications |
US6353356B1 (en) | 1999-08-30 | 2002-03-05 | Micron Technology, Inc. | High voltage charge pump circuits |
JP4091221B2 (ja) | 1999-09-10 | 2008-05-28 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP3348432B2 (ja) | 1999-09-14 | 2002-11-20 | 日本電気株式会社 | 半導体装置および半導体記憶装置 |
US6297974B1 (en) | 1999-09-27 | 2001-10-02 | Intel Corporation | Method and apparatus for reducing stress across capacitors used in integrated circuits |
US6181605B1 (en) | 1999-10-06 | 2001-01-30 | Advanced Micro Devices, Inc. | Global erase/program verification apparatus and method |
JP3829161B2 (ja) | 1999-10-14 | 2006-10-04 | スパンション インク | 多ビット情報を記録する不揮発性メモリ回路 |
US6147906A (en) | 1999-10-14 | 2000-11-14 | Advanced Micro Devices, Inc. | Method and system for saving overhead program time in a memory device |
US6331950B1 (en) | 1999-10-19 | 2001-12-18 | Fujitsu Limited | Write protect input implementation for a simultaneous operation flash memory device |
US6265268B1 (en) | 1999-10-25 | 2001-07-24 | Advanced Micro Devices, Inc. | High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device |
US6458677B1 (en) | 1999-10-25 | 2002-10-01 | Advanced Micro Devices, Inc. | Process for fabricating an ONO structure |
US6297143B1 (en) | 1999-10-25 | 2001-10-02 | Advanced Micro Devices, Inc. | Process for forming a bit-line in a MONOS device |
US6175523B1 (en) | 1999-10-25 | 2001-01-16 | Advanced Micro Devices, Inc | Precharging mechanism and method for NAND-based flash memory devices |
US6429063B1 (en) | 1999-10-26 | 2002-08-06 | Saifun Semiconductors Ltd. | NROM cell with generally decoupled primary and secondary injection |
US6436766B1 (en) | 1999-10-29 | 2002-08-20 | Advanced Micro Devices, Inc. | Process for fabricating high density memory cells using a polysilicon hard mask |
IT1308856B1 (it) | 1999-10-29 | 2002-01-11 | St Microelectronics Srl | Circuito di lettura per una memoria non volatile. |
JP2001143487A (ja) | 1999-11-15 | 2001-05-25 | Nec Corp | 半導体記憶装置 |
US6272047B1 (en) | 1999-12-17 | 2001-08-07 | Micron Technology, Inc. | Flash memory cell |
JP2003518309A (ja) | 1999-12-21 | 2003-06-03 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 電流制限器を備えた電圧発生器 |
US6828638B2 (en) | 1999-12-22 | 2004-12-07 | Intel Corporation | Decoupling capacitors for thin gate oxides |
JP4360736B2 (ja) | 2000-01-27 | 2009-11-11 | 株式会社ルネサステクノロジ | 不揮発性半導体記憶装置および不揮発性半導体記憶装置のデータ消去方法 |
US6201737B1 (en) | 2000-01-28 | 2001-03-13 | Advanced Micro Devices, Inc. | Apparatus and method to characterize the threshold distribution in an NROM virtual ground array |
US6222768B1 (en) | 2000-01-28 | 2001-04-24 | Advanced Micro Devices, Inc. | Auto adjusting window placement scheme for an NROM virtual ground array |
US6185143B1 (en) | 2000-02-04 | 2001-02-06 | Hewlett-Packard Company | Magnetic random access memory (MRAM) device including differential sense amplifiers |
US6261904B1 (en) | 2000-02-10 | 2001-07-17 | Advanced Micro Devices, Inc. | Dual bit isolation scheme for flash devices |
TW476179B (en) | 2000-02-11 | 2002-02-11 | Winbond Electronics Corp | Charge pump circuit applied in low supply voltage |
US6410388B1 (en) | 2000-02-15 | 2002-06-25 | Advanced Micro Devices, Inc. | Process for optimizing pocket implant profile by RTA implant annealing for a non-volatile semiconductor device |
US6438031B1 (en) | 2000-02-16 | 2002-08-20 | Advanced Micro Devices, Inc. | Method of programming a non-volatile memory cell using a substrate bias |
US6266281B1 (en) | 2000-02-16 | 2001-07-24 | Advanced Micro Devices, Inc. | Method of erasing non-volatile memory cells |
US6215702B1 (en) | 2000-02-16 | 2001-04-10 | Advanced Micro Devices, Inc. | Method of maintaining constant erasing speeds for non-volatile memory cells |
US6205055B1 (en) | 2000-02-25 | 2001-03-20 | Advanced Micro Devices, Inc. | Dynamic memory cell programming voltage |
US6343033B1 (en) | 2000-02-25 | 2002-01-29 | Advanced Micro Devices, Inc. | Variable pulse width memory programming |
US6205056B1 (en) | 2000-03-14 | 2001-03-20 | Advanced Micro Devices, Inc. | Automated reference cell trimming verify |
US6240040B1 (en) | 2000-03-15 | 2001-05-29 | Advanced Micro Devices, Inc. | Multiple bank simultaneous operation for a flash memory |
US6458656B1 (en) | 2000-03-16 | 2002-10-01 | Advanced Micro Devices, Inc. | Process for creating a flash memory cell using a photoresist flow operation |
DE10017920A1 (de) | 2000-04-11 | 2001-10-25 | Infineon Technologies Ag | Ladungspumpenanordnung |
JP2001297316A (ja) | 2000-04-14 | 2001-10-26 | Mitsubishi Electric Corp | メモリカード及びその制御方法 |
US6396741B1 (en) | 2000-05-04 | 2002-05-28 | Saifun Semiconductors Ltd. | Programming of nonvolatile memory cells |
US6490204B2 (en) | 2000-05-04 | 2002-12-03 | Saifun Semiconductors Ltd. | Programming and erasing methods for a reference cell of an NROM array |
US6928001B2 (en) | 2000-12-07 | 2005-08-09 | Saifun Semiconductors Ltd. | Programming and erasing methods for a non-volatile memory cell |
JP4002712B2 (ja) | 2000-05-15 | 2007-11-07 | スパンション エルエルシー | 不揮発性半導体記憶装置および不揮発性半導体記憶装置のデータ保持方法 |
US6417081B1 (en) | 2000-05-16 | 2002-07-09 | Advanced Micro Devices, Inc. | Process for reduction of capacitance of a bitline for a non-volatile memory cell |
US6593606B1 (en) | 2000-05-16 | 2003-07-15 | Advanced Micro Devices, Inc. | Staggered bitline strapping of a non-volatile memory cell |
US6538270B1 (en) | 2000-05-16 | 2003-03-25 | Advanced Micro Devices, Inc. | Staggered bitline strapping of a non-volatile memory cell |
US6275414B1 (en) | 2000-05-16 | 2001-08-14 | Advanced Micro Devices, Inc. | Uniform bitline strapping of a non-volatile memory cell |
JP2001357686A (ja) | 2000-06-13 | 2001-12-26 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
JP3653449B2 (ja) | 2000-06-15 | 2005-05-25 | シャープ株式会社 | 不揮発性半導体記憶装置 |
US6618290B1 (en) | 2000-06-23 | 2003-09-09 | Advanced Micro Devices, Inc. | Method of programming a non-volatile memory cell using a baking process |
US6292394B1 (en) | 2000-06-29 | 2001-09-18 | Saifun Semiconductors Ltd. | Method for programming of a semiconductor memory cell |
US6519182B1 (en) | 2000-07-10 | 2003-02-11 | Advanced Micro Devices, Inc. | Using hot carrier injection to control over-programming in a non-volatile memory cell having an oxide-nitride-oxide (ONO) structure |
JP4707803B2 (ja) | 2000-07-10 | 2011-06-22 | エルピーダメモリ株式会社 | エラーレート判定方法と半導体集積回路装置 |
TW503528B (en) | 2000-07-12 | 2002-09-21 | Koninkl Philips Electronics Nv | Semiconductor device |
JP2002050705A (ja) | 2000-08-01 | 2002-02-15 | Fujitsu Ltd | 半導体記憶装置及びその製造方法 |
WO2002013199A1 (fr) | 2000-08-03 | 2002-02-14 | Fujitsu Limited | Memoire a semiconducteurs non volatile et procede de lecture des donnees |
US6562683B1 (en) | 2000-08-31 | 2003-05-13 | Advanced Micro Devices, Inc. | Bit-line oxidation by removing ONO oxide prior to bit-line implant |
US6246555B1 (en) | 2000-09-06 | 2001-06-12 | Prominenet Communications Inc. | Transient current and voltage protection of a voltage regulator |
US6356469B1 (en) | 2000-09-14 | 2002-03-12 | Fairchild Semiconductor Corporation | Low voltage charge pump employing optimized clock amplitudes |
US6356062B1 (en) | 2000-09-27 | 2002-03-12 | Intel Corporation | Degenerative load temperature correction for charge pumps |
US6583479B1 (en) | 2000-10-16 | 2003-06-24 | Advanced Micro Devices, Inc. | Sidewall NROM and method of manufacture thereof for non-volatile memory cells |
US6537881B1 (en) | 2000-10-16 | 2003-03-25 | Advanced Micro Devices, Inc. | Process for fabricating a non-volatile memory device |
JP4051175B2 (ja) | 2000-11-17 | 2008-02-20 | スパンション エルエルシー | 不揮発性半導体メモリ装置および製造方法 |
US6465306B1 (en) | 2000-11-28 | 2002-10-15 | Advanced Micro Devices, Inc. | Simultaneous formation of charge storage and bitline to wordline isolation |
US6433624B1 (en) | 2000-11-30 | 2002-08-13 | Intel Corporation | Threshold voltage generation circuit |
JP2002184190A (ja) | 2000-12-11 | 2002-06-28 | Toshiba Corp | 不揮発性半導体記憶装置 |
EP1217744B1 (en) | 2000-12-21 | 2004-03-24 | STMicroelectronics S.r.l. | An output buffer with constant switching current |
WO2002050843A1 (fr) | 2000-12-21 | 2002-06-27 | Fujitsu Limited | Memoire a semi-conducteurs non volatile et procede d'effacement |
TW490675B (en) | 2000-12-22 | 2002-06-11 | Macronix Int Co Ltd | Control method of multi-stated NROM |
US6349056B1 (en) * | 2000-12-28 | 2002-02-19 | Sandisk Corporation | Method and structure for efficient data verification operation for non-volatile memories |
US6452438B1 (en) | 2000-12-28 | 2002-09-17 | Intel Corporation | Triple well no body effect negative charge pump |
JP3846293B2 (ja) | 2000-12-28 | 2006-11-15 | 日本電気株式会社 | 帰還型増幅回路及び駆動回路 |
JP2002216496A (ja) | 2001-01-16 | 2002-08-02 | Umc Japan | 半導体メモリ装置 |
US6449190B1 (en) | 2001-01-17 | 2002-09-10 | Advanced Micro Devices, Inc. | Adaptive reference cells for a memory device |
US6614692B2 (en) | 2001-01-18 | 2003-09-02 | Saifun Semiconductors Ltd. | EEPROM array and method for operation thereof |
JP2002216488A (ja) | 2001-01-18 | 2002-08-02 | Iwate Toshiba Electronics Co Ltd | 半導体記憶装置 |
JP3631463B2 (ja) * | 2001-12-27 | 2005-03-23 | 株式会社東芝 | 不揮発性半導体記憶装置 |
US6445030B1 (en) | 2001-01-30 | 2002-09-03 | Advanced Micro Devices, Inc. | Flash memory erase speed by fluorine implant or fluorination |
US6567303B1 (en) | 2001-01-31 | 2003-05-20 | Advanced Micro Devices, Inc. | Charge injection |
JP3930256B2 (ja) | 2001-02-07 | 2007-06-13 | スパンション エルエルシー | 半導体装置及びその製造方法 |
US6348381B1 (en) | 2001-02-21 | 2002-02-19 | Macronix International Co., Ltd. | Method for forming a nonvolatile memory with optimum bias condition |
JP4467815B2 (ja) | 2001-02-26 | 2010-05-26 | 富士通マイクロエレクトロニクス株式会社 | 不揮発性半導体メモリの読み出し動作方法および不揮発性半導体メモリ |
US6738289B2 (en) * | 2001-02-26 | 2004-05-18 | Sandisk Corporation | Non-volatile memory with improved programming and method therefor |
US6442074B1 (en) | 2001-02-28 | 2002-08-27 | Advanced Micro Devices, Inc. | Tailored erase method using higher program VT and higher negative gate erase |
US6456533B1 (en) | 2001-02-28 | 2002-09-24 | Advanced Micro Devices, Inc. | Higher program VT and faster programming rates based on improved erase methods |
US6307784B1 (en) | 2001-02-28 | 2001-10-23 | Advanced Micro Devices | Negative gate erase |
US6528390B2 (en) | 2001-03-02 | 2003-03-04 | Advanced Micro Devices, Inc. | Process for fabricating a non-volatile memory device |
US6426898B1 (en) | 2001-03-05 | 2002-07-30 | Micron Technology, Inc. | Method of reducing trapped holes induced by erase operations in the tunnel oxide of flash memory cells |
US6351415B1 (en) | 2001-03-28 | 2002-02-26 | Tower Semiconductor Ltd. | Symmetrical non-volatile memory array architecture without neighbor effect |
JP2002299473A (ja) | 2001-03-29 | 2002-10-11 | Fujitsu Ltd | 半導体記憶装置及びその駆動方法 |
US6577514B2 (en) | 2001-04-05 | 2003-06-10 | Saifun Semiconductors Ltd. | Charge pump with constant boosted output voltage |
US6665769B2 (en) | 2001-04-05 | 2003-12-16 | Saifun Semiconductors Ltd. | Method and apparatus for dynamically masking an N-bit memory array having individually programmable cells |
US20020145465A1 (en) | 2001-04-05 | 2002-10-10 | Joseph Shor | Efficient charge pump apparatus and method for operating the same |
US6584017B2 (en) | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
US6677805B2 (en) | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
US6448750B1 (en) | 2001-04-05 | 2002-09-10 | Saifun Semiconductor Ltd. | Voltage regulator for non-volatile memory with large power supply rejection ration and minimal current drain |
US6535434B2 (en) | 2001-04-05 | 2003-03-18 | Saifun Semiconductors Ltd. | Architecture and scheme for a non-strobed read sequence |
US6493266B1 (en) | 2001-04-09 | 2002-12-10 | Advanced Micro Devices, Inc. | Soft program and soft program verify of the core cells in flash memory array |
EP1249842B1 (en) * | 2001-04-10 | 2009-08-26 | STMicroelectronics S.r.l. | Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude |
JP2002319287A (ja) | 2001-04-20 | 2002-10-31 | Fujitsu Ltd | 不揮発性半導体メモリ |
US6636440B2 (en) | 2001-04-25 | 2003-10-21 | Saifun Semiconductors Ltd. | Method for operation of an EEPROM array, including refresh thereof |
US6455896B1 (en) | 2001-04-25 | 2002-09-24 | Macronix International Co., Ltd. | Protection circuit for a memory array |
TW508590B (en) | 2001-05-09 | 2002-11-01 | Macronix Int Co Ltd | Operating method of flash memory with symmetrical dual channel |
US6522585B2 (en) | 2001-05-25 | 2003-02-18 | Sandisk Corporation | Dual-cell soft programming for virtual-ground memory arrays |
EP1265252A1 (en) * | 2001-06-05 | 2002-12-11 | STMicroelectronics S.r.l. | A method for sector erasure and sector erase verification in a non-voltaile FLASH EEPROM |
US6617179B1 (en) | 2001-06-05 | 2003-09-09 | Advanced Micro Devices, Inc. | Method and system for qualifying an ONO layer in a semiconductor device |
US6449188B1 (en) | 2001-06-19 | 2002-09-10 | Advanced Micro Devices, Inc. | Low column leakage nor flash array-double cell implementation |
US6662274B2 (en) | 2001-06-20 | 2003-12-09 | Intel Corporation | Method for using cache prefetch feature to improve garbage collection algorithm |
US6574139B2 (en) | 2001-06-20 | 2003-06-03 | Fujitsu Limited | Method and device for reading dual bit memory cells using multiple reference cells with two side read |
US6512701B1 (en) | 2001-06-21 | 2003-01-28 | Advanced Micro Devices, Inc. | Erase method for dual bit virtual ground flash |
DE10129958B4 (de) | 2001-06-21 | 2006-07-13 | Infineon Technologies Ag | Speicherzellenanordnung und Herstellungsverfahren |
US6436768B1 (en) | 2001-06-27 | 2002-08-20 | Advanced Micro Devices, Inc. | Source drain implant during ONO formation for improved isolation of SONOS devices |
US6462387B1 (en) | 2001-06-29 | 2002-10-08 | Chinatech Corporation | High density read only memory |
KR100390959B1 (ko) | 2001-06-29 | 2003-07-12 | 주식회사 하이닉스반도체 | 센싱회로를 이용한 멀티레벨 플래시 메모리 프로그램/리드방법 |
JP4859294B2 (ja) | 2001-07-10 | 2012-01-25 | 富士通セミコンダクター株式会社 | 不揮発性半導体記憶装置 |
US6654296B2 (en) | 2001-07-23 | 2003-11-25 | Samsung Electronics Co., Ltd. | Devices, circuits and methods for dual voltage generation using single charge pump |
US6643178B2 (en) | 2001-07-31 | 2003-11-04 | Fujitsu Limited | System for source side sensing |
US6525969B1 (en) | 2001-08-10 | 2003-02-25 | Advanced Micro Devices, Inc. | Decoder apparatus and methods for pre-charging bit lines |
US6469929B1 (en) | 2001-08-21 | 2002-10-22 | Tower Semiconductor Ltd. | Structure and method for high speed sensing of memory arrays |
US6456528B1 (en) * | 2001-09-17 | 2002-09-24 | Sandisk Corporation | Selective operation of a multi-state non-volatile memory system in a binary mode |
US6440797B1 (en) | 2001-09-28 | 2002-08-27 | Advanced Micro Devices, Inc. | Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory |
US6566194B1 (en) | 2001-10-01 | 2003-05-20 | Advanced Micro Devices, Inc. | Salicided gate for virtual ground arrays |
US6645801B1 (en) | 2001-10-01 | 2003-11-11 | Advanced Micro Devices, Inc. | Salicided gate for virtual ground arrays |
US6630384B1 (en) | 2001-10-05 | 2003-10-07 | Advanced Micro Devices, Inc. | Method of fabricating double densed core gates in sonos flash memory |
US6510082B1 (en) | 2001-10-23 | 2003-01-21 | Advanced Micro Devices, Inc. | Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold |
US6643181B2 (en) | 2001-10-24 | 2003-11-04 | Saifun Semiconductors Ltd. | Method for erasing a memory cell |
TW506123B (en) | 2001-10-24 | 2002-10-11 | Macronix Int Co Ltd | Multi-level NROM memory cell and its operating method |
US6791396B2 (en) | 2001-10-24 | 2004-09-14 | Saifun Semiconductors Ltd. | Stack element circuit |
US6653190B1 (en) | 2001-12-15 | 2003-11-25 | Advanced Micro Devices, Inc. | Flash memory with controlled wordline width |
US6535020B1 (en) | 2001-12-18 | 2003-03-18 | Sun Microsystems, Inc. | Output buffer with compensated slew rate and delay control |
US6967872B2 (en) * | 2001-12-18 | 2005-11-22 | Sandisk Corporation | Method and system for programming and inhibiting multi-level, non-volatile memory cells |
US6885585B2 (en) | 2001-12-20 | 2005-04-26 | Saifun Semiconductors Ltd. | NROM NOR array |
US6639271B1 (en) | 2001-12-20 | 2003-10-28 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
US6583007B1 (en) | 2001-12-20 | 2003-06-24 | Saifun Semiconductors Ltd. | Reducing secondary injection effects |
DE10164415A1 (de) | 2001-12-29 | 2003-07-17 | Philips Intellectual Property | Verfahren und Anordnung zur Programmierung und Verifizierung von EEPROM-Pages sowie ein entsprechendes Computerprogrammprodukt und ein entsprechendes computerlesbares Speichermedium |
US6674138B1 (en) | 2001-12-31 | 2004-01-06 | Advanced Micro Devices, Inc. | Use of high-k dielectric materials in modified ONO structure for semiconductor devices |
US6529412B1 (en) | 2002-01-16 | 2003-03-04 | Advanced Micro Devices, Inc. | Source side sensing scheme for virtual ground read of flash eprom array with adjacent bit precharge |
US20030134476A1 (en) | 2002-01-17 | 2003-07-17 | Yakov Roizin | Oxide-nitride-oxide structure |
JP2003224213A (ja) | 2002-01-30 | 2003-08-08 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置 |
US7190620B2 (en) | 2002-01-31 | 2007-03-13 | Saifun Semiconductors Ltd. | Method for operating a memory device |
US6700818B2 (en) | 2002-01-31 | 2004-03-02 | Saifun Semiconductors Ltd. | Method for operating a memory device |
US6975536B2 (en) | 2002-01-31 | 2005-12-13 | Saifun Semiconductors Ltd. | Mass storage array and methods for operation thereof |
US7062619B2 (en) | 2002-01-31 | 2006-06-13 | Saifun Semiconductor Ltd. | Mass storage device architecture and operation |
US6928527B2 (en) | 2002-01-31 | 2005-08-09 | Saifun Semiconductors Ltd. | Look ahead methods and apparatus |
JP4082913B2 (ja) | 2002-02-07 | 2008-04-30 | 株式会社ルネサステクノロジ | メモリシステム |
US6731011B2 (en) | 2002-02-19 | 2004-05-04 | Matrix Semiconductor, Inc. | Memory module having interconnected and stacked integrated circuits |
JP3796457B2 (ja) | 2002-02-28 | 2006-07-12 | 富士通株式会社 | 不揮発性半導体記憶装置 |
US6639844B1 (en) | 2002-03-13 | 2003-10-28 | Advanced Micro Devices, Inc. | Overerase correction method |
US6642573B1 (en) | 2002-03-13 | 2003-11-04 | Advanced Micro Devices, Inc. | Use of high-K dielectric material in modified ONO structure for semiconductor devices |
US6706595B2 (en) | 2002-03-14 | 2004-03-16 | Advanced Micro Devices, Inc. | Hard mask process for memory device without bitline shorts |
TW527722B (en) | 2002-03-20 | 2003-04-11 | Macronix Int Co Ltd | Non-volatile memory device and fabrication method thereof |
US6617215B1 (en) | 2002-03-27 | 2003-09-09 | Advanced Micro Devices, Inc. | Memory wordline hard mask |
US8673716B2 (en) | 2002-04-08 | 2014-03-18 | Spansion Llc | Memory manufacturing process with bitline isolation |
US6690602B1 (en) | 2002-04-08 | 2004-02-10 | Advanced Micro Devices, Inc. | Algorithm dynamic reference programming |
US6799256B2 (en) | 2002-04-12 | 2004-09-28 | Advanced Micro Devices, Inc. | System and method for multi-bit flash reads using dual dynamic references |
JP2003309192A (ja) | 2002-04-17 | 2003-10-31 | Fujitsu Ltd | 不揮発性半導体メモリおよびその製造方法 |
CN1292356C (zh) | 2002-04-17 | 2006-12-27 | 松下电器产业株式会社 | 非易失性半导体存储装置及其机密保护方法 |
US6608526B1 (en) | 2002-04-17 | 2003-08-19 | National Semiconductor Corporation | CMOS assisted output stage |
US6642148B1 (en) | 2002-04-19 | 2003-11-04 | Advanced Micro Devices, Inc. | RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist |
US6670241B1 (en) | 2002-04-22 | 2003-12-30 | Advanced Micro Devices, Inc. | Semiconductor memory with deuterated materials |
US6816423B2 (en) | 2002-04-29 | 2004-11-09 | Fujitsu Limited | System for control of pre-charge levels in a memory device |
JP2003332469A (ja) | 2002-05-10 | 2003-11-21 | Fujitsu Ltd | 不揮発性半導体記憶装置及びその製造方法 |
US6594181B1 (en) | 2002-05-10 | 2003-07-15 | Fujitsu Limited | System for reading a double-bit memory cell |
US6804151B2 (en) | 2002-05-15 | 2004-10-12 | Fujitsu Limited | Nonvolatile semiconductor memory device of virtual-ground memory array with reliable data reading |
US6653191B1 (en) | 2002-05-16 | 2003-11-25 | Advanced Micro Devices, Inc. | Memory manufacturing process using bitline rapid thermal anneal |
JP3967193B2 (ja) | 2002-05-21 | 2007-08-29 | スパンション エルエルシー | 不揮発性半導体記憶装置及びその製造方法 |
US20030218913A1 (en) | 2002-05-24 | 2003-11-27 | Le Binh Quang | Stepped pre-erase voltages for mirrorbit erase |
JP4104133B2 (ja) | 2002-05-31 | 2008-06-18 | スパンション エルエルシー | 不揮発性半導体記憶装置及びその製造方法 |
JP4028301B2 (ja) | 2002-06-11 | 2007-12-26 | 富士通株式会社 | 不揮発性半導体記憶装置及びその消去方法 |
US6570211B1 (en) | 2002-06-26 | 2003-05-27 | Advanced Micro Devices, Inc. | 2Bit/cell architecture for floating gate flash memory product and associated method |
US6917544B2 (en) | 2002-07-10 | 2005-07-12 | Saifun Semiconductors Ltd. | Multiple use memory chip |
US7196369B2 (en) | 2002-07-15 | 2007-03-27 | Macronix International Co., Ltd. | Plasma damage protection circuit for a semiconductor device |
JP4260434B2 (ja) | 2002-07-16 | 2009-04-30 | 富士通マイクロエレクトロニクス株式会社 | 不揮発性半導体メモリ及びその動作方法 |
US6813189B2 (en) | 2002-07-16 | 2004-11-02 | Fujitsu Limited | System for using a dynamic reference in a double-bit cell memory |
US6734063B2 (en) | 2002-07-22 | 2004-05-11 | Infineon Technologies Ag | Non-volatile memory cell and fabrication method |
JP2004079602A (ja) | 2002-08-12 | 2004-03-11 | Fujitsu Ltd | トラップ層を有する不揮発性メモリ |
US6765259B2 (en) | 2002-08-28 | 2004-07-20 | Tower Semiconductor Ltd. | Non-volatile memory transistor array implementing “H” shaped source/drain regions and method for fabricating same |
US6859028B2 (en) | 2002-11-26 | 2005-02-22 | Sige Semiconductor Inc. | Design-for-test modes for a phase locked loop |
JP4113423B2 (ja) | 2002-12-04 | 2008-07-09 | シャープ株式会社 | 半導体記憶装置及びリファレンスセルの補正方法 |
US6731542B1 (en) | 2002-12-05 | 2004-05-04 | Advanced Micro Devices, Inc. | Circuit for accurate memory read operations |
US6885590B1 (en) | 2003-01-14 | 2005-04-26 | Advanced Micro Devices, Inc. | Memory device having A P+ gate and thin bottom oxide and method of erasing same |
US6643177B1 (en) | 2003-01-21 | 2003-11-04 | Advanced Micro Devices, Inc. | Method for improving read margin in a flash memory device |
US6806535B2 (en) | 2003-01-22 | 2004-10-19 | Macronix International Co., Ltd. | Non-volatile memory and fabricating method thereof |
US6842383B2 (en) | 2003-01-30 | 2005-01-11 | Saifun Semiconductors Ltd. | Method and circuit for operating a memory cell using a single charge pump |
US6967896B2 (en) | 2003-01-30 | 2005-11-22 | Saifun Semiconductors Ltd | Address scramble |
US7178004B2 (en) * | 2003-01-31 | 2007-02-13 | Yan Polansky | Memory array programming circuit and a method for using the circuit |
US6803284B2 (en) | 2003-02-10 | 2004-10-12 | Macronix International Co., Ltd. | Method for manufacturing embedded non-volatile memory with two polysilicon layers |
US6859397B2 (en) * | 2003-03-05 | 2005-02-22 | Sandisk Corporation | Source side self boosting technique for non-volatile memory |
US6912160B2 (en) | 2003-03-11 | 2005-06-28 | Fujitsu Limited | Nonvolatile semiconductor memory device |
KR101178080B1 (ko) | 2003-08-13 | 2012-08-30 | 퀄컴 인코포레이티드 | 더 높은 데이터 레이트를 위한 신호 인터페이스 |
US6870772B1 (en) | 2003-09-12 | 2005-03-22 | Renesas Technology Corp. | Nonvolatile semiconductor memory device |
US6954393B2 (en) | 2003-09-16 | 2005-10-11 | Saifun Semiconductors Ltd. | Reading array cell with matched reference cell |
US6906357B1 (en) | 2003-10-10 | 2005-06-14 | National Semiconductor Corporation | Electrostatic discharge (ESD) protection structure with symmetrical positive and negative ESD protection |
US6930928B2 (en) | 2003-10-10 | 2005-08-16 | Macronix International Co., Ltd. | Method of over-erase prevention in a non-volatile memory device and related structure |
US6930925B2 (en) * | 2003-10-14 | 2005-08-16 | Atmel Corporation | Suspend-resume programming method for flash memory |
US6937523B2 (en) | 2003-10-27 | 2005-08-30 | Tower Semiconductor Ltd. | Neighbor effect cancellation in memory array architecture |
KR100562636B1 (ko) | 2003-12-30 | 2006-03-20 | 주식회사 하이닉스반도체 | 반도체 메모리 소자의 파워업 회로 |
CA2775734C (en) | 2004-03-10 | 2014-01-07 | Qualcomm Incorporated | High data rate interface apparatus and method |
US7755938B2 (en) | 2004-04-19 | 2010-07-13 | Saifun Semiconductors Ltd. | Method for reading a memory array with neighbor effect cancellation |
US7020026B2 (en) * | 2004-05-05 | 2006-03-28 | Sandisk Corporation | Bitline governed approach for program control of non-volatile memory |
US20060084219A1 (en) | 2004-10-14 | 2006-04-20 | Saifun Semiconductors, Ltd. | Advanced NROM structure and method of fabrication |
US7242618B2 (en) | 2004-12-09 | 2007-07-10 | Saifun Semiconductors Ltd. | Method for reading non-volatile memory cells |
US7257025B2 (en) | 2004-12-09 | 2007-08-14 | Saifun Semiconductors Ltd | Method for reading non-volatile memory cells |
US8686242B1 (en) | 2012-03-01 | 2014-04-01 | Pioneer Hi-Bred International Inc | Soybean variety XBP38011 |
-
2003
- 2003-10-29 US US10/695,449 patent/US7136304B2/en not_active Expired - Lifetime
-
2004
- 2004-10-27 CN CNA2004800394008A patent/CN1902711A/zh active Pending
- 2004-10-27 JP JP2006537552A patent/JP2007510252A/ja active Pending
- 2004-10-27 EP EP04791843A patent/EP1683159A4/en not_active Withdrawn
- 2004-10-27 WO PCT/IL2004/000981 patent/WO2005041206A2/en active Application Filing
- 2004-10-28 TW TW093132724A patent/TWI371755B/zh active
-
2006
- 2006-10-17 US US11/581,449 patent/US7675782B2/en not_active Expired - Fee Related
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101620888A (zh) * | 2008-07-03 | 2010-01-06 | 旺宏电子股份有限公司 | 多位阶单元存储器的读取方法及应用其的读取电路 |
CN101620888B (zh) * | 2008-07-03 | 2012-09-05 | 旺宏电子股份有限公司 | 多位阶单元存储器的读取方法及应用其的读取电路 |
CN102203874A (zh) * | 2008-10-24 | 2011-09-28 | 桑迪士克股份有限公司 | 以高分辨率可变初始编程脉冲对非易失性存储器编程 |
CN102203874B (zh) * | 2008-10-24 | 2014-05-14 | 桑迪士克股份有限公司 | 以高分辨率可变初始编程脉冲对非易失性存储器编程 |
CN102483953A (zh) * | 2009-06-26 | 2012-05-30 | 桑迪士克技术有限公司 | 检测对非易失性储存器的编程的完成 |
CN102483953B (zh) * | 2009-06-26 | 2015-06-24 | 桑迪士克技术有限公司 | 检测对非易失性储存器的编程的完成 |
USRE45603E1 (en) | 2009-06-26 | 2015-07-07 | Sandisk Technologies Inc. | Detecting the completion of programming for non-volatile storage |
CN103310839A (zh) * | 2012-03-15 | 2013-09-18 | 旺宏电子股份有限公司 | 缩短擦除操作的方法与装置 |
CN103310839B (zh) * | 2012-03-15 | 2016-01-20 | 旺宏电子股份有限公司 | 缩短擦除操作的方法与装置 |
CN103928042A (zh) * | 2013-01-16 | 2014-07-16 | 旺宏电子股份有限公司 | 一种操作多位存储单元的方法 |
CN105989879A (zh) * | 2015-02-06 | 2016-10-05 | 华邦电子股份有限公司 | 高可靠性非易失性半导体存储装置及其数据抹除方法 |
CN105989879B (zh) * | 2015-02-06 | 2019-10-11 | 华邦电子股份有限公司 | 高可靠性非易失性半导体存储装置及其数据抹除方法 |
Also Published As
Publication number | Publication date |
---|---|
US20070115726A1 (en) | 2007-05-24 |
TW200535848A (en) | 2005-11-01 |
JP2007510252A (ja) | 2007-04-19 |
WO2005041206A2 (en) | 2005-05-06 |
US7136304B2 (en) | 2006-11-14 |
EP1683159A2 (en) | 2006-07-26 |
TWI371755B (en) | 2012-09-01 |
WO2005041206A8 (en) | 2005-06-30 |
EP1683159A4 (en) | 2007-03-21 |
US20050105337A1 (en) | 2005-05-19 |
WO2005041206A3 (en) | 2005-06-02 |
US7675782B2 (en) | 2010-03-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN1902711A (zh) | 用于对非易失性存储器阵列编程的方法、系统和电路 | |
CN1822233A (zh) | 一种擦除一个或多个非易失存储器单元的方法、电路和系统 | |
CN100587841C (zh) | 非易失存储器器件及其编程方法 | |
US8498163B2 (en) | Semiconductor memory apparatus and data erasing method | |
CN1825484A (zh) | 一种存储设备的操作方法 | |
CN1941204A (zh) | 同时编程与编程验证的非易失性存储器 | |
CN107731252B (zh) | 非易失性存储器设备和包括其的存储设备 | |
CN1494720A (zh) | 闪存阵列中的核心存储单元的软程序及软程序校验 | |
CN1902710A (zh) | 用于非易失性存储器阵列中的读取误差检测的方法、电路和系统 | |
CN1460268A (zh) | 改进编程的非易失性存储器及为此的方法 | |
CN103477392A (zh) | 具有减少的验证的改进的编程的非易失性存储器和方法 | |
US9792999B2 (en) | Adaptive scheme for incremental step pulse programming of flash memory | |
US20130044544A1 (en) | Nonvolatile memory device | |
CN1870177A (zh) | 快闪存储器装置的编程方法 | |
CN106486169B (zh) | 一种Nand Flash的擦除方法 | |
CN103489479A (zh) | 半导体存储器件及其操作方法 | |
KR20100056860A (ko) | 비휘발성 메모리 소자의 프로그램 방법 | |
US20120195118A1 (en) | Semiconductor memory apparatus, data programming method thereof, and memory system including the same | |
US10943650B2 (en) | Method for programming memory system | |
JP2022528898A (ja) | マルチレベルセルnand型フラッシュメモリデバイスのプログラム方法及びmlc nand型フラッシュメモリデバイス | |
CN110140174A (zh) | 用于通过施加多个位线偏置电压在非易失性存储器器件中编程的方法 | |
CN111081303B (zh) | 存储器编程方法、装置、电子设备及计算机可读存储介质 | |
US20090323431A1 (en) | Non-volatile memory device and program method thereof | |
Park et al. | Adaptive program verify scheme for improving NAND flash memory performance and lifespan | |
KR100546343B1 (ko) | 플래시 메모리 장치의 프로그램 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |