CN1890808A - 改进电源布线的方法和装置 - Google Patents
改进电源布线的方法和装置 Download PDFInfo
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Abstract
一种装置包括:含有顶端金属层的管芯,顶端金属层最少由第一金属线和第二金属线组成;覆盖顶端金属层的钝化层;位于钝化层上的C4凸块;在钝化层有第一钝化层开口和第二钝化层开口,第一钝化层开口将第一金属线连到C4凸块,第二钝化层开口将第二金属线连到C4凸块。
Description
发明领域
本发明一般涉及半导体封装领域,尤其涉及C4凸块和半导体管芯间的互连。
相关技术论述
当今,半导体管芯通过二维C4凸块阵列和倒装芯片封装连接起来。电源通过这些C4凸块通过封装布线到芯片。电源通过管芯顶端金属层中的金属互连线从这些C4凸块进一步分布到管芯的不同部分。
图1示出了C4凸块102和管芯100的顶端金属层之间的连接。目前该连接通过单个钝化层开口完成,如图1所示。C4凸块102通过单个钝化层开口106和顶端金属层中的金属线104相连。通常,C4凸块102的直径为110微米。顶端金属层上的线宽20微米,钝化层开口106面积大约为256平方微米(16微米×16微米)。
电源经由多层金属层布线通过管芯。顶层的两层金属层如图1所示。顶层金属层上的金属线104将电源分布到较低金属层上的金属线上,包括top-1金属层上的金属线112。因此,电源从C4凸块102经过单个钝化开口106到达管芯的顶端金属线104,然后再布线到top-1金属层线112和其它较低层的金属线。
电流密度与电源网格可靠传送电流的能力取决于金属叠层,金属EM(电迁移)能力以及金属叠层上通孔。目前电迁移问题有几种方法解决。比如,对于单个钝化层开口连接,当电流聚集超过电迁移的容限时,可以往金属叠层上添加附加金属层来降低电流聚集,然而这可能会增加制造成本。另一个可选的降低电流聚集的方法是用一块厚些的金属层或增加金属线的间距。这可能会不良地降低信号布线能力。另一个办法是掺杂金属层使其允许更大的电迁移容限。金属层掺杂可能会增加金属线电阻,这是不希望看到的。
附图简述
图1示出了连接到管芯顶端金属层的C4凸块阵列的俯视图。
图2示出了根据本发明一个实施例的连接到管芯顶端金属层的C4凸块的俯视图。
图3示出了根据本发明一个实施例的连接到管芯顶端金属层的C4凸块的俯视图。
图4示出了根据本发明一个实施例的连接到管芯顶端金属层的C4凸块的剖面图。
图5示出了根据本发明一个实施例的连接到管芯顶端金属层的C4凸块阵列的俯视图。
图6示出了根据本发明一个实施例的将管芯连接到封装的C4凸块的剖视图。
图7示出了根据本发明一个实施例的方法的流程图。
具体实施方式
在下面的描述中,为了使对本发明有一个全面的理解,将描述大量具体细节,比如精确的工艺步骤。然而对于该领域的技术人员来说显见的是,不需要这些具体细节来实施本发明。在其他场合,一些公知组件或方法将不再详细说明以避免不必要地掩盖本发明。
描述了一种通过多钝化层孔将单个C4凸块连接到管芯顶端金属层上的多条金属线的方法,以及形成这种连接的方法。将多钝化层开口用于连接单个C4凸块可以降低管芯和封装之间的电阻。电流聚集和较低金属层上的IR(电压)压降同样可以通过采用多钝化层开口来降低。不需要附加金属层来降低电流聚集或IR压降。
图2示出了根据本发明一个实施例的含有附着其上的C4凸块202的管芯200连接到管芯上的顶视图。在本发明的一个实施例中,C4凸块可能由焊料组成。在本发明的另一个实施列中,C4凸块可能由另一种导电材料构成,如铜。C4凸块可以有大约为110um的直径。C4凸块202可以通过钝化层中的钝化层开口206和多条顶层金属线204相连。C4凸块下两个钝化层开口的各自尺寸可能近似相等,也可能不一样。在一个实施例中,C4凸块下两个钝化层开口中的每一个可以约为6um宽,30um长。钝化层开口可能比金属线204的宽度要窄。两个钝化层开口的总面积可能大约近似为360um2。一个钝化层开口206可提供用于与C4凸块相连的每条金属线204。顶端金属层中的金属线204基本相互平行走线。在本发明的一个实施例中,顶层金属线大约为10um宽,并且相隔大约50um。金属线204可以由铜或其他导电材料构成。
和用单钝化层开口以及单金属线相比,用多钝化层开口将C4凸块连接到多金属线会增加C4凸块和金属线间的总连接面积。总连接面积的增加也会有效降低封装与管芯间的电阻。
图3示出了本发明的另一个实施例。两个或多个钝化层开口206可以用来连接C4凸块202和单根金属线204。这同样可以通过增加C4凸块和金属线间的总连接面积来有效降低封装和管芯间的电阻。
钝化层开口206中的每一个开口可以是同样的大小,也可能大小不同。如图3所示的钝化层开口206相互间直立放置,钝化层开口206同样可以相互水平放置,即并行钝化层开口结构。
图4示出了图2中管芯的剖视图。管芯200包括一个衬底201和顶端金属层金属线204。管芯200还可以包含多条附加的较低层金属线,比如top-1金属线212。金属叠层中的金属线通过通孔213彼此相连。通孔213将顶层金属线204连接到top-1金属线212。集成电路250,比如晶体管或电容,可以在衬底201中生成。集成电路可以通过通孔213连接到金属叠层中的金属层。
在管芯200顶层表面上形成的钝化层210保护管芯表面免受外部污染和灰尘。开口206在钝化层中形成,以使C4凸块202可以连接到多根顶层金属线204。在本发明的一个实施例中,C4凸块可能设置于两个钝化层开口上方使其可以连接到两根金属线。在其它实施例中,C4凸块可以通过两个以上的钝化层开口连接到两根以上的金属线。可以提供至少一个钝化层开口以将C4凸块连接到每条金属线。在另一实施例中,可提供多个钝化层开口以将C4凸块连接到每根金属线。在一个实施例中,焊球受限冶金(BLM)215可位于C4凸块的下面。BLM层可由以下材料构成,钛、钒、铝或者氮化物,但并不局限于这几种材料。
图5示出了根据一个实施例的含有高功率区和低功率区的管芯500的俯视图。在管芯的高功率区中,为了电源连接和接地连接,多个钝化层开口510被用于将每个C4凸块503连接到管芯顶端金属层上的多根金属线508A或508B。管芯的高功率区可以定义为在C4凸块周围局部区域和下面的金属层中需要较低电流密度的那些区域。管芯的高功率区的电流密度一般是管芯低功率区电流密度的3到4倍。
本发明的实施例降低了顶端金属层和紧临顶端金属层的下面那层金属层的电流密度和电流聚集。比如,对于一个有八层金属层的管芯,当电流聚集超过了第7层金属层的EM(电迁移)容限时,就需要采用多个钝化层开口将C4凸块连接到顶端第八层金属层上的多根金属线。在用多钝化层开口将单个C4凸块连接到顶端金属层上的多金属线的情况中,电流聚集降幅可达90%。管芯高功率区也可以定义为那些需要较低IR压降的区域。本发明实施例在采用多钝化层开口连接C4凸块和顶端金属层上的多金属线的区域降低IR压降。仿真显示IR压降性能将提高60%。这种提高是由于增大的钝化层开口从而降低了最高两层金属层的电阻而引起的。
在一个实施例中,位于管芯高功率区的C4凸块503各自通过两个钝化层开口510连接到顶端金属层上的两条窄金属线508A或508B。在本发明的一个特定实施例中,连接单个C4凸块和两根窄金属线的每个钝化层开口510大约为6um×30um大小,或总面积约为360um2。因此,与低功率区的连接面积相比,在管芯高功率区中,本发明的实施例可以用来增加C4凸块和管芯间的总连接面积。
管芯高功率区520的电源端(Vcc)和接地端(Vss)通过交替的细窄顶端金属线对508A和508B分布到管芯上。窄金属线508A是电源线(Vcc),窄金属线504B是地线(Vss)。在高功率区,窄金属线508A和508B相互平行走线,大约为10um宽。窄金属线508A间的间隔和窄金属线508间的间隔可在20um到70um之间,尤其可大约为50um。金属线508将电源端分布到较低金属层,包括金属线512。金属线512在top-1金属层上,即紧邻顶端金属层的下面一层金属层,并且和顶层金属线508基本垂直走线。在管芯高功率区,电源线必须在顶端层Vcc和Vss C4凸块之间top-1金属线512上行进一段距离DH,来完成电流通路。在一个实施例中,这个距离大约为114um。因此,在高功率区,当每个C4凸块下有多个钝化层开口时,电源线在top-1层金属线上行进的距离要比仅有一个单钝化层开口时短30%。因为通过采用多钝化层开口连接C4凸块和多根金属线可以明显减少top-1金属层上电源线必须行进的距离,所以top-1金属层上的IR(电压)压降和电流聚集得以降低。另外,当采用多钝化层开口拓扑结构时,top-1金属线512的宽度可以减小大约30%,以有效地将电源引入到管芯。这允许在top-1金属层上路由更多数量的信号。
在一个实施例中,管芯500还可以包括一个低功率区。低功率区是那些EM容限和IR压降被确定为适当因此EM余量和IR压降不需要降低的区域。在低功率区,单个钝化层开口506可以用来连接每个C4凸块502和管芯顶端金属层上的单根金属线504A或504B用于电源和接地连接。单个钝化层开口也可以用于和管芯上的I/O信号线相连的C4凸块。在本发明的一个实施例中,连接单个C4凸块和单根宽金属线的每个钝化层开口506可大约16um×16um大小,或大约为256um2。管芯低功率区510的电源端和接地端通过交替的宽顶端金属线504A和504B分布到管芯上。宽金属线504A是电源线(Vcc),宽金属线504B是接地线(Vss)。在管芯低功率区,电源线必须在顶层Vcc和Vss C4凸块之间top-1金属线512上行进一段距离DL。在一个实施例中,这个距离大约为160-170um。在低功率区,金属线504A和504B基本相互平行走线,可大约20um宽。宽金属线504的间隔大约为70-75um。金属线504将电源端分布到较低金属层,包括金属线512。top-1金属层上的金属线512位于紧邻顶端金属层的下面,并且基本垂直于顶层金属线504走线。
图6示出了根据本发明实施例的管芯和封装的剖视图。C4凸块602和603将倒装芯片封装620连接到管芯600。电源端可以通过C4凸块和C4凸块下的钝化层开口从倒装芯片封装620分布到多根顶层金属线。电源端然后可以进一步分布到整个管芯,从顶端金属层金属线到位于顶端金属层下的其他金属层,包括top-1金属层612。top-1金属层612通过通孔613和顶层金属线608相连。
对照图5如上所述,在管芯的高功率区,为了电源连线和接地连线,多个钝化层开口610可用于将每个C4凸块603连接到管芯顶端金属层上的多根金属线608。如上所述,在低功率区中为了电源连接和接地连接,单个钝化层开口606可用于将C4凸块602连接到管芯600顶端金属层上的单根金属线604。单个钝化层开口也可以用于连接到管芯上的I/O信号线的C4凸块。
图7是一个流程图700,示出了根据本发明实施例的过程。首先,如在框710中所述,将钝化层形成于半导体管芯的顶层表面。半导体管芯可以包括金属线、集成电路或者其他电路元件。钝化层可以在管芯的顶层表面生长或淀积。
其次,如框720所述,钝化层开口可以形成于钝化层中。钝化层开口可以使用常规平版印刷工艺通过形成图案而形成。钝化层开口可以是任何形状或大小,只要它们不比覆盖钝化层开口的C4凸块大。在实施例中,钝化层开口形状可以为方形、矩形、八边形或圆形。钝化层开口的大小可以从大约50um2到500um2。生成后,钝化层开口将暴露出管芯顶端金属层上的金属线。
钝化层开口生成后,可将多个C4凸块放置在管芯顶层表面的钝化层上面,如框730所述。在这些高功率区,如上所述,每个C4凸块可以覆盖至少两个钝化层开口,并可以连接到至少两根顶层金属线。在低功率区,或者对于I/O信号线,每个C4凸块可以只覆盖一个钝化层开口,并可以只连接到一根顶层金属线。
最后,如框740中所述,封装可放置在管芯和C4凸块上面,使得C4凸块电连接管芯和封装。
本发明可以由所述实施例经过不同改动和替代后实现。比如,像半导体技术可以按比例缩小至更小尺寸一样,在这里提到的尺寸也可以按比例缩减。虽然已经叙述了特定的实施例,包括特定的参数、方法和材料,然而该技术领域的技术人员和得益于这些公开内容的人很容易明白,所描述和说明的用来解释本发明实质的一些在细节上、材料上、材料的布置上和步骤上的不同改动,是不能脱离所附权利说明书中所描述的本发明的原理和范围的。
Claims (32)
1.一种装置,包括:
具有顶端金属层的管芯,所述顶端金属层至少由第一金属线和第二金属线组成;
覆盖所述顶端金属层的钝化层;
所述钝化层上的C4凸块;以及
所述钝化层中的第一钝化层开口和第二钝化层开口,所述第一钝化层开口将所述第一金属线连接到所述C4凸块,且所述第二钝化层开口将所述第二金属线连接到所述C4凸块。
2.如权利要求1所述的装置,其特征在于,所述第一和第二金属线由铜构成。
3.如权利要求1所述的装置,其特征在于,所述C4凸块由焊料构成。
4.如权利要求1所述的装置,其特征在于,所述C4凸块由导电材料构成。
5.如权利要求1所述的装置,其特征在于,所述C4凸块的直径小于120um。
6.如权利要求1所述的装置,其特征在于,所述第一金属线和所述第二金属线基本相互平行。
7.如权利要求1所述的装置,其特征在于,所述第一金属线和所述第二金属线小于10um宽。
8.如权利要求6所述的装置,其特征在于,所述第一金属线和所述第二金属线相隔小于50um。
9.一种装置,包括:
具有顶端金属层的管芯,所述顶端金属层至少由第一金属线和第二金属线组成;
覆盖所述顶端金属层的钝化层,所述钝化层包括多个钝化层开口;以及
位于所述钝化层上的多个C4凸块,每个C4凸块覆盖至少两个钝化层开口,并至少被连接到所述第一金属线和所述第二金属线。
10.如权利要求9所述的装置,其特征在于,进一步包括紧邻于所述顶端金属层下的第二金属层。
11.如权利要求9所述的装置,其特征在于,所述第二金属层由多个基本垂直于所述第一金属线和第二金属线走线的金属线组成。
12.如权利要求11所述的装置,其特征在于,所述第一金属线、所述第二金属线以及所述多条金属线由铜构成。
13.如权利要求9所述的装置,其特征在于,所述多个C4凸块中的每一个由导电材料构成。
14.如权利要求9所述的装置,其特征在于,所述多个C4凸块中的每一块由焊料构成。
15.如权利要求13所述的装置,其特征在于,所述多个C4凸块中的每一个的直径都小于120um,并且离另一块C4凸块小于75um。
16.如权利要求9所述的装置,其特征在于,所述第一金属线和所述第二金属线基本相互平行。
17.如权利要求9所述的装置,其特征在于,所述第一金属线和所述第二金属线小于10um宽。
18.如权利要求9所述的装置,其特征在于,所述第一金属线和所述第二金属线相隔小于50um。
19.一种装置,包括:
管芯,它具有高功率区、低功率区以及顶端金属层;
第一金属线和第二金属线,它们位于所述高功率区的顶端金属层上;
第三金属线,它位于所述低功率区的顶端金属层上;
覆盖所述顶端金属层的钝化层,所述钝化层包括多个钝化层开口;
位于所述高功率区中的钝化层上的C4凸块,所述C4凸块覆盖至少两个钝化层开口,并至少连接到所述第一金属线和所述第二金属线;以及
位于所述低功率区中的钝化层上的C4凸块,所述C4凸块覆盖一个钝化层开口并连接到所述第三金属线。
20.如权利要求19所述的装置,其特征在于,所述金属线由铜构成。
21.如权利要求19所述的装置,其特征在于,所述C4凸块由焊料构成。
22.如权利要求19所述的装置,其特征在于,所述C4凸块由导电材料构成。
23.如权利要求19所述的装置,其特征在于,所述C4凸块直径小于120um。
24.如权利要求19所述的装置,其特征在于,所述第一金属线和所述第二金属线每一根都比第三金属线窄。
25.一种方法,包括:
在半导体器件的顶层表面上形成钝化层,所述半导体器件的顶端表面包含多条金属线;
在所述钝化层中形成多个钝化层开口以将所述多条金属线中的每一条的一些部分暴露出来;以及
将C4凸块放置在所述钝化层上,使得所述C4凸块被置于所述多个钝化层开口的至少两个上并连接到所述多条金属线中的至少两条。
26.如权利要求25所述的方法,其特征在于,所述多条金属线基本相互平行走线。
27.如权利要求26所述的方法,其特征在于,所述多条金属线由铜构成。
28.如权利要求25所述的方法,其特征在于,所述多条金属线中的每条金属线小于10um宽。
29.如权利要求25所述的方法,其特征在于,所述多条金属线中的每条金属线彼此相距小于50um。
30.如权利要求25所述的方法,其特征在于,所述C4凸块由导电材料构成。
31.如权利要求25所述的方法,其特征在于,所述C4凸块由焊料构成。
32.如权利要求25所述的方法,其特征在于,所述C4凸块直径小于120um。
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-
2003
- 2003-12-17 US US10/739,726 patent/US7180195B2/en not_active Expired - Lifetime
-
2004
- 2004-08-20 TW TW093125197A patent/TWI255517B/zh active
- 2004-11-24 CN CNB2004800360942A patent/CN100477190C/zh active Active
- 2004-11-24 DE DE112004002466T patent/DE112004002466B4/de active Active
- 2004-11-24 WO PCT/US2004/039639 patent/WO2005062381A2/en active Application Filing
- 2004-11-24 JP JP2006543858A patent/JP4563400B2/ja not_active Expired - Fee Related
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112242375A (zh) * | 2020-10-19 | 2021-01-19 | Oppo广东移动通信有限公司 | 芯片和电子设备 |
Also Published As
Publication number | Publication date |
---|---|
WO2005062381A3 (en) | 2005-10-27 |
CN100477190C (zh) | 2009-04-08 |
TW200522235A (en) | 2005-07-01 |
TWI255517B (en) | 2006-05-21 |
JP4563400B2 (ja) | 2010-10-13 |
DE112004002466B4 (de) | 2013-08-14 |
WO2005062381A2 (en) | 2005-07-07 |
US7180195B2 (en) | 2007-02-20 |
US7208402B2 (en) | 2007-04-24 |
US20050233570A1 (en) | 2005-10-20 |
US20050133894A1 (en) | 2005-06-23 |
DE112004002466T5 (de) | 2008-03-27 |
JP2007514318A (ja) | 2007-05-31 |
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