CN1885532A - 线路组件结构制造方法及其结构 - Google Patents

线路组件结构制造方法及其结构 Download PDF

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CN1885532A
CN1885532A CNA200610090122XA CN200610090122A CN1885532A CN 1885532 A CN1885532 A CN 1885532A CN A200610090122X A CNA200610090122X A CN A200610090122XA CN 200610090122 A CN200610090122 A CN 200610090122A CN 1885532 A CN1885532 A CN 1885532A
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Prior art keywords
metal
microns
layer
connection pad
metal cartridge
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CN1885532B (zh
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林茂雄
周健康
陈科宏
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Qualcomm Inc
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Megica Corp
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Abstract

本发明涉及一种线路组件结构制造方法及其结构,该方法包括提供一基板,在该基板上设置至少第一金属柱及第二金属柱,此第一金属柱的最大横向尺寸除以第一金属柱及第二金属柱高度的比值小于4,且第一金属柱的高度介于20微米至300微米之间,且第一金属柱的中心点至第二金属柱的中心点之间的距离介于10微米至250微米之间。本发明因可将金属柱体之间距缩小至250微米以下,且可达到针孔数目少于400个的目标。并能有效改善集成电路的性能,且可大幅降低低电源IC组件的IC金属连接线路的阻抗及荷载。

Description

线路组件结构制造方法及其结构
技术领域
本发明涉及一种线路组件结构制造方法及其结构,特别涉及一种能有效改善集成电路性能的线路组件的制造方法及其结构。
背景技术
半导体晶圆片是可用以制造出持续增加密度且缩小几何特征图案的集成电路,借由多层的导电层与绝缘层的结构可分别提供位于不同层上的半导体组件之间的内部连接与隔绝的效果,例如:主动与被动组件,像薄膜晶体管、互补金氧半导体、电容、电感器、电阻等等的大规模集成电路中,在不同层状结构与半导体组件之间是需要增加多个电性连接部,且同时,对于组合式的集成电路芯片而言,亦需要增加大量的导线,这些导线穿越出集成电路芯片中的保护层并裸露在外,而最后则是终止在输入输出接垫上,此导线是用来与芯片封装的外部接触结构进行连接。
晶圆级封装,即为所谓的以晶圆级的方式封装一集成电路芯片的技术,而非传统的在将晶圆片先切割后而在进行单一单元的封装制造方法,因此,在将晶圆片切割为单一单元以供组装为最终的芯片承载封装之前,例如:在进行球栅数组封装之前,晶圆级封装即可将晶圆片制造、封装、测试与晶圆级预烧进行整合,其优点包含:借由缩小所占的体积与厚度以获得较小的尺寸、较轻的重量、相对简化的组装制造方法、较低的整体生产成本以及在电性上可获得有较佳的表现,且晶圆级封装是简化了一个组件自硅材料开始运送到客户手中的流程,可使集成电路芯片封装的产量提升且成本降低,由此,其导致在制造能力与结构可靠度方面,面临到相当大的挑战。
晶圆级封装基本上可扩张涵盖到晶圆制造方法中的组件连接制造方法与组件保护制造方法,在晶圆级封装的第一步骤中,其是借由半导体集成电路中的重配置线路技术后护层,以加大标准的接垫间距,因此,较低成本的模板印刷焊锡或是定位式的焊锡系可实现。针对重配置线路技术的揭露,举例来说,在美国专利案号第6,645,136号、第6,784,087号与第6,818,545号中的申请人,皆与本发明的申请人相同,而正如本专利所揭露的,一重配置线路层是与半导体结构中的输入输出接垫连接,此重配置线路层是形成在后护层上的聚合物层或弹性材质层上,而一柱状的接触窗是利用光罩制造方法以形成在此重配置线路层上,此反应后形成的柱状接触窗的侧面方向上为独立而未有任支撑的,并且借由覆晶组装技术,上述的反应后所形成的结构体则更可进一步组装至一芯片承载封装结构上。纵使此后护层结构与其所对应的制造方法可在集成电路封装中提供解决改善间距的方法,然而,在持续增加集成规模要求下的集成电路中,势必将面对更为严苛的细间隙标准要求,而针对此点,则必定会遭遇到相当的限制,且对于因应力诱导而产生的损坏而言,亦为一种潜在的风险。
美国专利案号第6,103,552揭露另一种包含有重配置线路层的后护结构的晶圆级封装制造方法,此重配置线路层是形成在后护层上的聚合物层上,而在重配置线路层上则是覆盖有另一聚合物层,且此聚合物层是经过蚀刻或是钻孔以形成微通孔,并填充金属以穿透微通孔的孔隙而形成内连接,也就是所谓的导电柱体,而上聚合物层与下聚合物层是借由一铬-铜层以隔离而不与重配置线路层接触,贴附在上述的导电柱体突出尾端的锡铅凸块是由无电镀、网板印刷或是模板印刷等法形成的;由于导电柱体是延伸至聚合物层外,除此之外,上述结构的顶表面并不平滑,因此,在高分辨率的影印成像无法达成前提下,导电柱体形成微通孔、以电镀形成锡铅凸块皆无法达成,最终,集成电路封装中的接触窗间距将受到限制,且此限制是随着聚合物层厚度的增加而变得更为显著,然而,随聚合物层厚度的增加是可以提供较令人满意的应力释放,关于此将于以下详述。再者,承上所述,下聚合物层是与上聚合物层隔离,因此,下聚合物层将无法单独提供较佳的应力释放,且若当下聚合物层的厚度制作得较为薄以降低重配置线路层的侧向位移,则会导致应力释放变得较差,所引起的问题将于以下进行讨论。
结构可靠度中的其中一种挑战为提供足够的应力释放,以供给上述晶圆级封装制造方法后形成的多层结构,其是包含半导体集成电路晶粒与额外的后护结构,举例说明,结合在保护层上的薄膜是受到双轴向应力所影响,且此应力为由热所诱导而产生的。在式(1)中表示出在后护层的薄膜中的双轴向热应力的数学理论模拟方程式,其提供接合在集成电路芯片中硅基材上的结构的多种物理参数:
σ ppt = 1 6 R Y s x Si 2 ( 1 - v Si ) x ppt
其中,
ppt=x=y,后护层薄膜中的双轴应力;
R=硅基板受热弯曲的曲率半径;
Ys=硅基板的杨氏系数(Young’s modulus);
vsi=硅基板的蒲松比(Poisson’s ratio);
xSi=硅基板的厚度;以及
xppt=后护层薄膜的厚度。
基于上述的方程式可知,除了增加硅基板的蒲松比外,有两种方式可用以降低双轴向应力,(a)降低xSi,其表示必须将硅基板变得更薄,或是(b)提高xppt,其表示必须增加后护薄膜结构的厚度。
图1揭示出现有技术的后护层结构10,其包含一重配置线路层12与一应力释放聚合物层14,此应力释放聚合物层14亦可称为应力缓冲层,且形成在半导体集成电路芯片18顶表面的一保护层16上,其中,聚合物层14可由弹性材料、环氧树脂、低介电系数材料或是其它聚合物材料构成,具有弹性的材料主要是用以提供此接合结构具备足够的机械弹性,且诚如上述的式(1)中所推论的结果,当集成电路芯片18上覆盖有聚合物层14时,此集成电路积片18与形成于其上的结构所产生的应力皆可被吸收或是缓冲,以降低集成电路芯片18发生局部的损坏,而尤其是对于精细繁复的集成电路芯片18的电路而言,后护结构10的可靠度可因此获得提升。此外,依据式(1)中所提出的关系式可知,缓冲效应的表现将随着聚合物层14厚度的增加而变得更好。
然而在应用厚聚合物层14时,通常会面临到一个问题。如图1中所示的重配置线路层12是通常由铜所构成,其用以将位于集成电路芯片18上的输入输出接垫20连接至外部电路。当接垫20的最顶端上同时或分别形成有锡铅凸块或铜导电柱体时,重配置线路层12可与下一层的封装结构连结得相当紧密,其中的封装结构可为一芯片承载,因此,重配置线路层12是借由聚合物层14所定义出的具有一定斜度的斜坡22,以将此重配置线路层12自像是形成有输入输出接垫20的一个较低的集成电路平面,逐渐上升至一较高的集成电路平面,例如:聚合物层14的顶部,此斜坡22的斜度是由金属化步骤以覆盖在厚聚合物层14的开口上所决定。在实际的应用上,斜坡22的斜度是会随着每一个聚合物层14开口不同而改变,而每一个开口则是决定于实际的制造方法条件与聚合物本身根本的物理性质与特性,例如:与材料表面能量有关的湿润接触角;举例说明,在许多的状况下,在集成电路保护层16上聚合物层14的斜坡22具有约为45度的斜度,因此,重配置线路层12必须借由一定量的侧向位移以延伸自集成电路中的接垫20至厚聚合物层14的顶端,故,此侧向位移迫使在重配置线路层12的布局上必需允许一定量的容许值,最终,由于此容许值必须要能够提供具有不同开口的聚合物层14形成各种的斜坡22斜率、各个重配置线路层具有不同的侧向位移,使得相邻的接触窗结构之间的间距将受到限制,其中,接触窗可共同或分别由锡铅凸块、铜柱所定义,且接触窗结构与保护层上的开口之间的间距亦随之增加,因此,此结果造成后护结构与下一层的封装结构之间,无法具有微小的结构间距;相反地,如果厚聚合物层并未被采用时,将造成应力缓冲不足而导致精细的集成电路芯片中的电路因受到应力诱导而发生损坏,且对于大的导电柱体而言,由于其侧向支撑力不足而使得输入输出结构间距将受到限制,然而,大的导电柱体结构系为必须的,因为其可以提供充足的距离以降低输入输出接垫20与集成电路芯片18中的电性电路之间所产生的耦合电容。
上述所提出的议题是针对后护层结构上的接触窗结构之间的间距缩减而导致的问题,也因为如此,亦使得集成电路中的集成规模的提升受到阻碍。
有鉴于此,欲提出一种晶圆级封装结构及其相对应的制造方法,以同时改善应力释放、达到接触窗结构间距的微小化。
发明内容
本发明的主要目的是提供一种线路组件结构制造方法及其结构,其可提供应力的释放与微小化的接触窗结构之间的间距,依据本发明,其间距小于250微米,且可达到针孔数目少于400个的目标。
本发明的另一目的是提供一种线路组件结构制造方法及其结构,其包含一重配置线路(RDL)支撑的后护层结构,是在保护层上形成一相对厚度较为薄的支撑层,如:聚合物层,以用来支撑重配置线路结构之间的细间隙,且具有一相对厚度较为厚的支撑层,如:聚合物层,以使得位于相邻层状封装结构之间的重配置线路结构之间的细间隙可获得支撑。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底、位于该半导体基底上的一金属层、及位于该半导体基底上及该金属层上的第一聚合物层;研磨该第一聚合物层;形成第二聚合物层在该第一聚合物层上,位于该第一、第二聚合物层内有一开口暴露出该金属层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底及位于该半导体基底上的一金属柱,其中该金属柱的最大横向尺寸除以该金属柱高度的比值小于4,且该金属柱的高度介于20微米至300微米之间;形成第一绝缘层在该半导体基底上,且包覆该金属柱;形成第二绝缘层在该第一绝缘层上,位于该第一、第二绝缘层内的一开口暴露出该第一金属柱。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体晶圆、位于该半导体晶圆上提供第一金属层、位于该半导体晶圆上及该第一金属层上提供一聚合物层,其中该半导体晶圆包括复数晶体管,形成该些复数晶体管包括掺杂三价或五价离子至该半导体晶圆;研磨该聚合物层;形成第二金属层在该聚合物层及该第一金属层上;形成一图案定义层在该第二金属层上,位于该图案定义层内的一开口暴露出该第二金属层;形成第三金属层在该口所暴露出的该第二金属层上;去除该图案定义层;去除未在该第三金属层下的该第二金属层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造在方法是提供一半导体晶圆及位于该半导体晶圆上的一金属柱,其中该金属柱的最大横向尺寸除以该金属柱高度的比值小于4,且该金属柱的高度介于20微米至300微米之间,其中该半导体晶圆包括多个晶体管,其中该半导体晶圆包括复数晶体管,形成该些复数晶体管包括掺杂三价或五价离子至该半导体晶圆;形成一绝缘层在该半导体晶圆上,且包覆该金属柱;形成第一金属层在该绝缘层上及该金属柱上;形成一图案定义层在该第一金属层上,位于该图案定义层内的一开口暴露出该第一金属层;形成第二金属层在该口所暴露出的该第一金属层上;去除该图案定义层;去除位于该第二金属层下的该第一金属层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底、位于该半导体基底上的第一金属层、及位于该半导体基底上及该第一金属层上的一聚合物层;研磨该聚合物层;形成一凸块在该第一金属层上,其中该形成该凸块包括:形成第二金属层在该聚合物层上及该第一金属层上;形成一图案定义层在该第二金属层上,位于该图案定义层内的一开口暴露出该第二金属层;形成第三金属层在该口所暴露出的该第二金属层上;去除该图案定义层;去除位于该第三金属层下的该第二金属层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底及位于该半导体基底上的一金属柱,其中该金属柱的最大横向尺寸除以该金属柱的高度的比值是小于4,且该金属柱的高度是介于20微米至300微米之间;形成一绝缘层在该半导体基底上,且包覆该金属柱;形成一开口在该绝缘层内,暴露出该金属柱。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底、位于该半导体基底上的一金属层、及位于该半导体基底上及该金属层上的一聚合物层;磨该聚合物层;形成一开口在该聚合物层内,暴露出该金属层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底及位于该半导体基底上的一金属柱,其中该金属柱的最大横向尺寸除以该金属柱的高度的比值小于4,且该金属柱的高度介于20微米至300微米之间;形成一绝缘层在该半导体基底上,且包覆该金属柱;蚀刻该绝缘层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底、位于该半导体基底上的一金属柱、及位于该半导体基底上及该金属柱上的一聚合物层;去除该聚合物层使暴露出该金属柱的一顶面,且该顶面到该聚合物层之间的高度差介于10微米到150微米。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底、位于该半导体基底上的一金属层、及位于该半导体基底上及该金属层上的一聚合物层;研磨该聚合物层;蚀刻该聚合物层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供提供一半导体基底;形成一聚合物层在该半导体基底上,在该聚合物层内的一开口的深度是介于10微米到300微米之间;形成一金属层在该聚合物层上及该开口内;去除位于该开口外的该金属层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底及位于该半导体基底上的一金属柱,其中该金属柱的最大横向尺寸除以该金属柱的高度的比值小于4,且该金属柱的高度介于20微米至300微米之间;形成一绝缘层在该半导体基底上,且包覆该金属柱;形成一凸块在该金属柱上;连接该凸块至一外界电路;形成第二绝缘层在该半导体基底与该外界电路之间。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底、位于该半导体基底上的一金属层、及位于该半导体基底上及该金属层上的第一聚合物层;研磨该第一聚合物层;形成一凸块在该金属层;连接该凸块至一外界电路;形成第二聚合物层在该半导体基底与该外界电路之间。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底、位于该半导体基底上的一金属层、及位于该半导体基底上及该金属层上的一聚合物层;研磨该聚合物层;形成一凸块在该金属层上,其中该形成该凸块包括一电镀制造方法。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底及位于该半导体基底上的一金属柱,其中该金属柱的最大横向尺寸除以该金属柱的高度的比值小于4,且该金属柱的高度介于20微米至300微米之间;形成一绝缘层在该半导体基底上,且包覆该金属柱;形成一凸块在该金属柱上,其中该形成该凸块包括一电镀制造方法。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底、位于该半导体基底上的一金属层、及位于该半导体基底上及该金属层上的一聚合物层;研磨该聚合物层;利用一打线制造方法形成一导线连接在该金属层上。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其制造方法是提供一半导体基底及位于该半导体基底上的一金属柱,其中该金属柱的最大横向尺寸除以该金属柱的高度的比值是小于4,且该金属柱的高度是介于20微米至300微米之间;形成一绝缘层在该半导体基底上,且包覆该金属柱;利用一打线制造方法形成一导线连接在该金属柱上。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一基板;第一金属柱,位于该基板上,该第一金属柱的最大横向尺寸除以该第一金属柱高度的比值小于4,且该第一金属柱的高度是介于20微米至300微米之间;第二金属柱,位于该基板上,该第二金属柱的最大横向尺寸除以该第二金属柱的高度的比值是小于4,且该第二金属柱的高度是介于20微米至300微米之间,该第一金属柱的中心点至该第二金属柱的中心点之间的距离是介于10微米至250微米之间。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一半导体基底;第一金属柱,位于该半导体基底上,该第一金属柱的最大横向尺寸除以该第一金属柱的高度的比值是小于4,且该第一金属柱的高度是介于20微米至300微米之间;第二金属柱,位于该半导体基底上,该第二金属柱的最大横向尺寸除以该第二金属柱的高度的比值是小于4,且该第二金属柱的高度是介于20微米至300微米之间;一绝缘层,位于该半导体基底上且包覆该第一及第二金属柱;第一凸块,位于该第一金属柱上;第二凸块,位于该第二金属柱上,其中该第一凸块的中心点至该第二凸块的中心点之间的距离是介于10微米至250微米之间。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一种半导体基底;第一金属柱,位于该半导体基底上,该第一金属柱的最大横向尺寸除以该第一金属柱的高度的比值是小于4,且该第一金属柱的高度是介于20微米至300微米之间;第二金属柱,位于该半导体基底上,该第二金属柱的最大横向尺寸除以该第二金属柱的高度的比值是小于4,且该第二金属柱的高度是介于20微米至300微米之间;一金属线路,连接该第一金属柱的顶面及该第二金属柱的顶面,其中该金属线路的材质包括金。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一半导体基底;第一金属柱,位于该半导体基底上,该第一金属柱的最大横向尺寸除以该第一金属柱的高度的比值是小于4,且该第一金属柱的高度是介于20微米至300微米之间;第二金属柱,位于该半导体基底上,该第二金属柱的最大横向尺寸除以该第二金属柱的高度的比值是小于4,且该第二金属柱的高度是介于20微米至300微米之间;一金属线路,连接该第一金属柱的顶面及该第二金属柱的顶面;一聚合物层,位于该金属线路上。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一半导体基底;一金属柱,位于该半导体基底上,该金属柱的最大横向尺寸除以该金属柱的高度的比值是小于4,且该金属柱的高度是介于20微米至300微米之间,其中利用打线制造方法适于形成一导线连接在该金属柱上。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一半导体基底;一金属柱,位于该半导体基底上,该金属柱的最大横向尺寸除以该金属柱的高度的比值是小于4,且该金属柱的高度是介于20微米至300微米之间;一聚合物层,位于该半导体基底上,且包覆该金属柱,其中高度介于10微米至150微米的一凸块适于形成在该金属柱上。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一半导体基底;一金属柱,位于该半导体基底上,该金属柱的最大横向尺寸除以该金属柱的高度的比值是小于4,且该金属柱的高度是介于20微米至300微米之间;一聚合物层,位该半导体基底上,且包覆该金属柱;一金属线圈,位于该聚合物层上,该金属线圈的厚度是介于1微米至15微米之间。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一半导体基底;一金属柱,位于该半导体基底上,该金属柱的最大横向尺寸除以该金属柱的高度的比值是小于4,且该金属柱的高度是介于20微米至300微米之间;一凸块,位于该金属柱上,其中该凸块包括厚度介于10微米到30微米的一金层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一半导体基底;一金属柱,位于该半导体基底上,该金属柱的最大横向尺寸除以该金属柱的高度的比值是小于4,且该金属柱的高度是介于20微米至300微米之间;一凸块,位于该金属柱上,其中该凸块包括含钛的一金属层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一半导体基底;一金属柱,位于该半导体基底上,该金属柱的最大横向尺寸除以该金属柱的高度的比值是小于4,且该金属柱的高度是介于20微米至300微米之间;一凸块,位于该金属柱上,其中该凸块包括含铬的一金属层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一半导体基底;一金属柱,位于该半导体基底上,该金属柱的最大横向尺寸除以该金属柱的高度的比值是小于4,且该金属柱的高度是介于20微米至300微米之间;一凸块,位于该金属柱上,其中该凸块包括含钽的一金属层。
为了本发明上述的目的,提出一种线路组件结构制造方法及其结构,其包括提供一半导体基底;一金属柱,位于该半导体基底上,该金属柱的最大横向尺寸除以该金属柱的高度的比值是小于4,且该金属柱的高度是介于20微米至300微米之间;第一聚合物层,位于该半导体基底上,且包覆该金属柱;一基板;一凸块,位于该金属柱与该基板之间;第二聚合物层,位于该基板与该半导体基底之间,且包覆该凸块。
以下借由具体实施例配合所附的附图详加说明,更容易了解本发明的目的、技术内容、特点及其所达成的功效。
附图说明
图1为现有技术技术的剖面示意图。
图2为本发明半导体基底的剖面示意图。
图3为本发明半导体基底上设置细联机结构及保护层的剖面示意图。
图4A及图4B为本发明形成第一聚合物层的剖面示意图。
图5A为本发明形成第一黏着/阻障层的剖面示意图。
图6A至图6E为本发明形成第一重配置线路层及金属柱体的剖面示意图。
图7A及图7B为本发明金属柱体物性示意图及俯视图。
图8A为本发明形成第二聚合物层的剖面示意图。
图8B为本发明形成第二聚合物层开口的剖面示意图。
图8C为本发明研磨第二聚合物层的剖面示意图。
图9为本发明形成第三聚合物层的剖面示意图。
图10A至图10D为本发明形成第三金属层的剖面示意图。
图11为本发明半导体基底进行切割的剖面示意图。
图12A至图12C为本发明形成锡球的剖面示意图。
图12D至图12E为本发明半导体基底进行切割及接合至基板的剖面示意图。
图13A及图13B为本发明金属柱体进行打线制造方法的剖面示意图。
图14A及图14B为本发明形成重配置线路层在金属柱体上的剖面示意图。
图15A至图15C为本发明铜/镍/金或铜/金的金属柱体打线的剖面示意图。
图16A至图16F为本发明形成第一线圈金属层在金属柱体上的剖面示意图。
图16G为本发明形成第二线圈金属层的剖面示意图。
图16H为本发明形成电容组件在金属柱体上的剖面示意图。
图17A至图17D为本发明形成连接二金属柱体的金属层的剖面示意图。
图17E至图17M为本发明形成多层线路层在金属柱体上的剖面示意图。
图18为本发明形成电阻组件在金属柱体上的剖面示意图。
图19A及图19B为本发明利用蚀刻方式去除部分第二聚合物层的剖面示意图。
图19C为本发明半导体基底进行切割的剖面示意图。
图19D及图19e为本发明形成锡球并进行切割步骤的剖面示意图。
图19F为本发明形成接垫的剖面示意图。
图19G至图19K为本发明形成连接二金属柱体的金属层的剖面示意图。
图20A为本发明形成图9聚合物层在半导体基底上的剖面示意图。
图20B至图20D为本发明以镶嵌方式形成金属柱体的剖面示意图。
图21A至图21D为本发明形成凸块、接垫、锡球、重配置线路层的结构剖示图。
图22至图25为本发明形成快速电流通道(freeway)、线圈、电容组件、电阻组件的结构剖示图。
附图标号说明:10-后护层结构;12-重配置线路层;14-聚合物层;18-半导体集成电路芯片;16-保护层;20-接垫;22-斜坡;30-半导体基底;32-电子组件;34-细联机结构;36-薄膜绝缘层;38-细线路层;40-导通孔;42-保护层;44-接垫;46-第一聚合物层;48-开口;50-第一黏着/阻障层;54-图1案化光刻胶层;56-开口;58-第一金属层;60-第一重配置线路层;62-图2案化光刻胶层;64-开口;66-第二金属层;68-金属柱体;70-第二聚合物层;72-开口;74-第三聚合物层;76-开口;78-第二黏着/阻障层;82-图3案化光刻胶层;83-开口;84-第三金属层;86-凸块;88-半导体单元;92-锡球;94-基板;96-第四聚合物层;98-接垫;100-重配置线路层;102-金层;104-铜层;106-镍层;105-第三黏着/阻障层;110-图4案化光刻胶层;112-开口;114-第四金属层;116-第一线圈金属层;117-保护层;118-第五聚合物层;120-第二线圈金属层;121-电容组件;121a-低介电层;121b-絶缘层;121c-低电阻金属层;121d-保护层;122-第四黏着/阻障层;126-图5案化光刻胶层;128-开口;130-第五金属层;132-保护层;134-第六聚合层;136-第五黏着/阻障层;140-图6案化光刻胶层;142-第六金属层;144-第七聚合物层;146-第七金属层;148-第八聚合物层;150-第六黏着/阻障层;152-图7案化光刻胶层;154-第八金属层;156-保护层;158-图9案化聚合物层;160-第七黏着/阻障层;162-第九金属层。
具体实施方式
本发明为线路组件结构制造方法及其结构,借由在半导体基底上形成多个金属柱(Post)结构,并且使相邻金属柱之间距缩小至250微米以下,以下就数种不同实施例予以说明:
第一实施例:
第一种实施例的线路组件结构制造方法,请参阅图2所示,首先提供一半导体基底30,此半导体基底30的形式比如是硅基底、砷化镓基底(GAAS)、硅化锗基底、具有磊晶硅在绝缘层上(silicon-on-insulator,SOI)的基底,半导体基底30在此实施例中为圆形的一半导体晶圆,且此半导体基底30具有一主动表面,在半导体基底30的主动表面透过掺杂五价或三价的离子(例如硼离子或磷离子等)形成多个电子组件32,此电子组件32例如是金属氧化物半导体或晶体管,金属氧化物半导体组件(MOS devices),P信道金属氧化物半导体组件(p-channelMOS devices),n信道金属氧化物半导体组件(n-channel MOS devices),双载子互补式金氧半导体组件(BiCMOS devices),双载子连接晶体管(Bipolar JunctionTransistor,BJT),扩散区(Diffusion area),电阻组件(resistor),电容组件(capacitor)及互补金属氧化半导体(CMOS)等。
请参阅图3所示,而在半导体基底30的主动表面上形成一细联机结构34,此细联机结构34是由若干厚度小于3微米的薄膜绝缘层36及厚度小于3微米的细线路层38所构成,其中细线路层38是选自铜金属材质或铝金属材质,而薄膜绝缘层36又称为介电层,一般是利用化学气相沉积的方式所形成。此薄膜绝缘层36比如为氧化硅、化学气相沉积的四乙氧基硅烷(TEOS)氧化物、SiwCxOyHz、氮硅化合物或氮氧硅化合物,或是以旋涂方式形成的玻璃(SOG)、氟化玻璃(FSG)、丝印层(SiLK)、黑钻石薄膜(Black Diamond)、聚亚芳基酯(polyaryleneether)、聚苯并恶唑(polybenzoxazole,PBO)、多孔性氧化硅(porous silicon oxide),或者薄膜绝缘层36为其它介电常数值(FPI)小于3的材质。
在形成若干细线路层38在半导体基底30上的过程中,就金属镶嵌制造方法而言,是先溅镀一扩散阻絶层在一薄膜绝缘层36的开口内的底部及侧壁上及薄膜绝缘层36的上表面上,接着再溅镀一层例如是铜材质的种子层在扩散阻絶层上,接着再电镀一铜层在此种子层上,接着再利用化学机械研磨(chemical mechanicalpolishing,CMP)的方式去除位于该薄膜绝缘层36的开口外的铜层、种子层及扩散阻絶层,直到暴露出薄膜绝缘层36的上表面为止。而另一种方式亦可以先溅镀一铝层或铝合金层在一薄膜绝缘层36上,接着再利用影印蚀刻的方式图案化铝层或铝合金层。此细线路层38可透过薄膜绝缘层36内的导通孔40相互连接,或连接至电子组件32上,其中细线路层38一般的厚度是在0.1微米到0.5微米之间,在进行影印制造方法时细线路层38的细金属线路是使用五倍(5X)的曝光机(steppers)或扫描机(scanners)或使用更佳的仪器来制作。
接着在半导体基底30的表面利用化学气相沉积(CVD)方式设置一保护层42,此保护层42具有数个缺口暴露出数个接垫44,可以保护半导体基底30内的电子组件32免于湿气与外来离子污染物(foreign ion contamination)的破坏,也就是说保护层42可以防止移动离子(mobile ions)(比如是钠离子)、水气(moisture)、过渡金属(transition metal)(比如是金、银、铜)及其它杂质(impurity)穿透,而损坏保护层42下方的晶体管、多晶硅电阻组件或多晶硅-多晶硅电容组件的电子组件32或细金属线路。为了达到保护的目的,保护层42通常是由氧化硅(silicon oxide)、氧硅化合物、磷硅玻璃、氮化硅(silicon nitride)、及氧氮化硅(silicon oxy-nitride)等所组成。
而保护层42的第一种制作方式可以是先利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氧化硅层,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氮化硅层在该氧化硅层上。
第二种保护层42制作方式可以是先利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氧化硅层,接着再利用等离子体加强型化学气相沉积的步骤形成厚度介于0.05至0.15微米间的氮氧化硅层在该氧化硅层上,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氮化硅层在该氮氧化硅层上。
第三种保护层42制作方式可以是先利用化学气相沉积的步骤形成厚度介于0.05至0.15微米间的氮氧化硅层,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氧化硅层在该氮氧化硅层上,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氮化硅层在该氧化硅层上。
第四种保护层42制作方式可以是先利用化学气相沉积的步骤形成厚度介于0.2至0.5微米间的第一氧化硅层,接着再利用旋涂法(spin-coating)形成厚度介于0.5至1微米间的第二氧化硅层在该第一氧化硅层上,接着再利用化学气相沉积的步骤形成厚度介于0.2至0.5微米间的第三氧化硅层在该第二氧化硅层上,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氮化硅层在该第三氧化硅层上。
第五种保护层42制作方式可以是先利用高密度等离子体化学气相沉积(HDP-CVD)的步骤形成厚度介于0.5至2微米间的氧化硅层,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氮化硅层在该氧化硅层上。
第六种保护层42制作方式可以是先形成厚度介于0.2至3微米间的未掺杂的硅酸盐玻璃层(undoped silicate glass,USG),接着形成比如是四乙氧基硅烷(TEOS)、硼磷硅酸盐玻璃(borophosphosilicate glass,BPSG)或磷硅酸盐玻璃(phosphosilicateglass,PSG)等的厚度介于0.5至3微米间的一绝缘层在该未掺杂硅玻璃层上,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氮化硅层在该绝缘层上。
第七种保护层42制作方式可以是选择性地先利用化学气相沉积的步骤形成厚度介于0.05至0.15微米间的第一氮氧化硅层,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氧化硅层在该第二氮氧化硅层上,接着可以选择性地利用化学气相沉积的步骤形成厚度介于0.05至0.15微米间的第二氮氧化硅层在该氧化硅层上,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氮化硅层在该第二氮氧化硅层上或在该氧化硅层上,接着可以选择性地利用化学气相沉积的步骤形成厚度介于0.05至0.15微米间的第三氮氧化硅层在该氮化硅层上,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氧化硅层在该第三氮氧化硅层上或在该氮化硅层上。
第八种保护层42制作方式可以是先利用化学气相沉积(PECVD)的步骤形成厚度介于0.2至1.2微米间的第一氧化硅层,接着再利用旋涂法(spin-coating)形成厚度介于0.5至1微米间的第二氧化硅层在该第一氧化硅层上,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的第三氧化硅层在该第二氧化硅层上,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氮化硅层在该第三氧化硅层上,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的第四氧化硅层在该氮化硅层上。
第九种保护层42制作方式可以是先利用高密度等离子体化学气相沉积(HDP-CVD)的步骤形成厚度介于0.5至2微米间的第一氧化硅层,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氮化硅层在该第一氧化硅层上,接着再利用高密度等离子体化学气相沉积(HDP-CVD)的步骤形成厚度介于0.5至2微米间的第二氧化硅层在该氮化硅层上。
第十种保护层42制作方式可以是先利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的第一氮化硅层,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的氧化硅层在该第一氮化硅层上,接着再利用化学气相沉积的步骤形成厚度介于0.2至1.2微米间的第二氮化硅层在该氧化硅层上。
保护层42的厚度一般是大于0.35微米,在较佳的情况下,氮化硅层的厚度通常大于0.3微米。
完成此保护层42后,请参阅图4A所示,接着形成厚度介于3微米至50微米之间的第一聚合物层46在此保护层42上,此第一聚合物层46具有絶缘功能,且此第一聚合物层46的材质是选自材质比如为热塑性塑料、热固性塑料,具体如聚酰亚胺(polyimide,PI)、苯并环丁烯(benzo-cyclo-butene,BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子等、焊罩材料、其他弹性材料或多孔性介电材料等。而此第一聚合物层46主要是利用旋涂方式设置,另外也可利用热压合干膜方式、网版印刷方式进行,接着如图4B所示,利用蚀刻方式对此第一聚合物层46进行图案化,而形成数个开口48暴露出半导体基底30上的接垫44。其中值得注意的是,当第一聚合物层46为感光材质时,则比如可以利用影印制造方法(photolithography process),将第一聚合物层46图案化;当第一聚合物层46为非感光材质时,则比如可以利用影印和蚀刻制造方法(photolithography process and etching process),将第一聚合物层46图案化。
并且将图案化的第一聚合物层46后,利用烘烤加热、微波加热、红外线加热其中之一方式进行加热至介于摄氏200度与摄氏320度之间的温度或加热至介于摄氏320度与摄氏450度之间的温度,以硬化(curing)第一聚合物层46,硬化后的第一聚合物层46在体积上会呈现缩小的情形,且第一聚合物层46含水率小于1%,此含水率是将第一聚合物层46置放在温度介于摄氏425度至450度下时,其重量变化率小于1%。
如图5A所示,以溅镀方式形成厚度介于400埃至7000埃的第一黏着/阻障层50(Adhesion/Barrier/seed layer)在第一聚合物层46及接垫44上,其中此第一黏着/阻障层50的材质是选自钛金属、氮化钛、钛钨合金、钽金属层、铬、铬铜合金及氮化钽其中之一或所组成的群组的至少其中之一,且第一黏着/阻障层50,此第一黏着/阻障层50上另形成有一种子层(图中未示),此种子层有利于后续金属线路的设置,因此种子层的材质也随后续的金属线路材质有所变化,此外在本文后续实例中所有黏着/阻障层上皆形成有一种子层,在此特以说明。
当种子层上是电镀形成铜材质的金属线路时,种子层的材料是以铜为佳;当要电镀形成银材质的金属线路时,种子层的材料是以银为佳;当要电镀形成钯材质的金属线路时,种子层的材料是以钯为佳;当要电镀形成铂材质的金属线路时,种子层的材料是以铂为佳;当要电镀形成铑材质的金属线路时,种子层的材料是以铑为佳;当要电镀形成钌材质的金属线路时,种子层的材料是以钌为佳;当要电镀形成铼材质的金属线路时,种子层的材料是以铼为佳;当要电镀形成镍材质的金属线路时,种子层的材料是以镍为佳。
接着如图6A所示,形成图案化光刻胶层54在位于此第一黏着/阻障层50上的种子层上,此图案化光刻胶层54具有数个开口56暴露出部分的位于第一黏着/阻障层50上的种子层,在形成开口56的过程中比如是一倍(1X)的曝光机(steppers)或扫描机(scanners),且此图案化光刻胶层54为正光刻胶型式。接着电镀形成厚度介于1微米至50微米之间的第一金属层58在开口36所暴露出且位于第一黏着/阻障层50上的种子层上,此第一金属层58较佳的厚度是介于2微米至30微米之间,使第一金属层58电连接至细联机结构34,此第一金属层58比如是金、铜、银、钯、铂、铑、钌、铼或镍的单层金属层结构,或是由上述金属材质所组成的复合层去除此图案化光刻胶层54,即形成第一重配置线路层60,值得注意的特点在于此第一重配置线路60主要是将第一金属层58形成在开口48上及延伸至部分的第一聚合物层46上,并不是单纯形成在开口48上,而所延伸的第一金属层58上则有利于后续的线路的设置。
如图6B所示,接着形成图案化光刻胶层62在此第一重配置线路60上及位于第一黏着/阻障层50上的种子层上,此图案化光刻胶层62的数个开口64暴露出此第一重配置线路60的第一金属层58,接着如图6C所示,电镀形成厚度介于20微米至300微米之间的第二金属层66在此开口64内,且此第二金属层66的最大横向寛度是介于3微米至50微米,此第二金属层66的材质的材质选自金、铜、银、钯、铂、铑、钌、铼或镍其中之一或所组成的群组的至少其中之一,此第二金属层66较佳的厚度是介于30微米至100微米之间。
其中值得注意的是第二金属层66的材质若是铜金属时,则第一重配置线路60较佳的顶层金属材质为铜金属;第二金属层66的材质若是银金属时,则第一重配置线路60较佳的顶层金属材质为银金属;第二金属层66的材质若是钯金属时,则第一重配置线路60较佳的顶层金属材质为钯金属;第二金属层66的材质若是铂金属时,则第一重配置线路60较佳的顶层金属材质为铂金属;第二金属层66的材质若是铑金属时,则第一重配置线路60较佳的顶层金属材质为铑金属;第二金属层66的材质若是钌金属时,则第一重配置线路60较佳的顶层金属材质为钌金属;第二金属层66的材质若是铼金属时,则第一重配置线路60较佳的顶层金属材质为铼金属;第二金属层66的材质若是镍金属时,则第一重配置线路60较佳的顶层金属材质为镍金属。
如图6D所示,接着去除图案化光刻胶层62,并利用双氧水蚀刻去除位于第一金属层58下的第一黏着/阻障层50,其中除了利用双氧水去除第一黏着/阻障层50外,并利用含有碘的蚀刻液去除第一黏着/阻障层50上的种子层,例如碘化钾等蚀刻液,且此外去除位于第一金属层58下的种子层及第一黏着/阻障层50的步骤除了在去除图案化光刻胶层62后进行,也可在去除此图案化光刻胶层54后进行,如图6E所示。
如图7A及图7B所示,在去除第一金属层58下的第一黏着/阻障层50后,每一第二金属层66即定义成本发明的金属柱体68,此金属柱体68的最大横向尺寸Hw除以高度Ht的比值小于4的柱体,甚至此比值可小于3或2或1等,此金属柱体68最大横向寛度是介于3微米至50微米,因此金属柱体68为细小的柱体并不同于先前技术中的金属层或线路层,而且相邻金属柱体68的中心至中心间距Hb是介于10微米至250微米之间,并且较佳之间距可缩至10微米至200微米、10微米至175微米、10微米至150微米,而此金属柱体68设置在此第二金属层66的俯视图如图7B所示,由此图示中可明显看出此金属柱体68是形成在重配置线路60所延伸出的区域上,而并非在开口48上的重配置线路60上。
如图8A所示,形成第二聚合物层70在此半导体基底30上将金属柱体68覆盖,此第二聚合物层70的材质是选自材质比如为热塑性塑料、热固性塑料,例如聚酰亚胺(polyimide,PI)、苯并环丁烯(benzo-cyclo-butene,BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子等、焊罩材料、其他弹性材料或多孔性介电材料。而此第二聚合物层70设置方式是选自网版印刷或旋涂方式;请参阅图8B所示,其中若是以网版印刷方式设置可直接在第二聚合物层70内形成多数开口72而暴露出金属柱体68顶端,若是以旋涂方式设置此第二聚合物层70,则必须再经由一图案化步骤形成数个开口72,进而暴露出金属柱体68顶端,此第二聚合物层70若是以旋涂方式设置,则形成开口72的方式则是以影印或影印蚀刻方式形成。如图8C所示,另外暴露此金属柱体68方式除了形成开口72外,也可采用研磨方式使金属柱体68暴露出,但是进行研磨步骤前则必须将此第二聚合物层70进行硬化(Curing),等硬化后利用一化学机械研磨(CMP)将第二聚合物层70进行研磨,使金属柱体68顶端暴露出,此外除了可利用化学机械研磨(CMP)外,也可直接以机械研磨方式进行研磨,而硬化的步骤同样是利用烘烤加热、微波加热、红外线加热其中之一方式进行。
另外在此预先说明后续许多实施例大多是由图8B及图8C中的结构所延伸,所以对于本发明而言此二图示中揭示在半导体基底30上形成若干金属柱体68,相邻金属柱体68之间具有细间距(fine pitch)特征,其间距介于10微米至250微米之间,且金属柱体68的最大横向尺寸Hw除以高度Ht的比值小于4,因此后续许多实施例皆是在此金属柱体68上进行变化,而在此第一实施例中则是以图8C的结构为基础。
如图9所示,利用旋涂方式形成第三聚合物层74在第二聚合物层70上,对此第三聚合物层74进行图案化步骤形成数个开口76,此第三聚合物层74的图案化步骤是利用影印或影印和蚀刻方式进行;另外也可将干膜型式且已图案化的第三聚合物层74热压合在此第二聚合物层70上,或者是利用网版印刷方式将第三聚合物层74形成在第二聚合物层70上,此第三聚合物层74的材质选自材质比如为热塑性塑料、热固性塑料,例如聚酰亚胺(polyimide,PI)、苯并环丁烯(benzo-cyclo-butene,BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子等、焊罩材料、其他弹性材料或多孔性介电材料。
如图10A所示,以溅镀方式形成厚度介于400埃至7000埃的第二黏着/阻障层78在第三聚合物层74上及金属柱体68顶端表面上,此第二黏着/阻障层78的材质是选自钛金属、氮化钛、钛钨合金、钽金属层、铬、铬铜合金及氮化钽其中之一或所组成的群组的至少其中之一,并且同样在此第二黏着/阻障层78上形成一种子层,接着如图10B所示,形成图案化光刻胶层82在第二黏着/阻障层78的种子层上,此图案化光刻胶层82为正光刻胶型式,在此图案化光刻胶层82的数个开口83暴露出开口76上及开口76周围的第二黏着/阻障层78的种子层。
接着如图10C所示,以利电镀方式形成第三金属层84在开口83所暴露出且在第二黏着/阻障层78上的种子层上,此第三金属层84的材质选自金、铜、银、钯、铂、铑、钌、铼、镍、焊料、锡铅合金、锡银合金、锡银铜合金或无铅焊料等其中之一或所组成的群组的至少其中之一,如图10D所示,接着同样利用双氧水蚀刻去除位于第三金属层84下的第二黏着/阻障层78,其中也可利用含有碘的蚀刻液去除种子层,比如碘化钾等蚀刻液;在此值得注意的地方于此第三金属层84电镀所形成的厚度的差异、第三金属层84材质差异及位置差异则会使此半导体基底30接合至外界电路产生各种不同型式及应用,也就是根据不同的应用,图案化光刻胶层82的厚度、开口83寛度及开口82形成位置也会随的变化,进而电镀形成不同厚度、位置及材质的第三金属层84,其中上述的外界电路为软版、半导体芯片、印刷电路板、陶瓷基板或玻璃基板等。
在本实施例中此第三金属层84所形成的型式,包括凸块(bump)、接垫(pad)、重配置线路层(RDL)或锡球(solder),如上述图10D所示,第三金属层84的材质为金(Au)、铜、银、钯、铂、铑、钌、铼时,并且所形成第三金属层84的厚度(Ha)是介于5微米至30微米之间时,较佳厚度是介于10微米至25微米之间,此第三金属层84定义成一凸块86,且相邻凸块86中心至中心之间距是小于250微米之间,较佳者甚至可小于200微米、150微米之间,接着如图11所示,将此半导体基底30进行切割,使半导体基底30形成若干半导体单元88,而每一半导体单元88上的凸块86可借由形成一异方性导电胶(ACF)电连接至一外界电路上。
如图12A及图12B所示,第三金属层84的材质为焊料、锡铅合金、锡银合金、锡银铜合金或无铅焊料其中之一,且所形成第三金属层84的厚度(Hs)是介于20微米至150微米之间时,较佳厚度介于30微米至100微米之间,接着如图12C所示,将此半导体基底30进行一加热步骤,此第三金属层84在加热时会熔融形成球状,此形成球状的第三金属层84定义成一锡球92,且相邻锡球92中心至中心之间距是小于250微米之间,较佳者甚至可小于200微米、150微米之间。此外此第三金属层84型式除了上述二种外,也可以电镀方式形成厚度1微米至100微米之间的铜层在图案化光刻胶层82的开口83内,接着再电镀形成1微米至10微米之间的镍层在铜层上,最后电镀形成厚度介于20微米至150微米之间的锡层或锡银层或锡银铜合金层在此镍层上。
接着将此半导体基底30进行切割步骤,如图12D所示,使半导体基底30形成若干半导体单元88,而每一半导体单元88上的锡球92可接合在外界的基板94上,此基板94为半导体芯片、印刷电路板、陶瓷基板或玻璃基板。
如图12E所示,此半导体单元88上的锡球92接合在基板94上时,其中半导体单元88接合至基板94前可预先再形成第四聚合物层96在基板94上,此第四聚合物层96的材质可选自热塑性塑料、热固性塑料,例如聚酰亚胺(polyimide,PI)、苯并环丁烯(benzo-cyclo-butene,BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子等、焊罩材料、其他弹性材料或多孔性介电材料。而形成此第四聚合物层96方式包括热压合已图案化的干膜(dry film)在该基板94上、或热压合感光性干膜在基板94上,并利用影印方式图案化感光性干膜、或热压合一非感光性干膜在基板94上,并利用影印蚀刻方式图案化非感光性干膜、或利用网版印刷步骤形成第四聚合物层96在基板94上、或以旋涂方式形成感光性薄膜在基板94上,并利用影印方式图案化感旋光性薄膜或以旋涂方式形成非感光性薄膜在基板94上,并利用影印蚀刻方式图案化非感光性薄膜;待半导体单元88上的锡球92接合在基板94上后进行加热步骤,使第四聚合物层96硬化,此加热步骤可借由一烘烤加热、一微波加热、一红外线加热等方式达成。
如图13A及图13B所示,第三金属层84的材质为金(Au)、铜、银、钯、铂、铑、钌、铼时,并且所形成第三金属层84的厚度(Hp)是介于1微米至15微米之间时,较佳厚度是介于2微米至10微米之间,此第三金属层84定义成一接垫(pad)98,且相邻接垫98中心至中心之间距是小于250微米之间,较佳者甚至可小于200微米、150微米之间,此接垫98可利用打线制造方法形成一导线(wire)连接至外界电路上。
如图14A及图14B所示,第三金属层84的材质为金(Au)、铜、银、钯、铂、铑、钌、铼时,并且所形成第三金属层84的厚度(Hr)是介于5微米至30微米之间时,较佳厚度是介于10微米至25微米之间,且此第三金属层84形成的位置除了在第三聚合物层74的开口76上,还形成在开口76一侧边的第二黏着/阻障层78上,此第三金属层84定义为一重配置线路层(RDL)100,此重配置线路层100可利用打线制造方法形成导线(wire)连接至外界电路上,其中在此加强说明形成在开口76一侧边的第三金属层84是类似接垫98的功能,此种偏边(心)的设计是为了防止上述接垫98的尺寸过小时,在打线制造方法所需的打线面积不足,造成打线制造方法的困难度增加。
此外本实施例中图9至图14B中的凸块(bump)、接垫(pad)、重配置线路层(RDL)或锡球(solder)等应用皆是由图8C结构所延伸,但这些应用同样也可直接由图8B中结构所延伸,原因在于图9的结构是由形成第三聚合物层74在图8C结构上,并且图案化此第三聚合物层74形成数个开口,然而图8B的结构并非是经由研磨直到暴露出金属柱体68,而是以图案化方式形成数个开口暴露出金属柱体68,并且不需再设置第三聚合物层74,也就是说此图8B的结构相似于图8C的结构加上第三聚合物层74,因此关于图9后续延伸的如图10A-图10D、图11、图12A-图12E、图13A-图13B及图14A-图14B所示的凸块(bump)、接垫(pad)、重配置线路层(RDL)或锡球(solder)等应用可以推及到图8B所示的结构中,在此就不加以重复叙述说明。
第二实施例:
此实施例为第一实施例中的图8C的延伸,请参阅图15A所示,此实施例中金属柱体68的顶部为一金层102,此金层的厚度是介于1微米至30微米之间,而在此金属柱体68的金层102上利用打线制造方法形成一导线104电连接至外界电路上,其中值得注意在于而金层102以下的金属包括铜层104、镍层106(铜/镍/金结构),此铜层104厚度是介于10微米至100微米之间,而镍层106则是介于1微米至10微米之间,或是如第十五b图所示,金层102以下为铜层104(铜/金结构),此金层102厚度是介于1微米至30微米之间,或是如图15C所示,整个金属柱体68的材质为金材质,此金材质的金属柱体68厚度是介于10微米至100微米之间。
第三实施例:
此实施例为第一实施例中的图8C的延伸,请参阅图16A所示,形成第三黏着/阻障层105在第二聚合物层70上,同样在此第三黏着/阻障层105上形成有一种子层,此种子层的材质随后续设置的金属材质而改变,如图16B所示,形成图案化光刻胶层110在第三黏着/阻障层105上,此图案化光刻胶层110内具有数个开口112,其中至少一开口112位置是位于金属柱体68上方,且此开口112是呈现线圈形状,如图16C所示,电镀形成第四金属层114在图案化光刻胶层110的开口112内,此第四金属层114的材质为金(Au)、铜、银、钯、铂、铑、钌、铼其中之一,且此第四金属层114的厚度是介于1微米至30微米之间,此外此第四金属层114也可由多层复合金属层所构成,例如电镀一厚度介于1微米至30微米之间的铜层,并再电镀形成一厚度介于1微米至10微米之间的镍层在此铜层上,最后再形成厚度介于1微米至10微米之间的金层在此镍层上。
如图16D所示,移除图案化光刻胶层110,并且同样利用双氧水去除第三黏着/阻障层105,并利用含有碘的蚀刻液蚀刻去除位于第四金属层114下的种子层,如图16E所示,此第四金属层114呈现线圈形状,因此将此第四金属层114定义为第一线圈金属层116,其中第一线圈金属层116透过金属柱体68电连接至半导体基底30,如图16F所示,除了可电连接半导体基底30外也可透过打线制造方法电连接至外界电路(未图示),并且可形成厚度介于5微米至25微米之间保护层117在此第一线圈金属层116上,以保护第一线圈金属层116不受损坏及水气入侵,此保护层117的材质为有机化合物或无机化合物等,比如是热塑性塑料、热固性塑料,例如聚酰亚胺(polyimide,PI)、苯并环丁烯(benzo-cyclo-butene,BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子等、焊罩材料、其他弹性材料、多孔性介电材料、氧化硅(silicon oxide)、氧硅化合物、磷硅玻璃、氮化硅(silicon nitride)、及氧氮化硅(silicon oxy-nitride)等所组成,此第一线圈金属层116可应用在电感、电容及电阻等被动组件的领域之中。
在此列举出此第一线圈金属层116在电感被动组件的应用,请参阅图16G所示,在此第一线圈金属层116覆盖第五聚合物层118,此第五聚合物层118的厚度介于20微米至300微米之间,此第五聚合物层118的材质比如是聚酰亚胺(polyimide,PI),且此第五聚合物层118是利用旋涂方式形成;接着借由形成第一线圈金属层116方式在第五聚合物层118上形成第二线圈金属层120,此第二线圈金属层120可电连接至外界电路,当外界电路电流有所变化时,经由第二线圈金属层120产生感应电动势使第一线圈金属层116感应,并产生讯号传入半导体基底30内,如此即解说完成此电感被动组件的制作。
此外利用上述选择性电镀方式,也可在第二聚合物层70上形成一电容组件121(capacitor),如图16H图所示,图中在第二聚合物层70设有厚度500埃至5000埃之间的低介电层121a,此低介电层121a材质是选自钛、钛钨合金、钽或钽氮化合物等,且此低介电层121a电连接至一金属柱体68,接着在低介电层121a上包覆一高介电层121b,此高介电层121b的材质为氮氧硅化合物、氧硅化合物(silicon oxide)或聚酰亚胺(polyimide,PI),在相邻的金属柱体68上电镀形成一低电阻金属层121c,此低电阻金属层121c的形成方式共有2种,首先第1种方式是先溅镀形成厚度介于400埃至7500埃之间的一黏着/阻障层在第二聚合物层70及高介电层121b上,此黏着/阻障层的材质为钛、钛钨合金、铬、钽或氮化钽等,接着再溅镀形成厚度介于500埃至5000埃之间的种子层在此黏着/阻障层上;接着再电镀厚度介于1微米至30微米之间的铜层在此种子层上,接着电镀厚度介于1微米至10微米之间的一镍层在此铜层上。
而第2种方式则是先溅镀形成厚度介于400埃至7500埃之间的一黏着/阻障层在第二聚合物层70及高介电层121b上,接着再溅镀厚度500微米至5000微米之间金材质的种子层在此黏着/阻障层上,最后电镀厚度介于1微米至30微米的金层在此金材质种子层上。如此对此相邻金属柱体68施加电压时,在高介电层121b上下二侧形成大电压差,此结构可作为具有电容功能。最后可在此低电阻金属层121c及第二聚合物层70上覆盖一保护层121d,防止此电容组件121受到损坏。
第四实施例:
此实施例为第一实施例中的图8B的延伸,请参阅图17A所示,形成第四黏着/阻障层122在第二聚合物层70上,此第四黏着/阻障层122的材质为钛、钛钨合金、铬、钽或氮化钽其中之一,且同样在此第四黏着/阻障层122上形成有种子层,此种子层的材质包括有金、铜、银、铂、铼、钌、钯、铑其中之一,如图17B所示,形成图案化光刻胶层126在第四黏着/阻障层122上,此图案化光刻胶层126内具有数个开口128,其中二开口128位置是位于金属柱体68上方,如图17C所示,电镀形成厚度介于5微米至30微米之间的第五金属层130,在图案化光刻胶层126之开口128内的第四黏着/阻障层122上,且此第五金属层130为低电阻,比如金、银、铂、铼、钌、钯、铑或铜等,且此第五金属层130厚度是介于1微米至30微米之间;或者此第五金属层130可由多层复合金属层所构成,例如电镀一厚度介于1微米至30微米之间的铜层,并再电镀形成一厚度介于1微米至10微米之间的镍层在此铜层上,最后再形成厚度介于1微米至10微米之间的金层在此镍层上
接着如图17D所示,移除图案化光刻胶层126,并且同样利用双氧水及含有碘之蚀刻液蚀刻去除位于第五金属层130下的第四黏着/阻障层122及种子层,此第五金属层130电连接至二金属柱体68,此第五金属层130为二金属柱体68之间的金属连接线路,此金属连接线路可提供电流快速流动之通道,另外可形成一保护层132覆盖在第二聚合物层70及第五金属层130上,防止此第五金属层130受到损坏及水气入侵。
除了形成五金属层130作为金属连接线路外,也可延伸为多层线路结构,如图17E所示,形成第六聚合层134在第二聚合物层70及第五金属层130上,接着如图17F所示,图案化此第六聚合层134形成数个开口,暴露出第五金属层130,如图17G所示,依序溅镀形成第五黏着/阻障层136,此第五黏着/阻障层136之材质是选自钛、钛钨合金、钽、氮化钽及铬其中之一,并同样在此第五黏着/阻障层136上形成种子层(图中未示),此种子层之材质比如是金、铜、银、铂、铼、钌、钯、铑其中之一,如图17H所示,形成一图6案化光刻胶层140在上,此图案化光刻胶层140之数个开口暴露出第六聚合层134之开口,如图17I所示,形成第六金属层142在图案化光刻胶层140之开口内,此第六金属层142之材质为金(Au)、铜、银、钯、铂、铑、钌、铼其中之一,且此第六金属层142之厚度是介于1微米至30微米之间,此外此第六金属层142也可由多层复合金属层所构成,例如电镀一厚度介于1微米至30微米之间的铜层,并再电镀形成一厚度介于1微米至10微米之间的镍层在此铜层上,最后再形成厚度介于1微米至10微米之间的金层在此镍层上。
如图17J所示,移除图6案化光刻胶层140、及位于第六金属层142下方的及第五黏着/阻障层136及种子层,如图17k所示,接着再形成厚度介于10微米至25微米之间的第七聚合物层144在第六聚合层134及第六金属层142上,此第七聚合物层144之材质比如是聚酰亚胺(polyimide,PI),且此第七聚合物层144是利用旋涂方式形成,如图171所示,图案化此第七聚合物层144形成数个开口暴露出此第六金属层142,如图17M所示,借由打线制造方法形成导线在暴露的第六金属层142上,借此电连接至外界电路上。
第五实施例:
此实施例为第一实施例中的图8B之延伸,且此实施例与第四实施例相似,请参阅图18所示,其中此实施例形成之方式与第四实施例相同,差异点在于第四实施例中的第五金属层130为低电阻的材质,因此第五金属层130可供电流快速流通,然而第五实施例中(由图18观之)此第七金属层146为高电阻材质,比如是铬/镍合金(Cr/Ni)、钛、钨等,且此第七金属层146之厚度是介于1微米至3微米之间,因此第七金属层146在此实施例中是做为电阻组件之用。
第六实施例:
上述第一至第五实施例之中是图8B及图8C结构的延伸,然而此实施例则是由图8A结构所延伸,请参阅图19A及图19B所示,此实施例是利用蚀刻方式将部分的第二聚合物层70去除,其中在蚀刻此第二聚合物层70之前可预先利用化学机械研磨或机械研磨方式将此第二聚合物层70平坦化,如此可使进行蚀刻步骤时能均匀去除第二聚合物层70,直到暴露出高度1微米至150微米之间的金属柱体68,此暴露出高度为金属柱体顶面至第二聚合物层70顶面之间的距离,若金属柱体68之材质为金(Au)、铜、银、钯、铂、铑、钌、铼时,则金属柱体68较佳暴露出的高度是介于15微米至30微米之间,此暴露出的金属柱体68可作为凸块使用,如图19C所示,同样进行切割步骤将此半导体基底30切割形成数个半导体单元88,同样每一半导体单元88上的凸块可借由形成一异方性导电胶(ACF)电连接至外界电路上。
若金属柱体68之材质为焊料、锡铅合金、锡银合金、锡银铜合金或无铅焊料时,则金属柱体68较佳暴露出的高度是介于50微米至100微米之间,如图19D所示,且同样经过一加热步骤使暴露在外之金属柱体68熔融成球状(焊料锡球),接着如图19E所示,同样进行切割步骤将此半导体基底30切割形成数个半导体单元,每一半导体单元上的球形凸块接合至外界之基板上,并且在半导体单元与基板之间形成第八聚合物层148包覆每一球形凸块。
请参阅图19F所示,若金属柱体68之材质为金(Au)、铜、银、钯、铂、铑、钌、铼时,则金属柱体68较佳暴露出的高度是介于1微米至15微米之间,此暴露出的金属柱体68可作为接垫使用,此接垫可利用打线制造方法形成导线(wire)连接至外界电路上。
请参阅图19G所示,另外若暴露之金属柱体68之材质为金(Au)、铜、银、钯、铂、铑、钌、铼时,且所暴露之高度是介于5000埃至10微米之间时,形成一第六黏着/阻障层150在第二聚合物层70及金属柱体68暴露之表面上,此第六黏着/阻障层150之材质是选自钛、钛钨合金、钽、氮化钽及铬其中之一,并同样在此第六黏着/阻障层150上形成一种子层(未图示),此种子层之材质比如是金、铜、银、铂、铼、钌、钯、铑其中之一,且此第六黏着/阻障层150之厚度是介于1000埃至7500埃之间。
如图19H所示,形成图案化光刻胶层152在第六黏着/阻障层150上,图案化光刻胶层152之数个开口暴露出第六黏着/阻障层150,如图19I所示,形成第八金属层154在图案化光刻胶层152之开口内,如图19J所示,去除图案化光刻胶层152,并去除位于第八金属层154下之第六黏着/阻障层150,其中此第八金属层154连接在二金属柱体68之间以作为金属连接线路,此第八金属层154之材质为金(Au)、铜、银、钯、铂、铑、钌、铼其中之一,且此第八金属层154之厚度是介于1微米至30微米之间,此外此第八金属层154也可由多层复合金属层所构成,例如电镀厚度介于1微米至30微米之间的铜层,并再电镀形成厚度介于1微米至10微米之间的镍层在此铜层上,最后再形成厚度介于1微米至10微米之间的金层在此镍层上。
如图19K所示,最后形成一保护层156覆盖在第八金属层154及第二聚合物层70上用以保护此第八金属层154受到损伤,此保护层156之材质为热塑性塑料、热固性塑料,例如聚酰亚胺(polyimide,PI)、苯并环丁烯(benzo-cyclo-butene,BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子等、焊罩材料、其他弹性材料、多孔性介电材料、氧化硅(silicon oxide)、氧硅化合物、磷硅玻璃、氮化硅(silicon nitride)、及氧氮化硅(silicon oxy-nitride)等所组成。
此种利用蚀刻暴露出金属柱体68的方法除了可应用在上述凸块、接垫及金属连接线路之结构外,也可借由此结构应用在线圈结构、电容结构及电阻结构等上,因制作步骤与上述各别实施例相似,在此就不加以重复解说。
第七实施例:
此实施例之结构与图8C结构相似,差异点在于金属柱体68及形成第二聚合物层70之制造方法不同,请参阅图20A所示,在形成此第一重配置线路60在半导体基底30后,去除位于第一重配置线路60下的黏着/阻障层及种子层(如图6A),接着形成图案化聚合物层158在此第一重配置线路60上及第一黏着/阻障层50上,此图案化聚合物层158之数个开口暴露出第一重配置线路60,且图案化聚合物层158之开口深度介于20微米至300微米之间。
此图案化聚合物层158的材质可选自热塑性塑料、热固性塑料,例如聚酰亚胺(polyimide,PI)、苯并环丁烯(benzo-cyclo-butene,BCB)、聚氨脂(polyurethane)、环氧树脂、聚对二甲苯类高分子等、焊罩材料、其他弹性材料或多孔性介电材料,且此图案化聚合物层158形成方式包括热压合已图案化的干膜(dry film)在半导体基底30上、或热压合感光性干膜在半导体基底30上,并利用影印方式图案化感光性干膜、或热压合非感光性干膜在半导体基底30上,并利用影印蚀刻方式图案化非感光性干膜、或利用一网版印刷步骤形成图案化聚合物层158在半导体基底30上、或以旋涂方式形成一感光性薄膜在半导体基底30上,并利用影印方式图案化感光性薄膜或以旋涂方式形成非感光性薄膜在半导体基底30上,并利用影印蚀刻方式图案化非感光性薄膜。
如图20B所示,形成厚度介于400埃至7000埃之间的第七黏着/阻障层160在图案化聚合物层158及图案化聚合物层158开口内的第一重配置线路60上,此第七黏着/阻障层160的材质是选自钛、钛钨合金、钽、氮化钽及铬其中之一,并同样在此第七黏着/阻障层160上形成种子层(图中未示),此种子层的材质比如是金、铜、银、铂、铼、钌、钯、铑其中之一,且此第七黏着/阻障层160的厚度是介于1000埃至7500埃之间。
如图20C所示,以镶嵌(Damascene)方式形成第九金属层162在第七黏着/阻障层160上,并填满图案化聚合物层158的开口,此第九金属层162的材质为金(Au)、铜、银、钯、铂、铑、钌、铼其中之一,且此第九金属层162的厚度是介于1微米至30微米之间,此外此第九金属层162也可由多层复合金属层所构成,例如电镀一厚度介于1微米至30微米之间的铜层,并再电镀形成一厚度介于1微米至10微米之间的镍层在此铜层上,最后再形成厚度介于1微米至10微米之间的金层在此镍层上。
如图20D所示,进行研磨步骤将图案化聚合物层158的开口以外的第九金属层162及第七黏着/阻障层160去除,此研磨步骤是利用化学机械研磨(CMP)或机械研磨方式进行,以完成金属柱体68的设置,而此金属柱体68的最大横向尺寸Hw除以高度Ht的比值是小于4的柱体,此金属柱体68最大横向寛度是介于3微米至50微米,且相邻金属柱体68之间距Hb是介于10微米至250微米之间。
由于镶嵌(Damascene)方式所形成的金属柱体68结构与上述图8C中所揭示的结构十分相似,因此后续在图案化聚合物层158及金属柱体68上制作其它组件的方式为相同的步骤。
例如图21A至图21D所示,此图是揭示在图案化聚合物层158及金属柱体68上制作凸块、接垫、锡球、重配置线路层,其中制造方法部分已在上述实施例中说明,所以在此只揭示最终完成的结构,其制造方法部分就不重复说明。
如图22至图25所示,此图是揭示在图案化聚合物层158及金属柱体68上制作金属连接线路(interconnetion)、线圈、电容组件、电阻组件,其中制造方法部分已在上述实施例中说明,所以在此只揭示最终完成的结构,其制造方法部分就不重复说明。
本发明可提供应力的释放与微小化接触窗结构之间的间距,依据本发明,其间距是小于250微米,且可达成针孔数目少于400个的目标。并能有效改善集成电路的性能,且可大幅降低低电源IC组件的IC金属连接线路的阻抗及荷载。
以上所述是借由实施例说明本发明的特点,其目的在使熟悉本领域的普通一般技术人员能嘹解本发明的内容并据以实施,而非限定本发明专利权利要求范围,故,凡其它未脱离本发明所揭示的精神所完成的等效修饰或修改,仍应包含在以下所述的权利要求范围中。

Claims (23)

1.一种线路组件结构,其特征在于,包括:
一基板;
一第一金属柱体,位在该基板上,该第一金属柱体的最大横向尺寸除以该第一金属柱体的高度的比值是小于4,且该第一金属柱体的高度是介于20微米至300微米之间;以及
一第二金属柱体,位在该基板上,该第二金属柱体的最大横向尺寸除以该第二金属柱体的高度的比值是小于4,且该第二金属柱体的高度是介于20微米至300微米之间,该第一金属柱体的中心点至该第二金属柱体的中心点之间的距离是介于10微米至250微米之间。
2.如权利要求1所述的线路组件结构,其特征在于,还包括厚度介于20微米至300微米之间的一第一聚合物层,在该基板上且包覆该第一金属柱及该第二金属柱。
3.如权利要求1所述的线路组件结构,其特征在于,该第一金属柱体包括厚度介于30微米至100微米之间的一金层。
4.如权利要求1所述的线路组件结构,其特征在于,该第一金属柱体包括厚度介于30微米至100微米之间的一铜层。
5.如权利要求1所述的线路组件结构,其特征在于,还包括一金属连接线路,连接该第一金属柱体及该第二金属柱体。
6.如权利要求1所述的线路组件结构,其特征在于,该基板包括一半导体基底、位在该导体基底上的一第一金属结构、位在该金属线路上且含氮硅化合物的一保护层、及位在该保护层上的一第二金属结构,位在该保护层内的一开口暴露出该第一金属结构的一第一接垫,该第二金属结构包括一第二接垫,连接至该第一接垫,且该第一接垫从上视图观之的位置是不同于该第二接垫从上视图观之的位置,该第一金属柱体是位在该第二接垫上。
7.如权利要求1所述的线路组件结构,其特征在于,还包括一凸块,位在该第一金属柱体上,该凸块适于连接预先形成的一外界电路,该凸块包括厚度介于10微米至30微米的一金层。
8.如权利要求1所述的线路组件结构,其特征在于,还包括一凸块,位在该第一金属柱体上,该凸块适于连接预先形成的一外界电路,该凸块包括厚度介于10微米至150微米的一含锡焊料层。
9.如权利要求1所述的线路组件结构,其特征在于,还包括一接垫,位在该第一金属柱体上,该接垫的最大横向尺寸是大于该第一金属柱的最大横向尺寸,该接垫用于连接经由打线制程所形成的一导线。
10.如权利要求1所述的线路组件结构,其特征在于,该第一金属柱体的一顶面是用于连接利用打线制程所形成一导线。
11.如权利要求1所述的线路组件结构,其特征在于,还包括一金属线圈,连接该第一金属柱体及该第二金属柱体。
12.如权利要求1所述的线路组件结构,其特征在于,还包括一第二金属结构及一凸块,该第二金属结构位在该基板上,该第二金属结构包括一接垫,连接至该第一金属柱体,且该接垫从上视图观之的位置是不同于该第一金属柱体从上视图观之的位置,该凸块是位在该接垫上且适于连接预先形成的一外界电路,该凸块包括厚度介于10微米至30微米的一金层。
13.如权利要求1所述的线路组件结构,其特征在于,还包括一第二金属结构及一凸块,该第二金属结构位在该基板上,该第二金属结构包括一接垫,连接至该第一金属柱体,且该接垫从上视图观之的位置是不同于该第一金属柱体从上视图观之的位置,该凸块是位在该接垫上且适于连接预先形成的一外界电路,该凸块包括厚度介于10微米至150微米的一含锡焊料层。
14.如权利要求1所述的线路组件结构,其特征在于,还包括一第二金属结构,位在该基板上,该第二金属结构包括一接垫,连接至该第一金属柱体,且该接垫从上视图观之的位置是不同于该第一金属柱体从上视图观之的位置,该接垫是用于连接由打线制程所形成的一导线。
15.一种线路组件结构,其特征在于,包括:
一半导体基底;
一第一金属柱体,位在该半导体基底上,该第一金属柱体的最大横向尺寸除以该第一金属柱体的高度的比值是小于4,且该第一金属柱体的高度是介于20微米至300微米之间;
一第二金属柱体,位在该半导体基底上,该第二金属柱体的最大横向尺寸除以该第二金属柱体的高度的比值是小于4,且该第二金属柱体的高度是介于20微米至300微米之间;
一第一绝缘层,位在该半导体基底上且包覆该第一及第二金属柱体;
一第一凸块,位在该第一金属柱体上或该绝缘层上,且适于连接预先完成的一外界电路;以及
一第二凸块,位在该第二金属柱体上或该绝缘层上,且适于连接预先完成的一外界电路,其中该第一凸块的中心点至该第二凸块的中心点之间的距离是介于10微米至250微米之间。
16.如权利要求15所述的线路组件结构,其特征在于,该第一凸块的中心点至该第二凸块的中心点之间的距离是介于100微米至200微米之间。
17.如权利要求15所述的线路组件结构,其特征在于,该第一金属柱体包括厚度介于20微米至300微米之间的一金层。
18.如权利要求15所述的线路组件结构,其特征在于,该第一金属柱体包括介于20微米至300微米之间的一铜层。
19.如权利要求15所述的线路组件结构,其特征在于,该第一凸块包括厚度介于10微米至30微米之间的一金层。
20.如权利要求15所述的线路组件结构,其特征在于,该第一凸块包括厚度介于10微米至150微米之间的一含锡焊料层。
21.如权利要求15所述的线路组件结构,其特征在于,该第一绝缘层的材质包括聚酰亚胺。
22.如权利要求15所述的线路组件结构,其特征在于,还包括位在该导体基底上的一第一金属结构、位在该第一金属结构上且含氮硅化合物的一保护层、及位在该保护层上的一第二金属结构,位在该保护层内的一开口暴露出该第一金属结构的一第一接垫,该第二金属结构包括一第二接垫,连接至该第一接垫,且该第一接垫从上视图观之的位置是不同于该第二接垫从上视图观之的位置,该第一金属柱体是位在该第二接垫上。
23.如权利要求15所述的线路组件结构,其特征在于,还包括一金属结构,位在该第一绝缘层上及该第一金属柱体上,该金属结构包括一接垫,连接至该第一金属柱体,且该接垫从上视图观之的位置是不同于该第一金属柱体从上视图观的的位置,该第一凸块是位在该接垫上。
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