CN1881537B - 制造有源矩阵显示器件的方法 - Google Patents

制造有源矩阵显示器件的方法 Download PDF

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CN1881537B
CN1881537B CN 200610100376 CN200610100376A CN1881537B CN 1881537 B CN1881537 B CN 1881537B CN 200610100376 CN200610100376 CN 200610100376 CN 200610100376 A CN200610100376 A CN 200610100376A CN 1881537 B CN1881537 B CN 1881537B
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film
tungsten
wiring
metal film
cone angle
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CN1881537A (zh
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须泽英臣
小野幸治
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Semiconductor Energy Laboratory Co Ltd
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Abstract

布线及其制造方法、包括所说布线的半导体器件及干法腐蚀方法。提供一种干法腐蚀法,用于形成具有锥形且相对于底膜具有较大特定选择率的钨布线。如果适当调节偏置功率密度,并且如果利用具有氟作其主要成分的腐蚀气体去除钨薄膜的希望部分,则可以形成具有希望锥角的钨膜。

Description

制造有源矩阵显示器件的方法
本申请是专利申请号为200410056020.7发明名称为“布线及其制造方法、包括所说布线的半导体器件及干法腐蚀方法”的专利申请的分案申请。 
技术领域
本发明涉及一种具有由薄膜晶体管(此后称为TFT)构成的电路的半导体器件及其制造方法。例如,本发明涉及以液晶显示屏板为代表的电光器件,以及安装所说电光器件作为一个部件的电子设备。特别是,本发明涉及一种腐蚀金属薄膜的干法腐蚀方法及具有通过所说干法腐蚀方法得到的锥形布线的半导体器件。 
背景技术
注意,本说明书中,术语半导体器件表示利用半导体特征的一般器件,电光器件、半导体电路和电子设备都是半导体器件。 
近些年来,利用形成于具有绝缘表面的基片上的半导体薄膜(厚为几个nm-数百nm)构成薄膜晶体管(TFT)的技术已引起人了们的注意。薄膜晶体管可广泛应用于例如IC和电光器件等电子器件,具体说,将TFT作为像素显示器件的开关元件的研究正迅速发展。 
一般说,由于例如Al的易加工性、电阻率及其耐化学性,TFT布线材料经常用Al。然而,在TFT布线用Al时,由于热处理会形成如小丘或须晶等隆起,并且铝原子会扩散到沟道形成区中,造成了TFT无法正常工作,降低了TFT的特性。高耐热性的钨(W)具有5.5μΩ·cm的较低体电阻率,因此可以作为除Al外的布线材料。 
另外,近些年来,微加工技术的要求变得更严格。特别是,随着高清晰度和大屏幕液晶显示器的变化,布线加工步骤需要高选择性,线宽需要极严格地控制。 
一般布线工艺可以通过利用溶液的湿法腐蚀或利用气体的干法腐蚀进行。然而,从布线的小型化、重复性的保持、废料的减少和成本的降低等方面考虑,就布线加工来说,湿法腐蚀不好,认为干法腐蚀有利。 
在通过干法腐蚀加工钨(W)时,一般用SF6和Cl2的混合气体作腐蚀气体。尽管在用这种气体混合物时可以在短时间内以高腐蚀速率进行微加工,但很难得到希望的锥形。为了改善形成于布线上的层叠膜的台阶覆盖,根据器件结构,存在着将布线截面制作成想要的正锥形的情况。 
发明内容
本发明的目的是提供一种构图由钨(W)或钨化合物构成的腐蚀层以使截面形成正锥形的干法腐蚀法。另外,本发明的另一目的是提供一种控制干法腐蚀方法以便不管位置如何使整个腐蚀层上具有均匀、任意锥角的方法。此外,本发明再一目的是提供一种利用具有由上述方法得到的任意锥角的布线的半导体器件,及制造该半导体器件的方法。 
本说明书中公开的本发明的一个方案涉及一种布线: 
所说布线具有钨膜、具有钨化合物作其主要成分的金属化合物膜,或具有钨合金作其主要成分的金属合金膜,其特征在于锥角α为5°-85°。 
另外,本发明的另一个方案涉及一种布线: 
所说布线具有由选自钨膜、具有钨化合物作其主要成分的金属化合物膜和具有钨合金作其主要成分的金属合金膜的组中的层叠薄膜构成的层叠结构,其特征在于锥角α为5°-85°。 
在上述每个方案中,金属合金膜的特征在于,它是选自Ta、Ti、Mo、Cr、Nb及Si和钨中的一种元素或多种元素的合金膜。 
另外,金属化合物膜的特征在于,在上述每个方案中它是钨的氮化膜。 
另外,为了提高上述每个方案的粘附性,形成具有导电性的硅膜(例如,掺磷硅膜或掺硼硅膜)作布线的最下层。 
本发明的一个方案涉及一种半导体器件: 
具有由钨膜、具有钨化合物作其主要成分的金属化合物膜或具有钨合金作其主要成分的金属合金膜构成的布线的半导体器件,其中锥角α 为5°-85°。 
另外,本发明的另一个方案涉及一种半导体器件,包括: 
具有由选自钨膜、具有钨化合物作其主要成分的金属化合物膜和具有钨合金作其主要成分的金属合金膜的层叠薄膜构成的层叠结构,其中锥角α为5°-85°。 
在上述涉及与半导体的每个方案中,布线的特征在于它是TFT的栅布线。 
另外,本发明的一个方案涉及一种制造布线的方法: 
一种制造布线的方法,包括: 
在底膜上形成金属薄膜的步骤; 
在金属薄膜上形成抗蚀剂图形的步骤; 
通过腐蚀具有抗蚀剂图形的金属薄膜,形成根据偏置功率密度控制锥角α的布线的步骤。 
另外,本发明的另一个方案涉及一种制造布线的方法: 
一种制造布线的方法,包括: 
在底膜上形成金属薄膜的步骤; 
在金属薄膜上形成抗蚀剂图形的步骤; 
通过腐蚀具有抗蚀剂图形的金属薄膜,形成根据含氟气体的流速控制锥角α的布线的步骤。 
在上述涉及制造布线方法的每个方案中,制造方法的特征在于: 
利用由含氟的第一反应气和含氯的第二反应气的混合气构成的腐蚀气体,进行腐蚀;及 
底膜和金属薄膜间的腐蚀气的特定(specific)选择率大于2.5。 
另外,在涉及制造布线的方法的上述每个方案中,金属薄膜的特征在于,它是由选自钨膜、具有钨化合物作其主要成分的金属化合物膜和具有钨合金作其主要成分的金属合金膜的薄膜构成的一种薄膜或各薄膜的层叠膜。 
本发明的一个方案涉及干法腐蚀方法: 
干法腐蚀的方法包括利用腐蚀气体去除选自钨膜、具有钨化合物作其主要成分的金属化合物膜和具有钨合金作其主要成分的金属合金膜的薄膜的要求部分的步骤,其特征在于,所说腐蚀气体是含氟的第一反应气和含氯的第二反应气体的混合气。 
在涉及干法腐蚀方法的本发明上述方案中,第一反应气的特征在于,它是选自CF4、C2F6和C4F8中的一种气体。 
另外,在涉及干法腐蚀的本发明上述方案中,第二反应气的特征在于,它是选自Cl2、SiCl4和BCl3中的一种气体。 
另外,所说腐蚀方法的特征在于,在涉及干法腐蚀法的本发明上述方案中,利用ICP腐蚀装置。 
涉及干法腐蚀方法的本发明上述方案还有一特征在于,根据ICP腐蚀装置的偏置功率密度控制锥角α。 
本发明的另一方案涉及干法腐蚀方法: 
干法腐蚀方法的特征在于,根据偏置功率密度控制所形成的孔或凹部的内侧壁的锥角。 
此外,本发明的另一方案涉及一种干法腐蚀方法: 
干法腐蚀方法的特征在于,根据特定气体流速,控制所形成的孔或凹部的内侧壁的锥角。 
附图说明
各附图中: 
图1是展示锥角α与偏置功率的关系的示图; 
图2是展示锥角α与特定CF4流速的关系的示图; 
图3是展示锥角α与特定(W/抗蚀剂)选择率的关系的示图; 
图4是展示ICP腐蚀装置的等离子体产生机制的示图; 
图5是展示多螺旋线圈法ICP腐蚀装置的示图; 
图6A和6B是锥角α的例示图; 
图7A-7C是各布线的截面SEM照片; 
图8A和8B是各布线的截面SEM照片; 
图9A和9B是展示腐蚀速率和特定(W/抗蚀剂)选择率与偏置功率的关系的示图; 
图10A和10B是展示腐蚀速率和特定(W/抗蚀剂)选择率与特定CF4流速的关系的示图; 
图11A和11B是展示腐蚀速率和特定(W/抗蚀剂)选择率与ICP功率的关系的示图; 
图12是有源矩阵液晶显示器件的截面图; 
图13是有源矩阵液晶显示器件的截面图; 
图14是有源矩阵液晶显示器件的截面图; 
图15A-15F是各布线截面图; 
图16是展示有源矩阵型EL显示器件的示图; 
图17是展示AM-LCD的透视图; 
图18A-18F是展示电子设备的例子的示图; 
图19A-19D是展示电子设备的例子的示图。 
具体实施方式
下面用图1-8B介绍本发明的优选实施例。 
本发明采用使用高密度等离子体的ICP(感应耦合等离子体)腐蚀装置。简单说,ICP腐蚀装置是一种能够通过在低压下的等离子体中感应耦合RF功率得到等于或大于1011/cm3的等离子体密度、并以高选择性和高腐蚀速率进行腐蚀的装置。 
首先,利用图4详细介绍ICP干法腐蚀装置的等离子体产生机制。 
图4中示出了腐蚀室的简化结构图。天线线圈12设置在室上部中的石英基片11上,线圈12通过匹配盒13与RF功率源14连接。另外,RF功率源17通过匹配盒16与设置于相对侧上的基片下电极15连接。 
如果RF电流加于基片上的天线线圈12上,则RF电流J在θ方向流动,在Z方向产生磁场B。 
μ。J=rot B 
根据电磁感应的法拉第定律,在θ方向产生感应电场E。 
- ∂ B / ∂ t = rotE
电子在感应电场E中在θ方向被加速,并与气体分子碰撞,产生等离子体。感应电场的方向是θ方向,因此,由于带电粒子与腐蚀室壁和基片碰撞造成的电荷消失的几率降低。因此甚至在1Pa的低压下,也可以产生高密度等离子体。另外,下游几乎没有磁场B,所以等离子体变为以片形散布的高密度等离子体。 
通过调节加于天线线圈12(加ICP功率)和基片下电极15(加偏置功率)上的RF功率源,可以分别控制等离子体密度和自偏压。另外,可以根据要处理的工件材料改变所加RF功率的频率。 
为了用ICP腐蚀装置得到高密度等离子体,需要RF电流J在天线 线圈12中以低损耗流动,并且,为了制造大表面积,天线线圈12的电感必须减小。因此开发出了具有多个螺旋线圈22的ICP腐蚀装置,其中天线线圈是隔开的,如图5所示。图5中,参考数字21表示石英基片,参考数字23和26表示匹配盒,24和27表示RF功率源。另外,支撑基片28的下电极25通过室下部的绝缘体29形成。如果使用其中采用了多个螺旋线圈的利用ICP的腐蚀装置,则可以对上述抗传导电材料进行很好地腐蚀。 
本发明的申请人改变腐蚀条件,利用多螺旋ICP腐蚀装置(松下电器型号:E645),进行了许多试验。 
首先,介绍用于各试验的腐蚀试验片。在绝缘基片(康宁#1737玻璃基片)上由氮氧化硅膜形成底膜(200nm厚),然后,通过溅射在其上形成金属层叠膜。使用纯度等于或高于6N的钨靶。另外,可以使用例如氩(Ar)、氪(Kr)或氙(Xe)中的一种气体或这些气体的混合气体。注意,操作者可以适当地控制例如溅射功率、气体压力和基片温度等膜淀积条件。 
金属层叠膜用由WNx(其中0<x<1)表示的氮化钨膜(厚30nm)作下层,用钨膜(370nm)作上层。 
这样得到的金属层叠膜几乎不含杂质元素,具体说,可以使得所含氧的量等于或小于30ppm。可以使电阻率等于或小于20μΩ·cm,一般为6-15μΩ·cm。另外,可以使膜应力从-5×109达因/cm2到5×109达因/cm2
注意,整个说明书中,氮氧化硅膜是由SiOxNy表示的绝缘膜,表示绝缘膜含有预定比例的硅、氧和氮。 
利用多螺旋线圈ICP腐蚀装置,对腐蚀试验片进行金属层叠膜的构图实验。注意,在进行干法腐蚀时,无需说,要使用抗蚀剂,并将之构图成预定形状,形成抗蚀掩模图形(膜厚:1.5微米)。 
图6A示出了腐蚀加工前腐蚀试验片模型的剖面图。图6A中,参考数字601表示基片,参考数字602表示底膜,603a和603b表示金属层叠膜(膜厚X=400nm),604a和604b表示抗蚀掩模图形(膜厚Y=1.5微米)。另外,图6B是展示腐蚀加工后状态的示图。 
注意,如图6B所示,整个说明书中,锥角表示布线603的截面形状的锥形部分(倾斜部分)与底膜602间的夹角α。另外,该锥角可以 表示为tanα=X/Z,其中Z为锥形部分的宽度,X为膜厚。 
本发明的申请人改变该干法腐蚀的数个条件,观察了布线的截面形状。 
(实验1) 
图1是展示锥角α与偏置功率间关系的示图。在20W、30W、40W、60W和100W,用13.56MHz,即,用0.128、0.192、0.256、0.384和0.64(W/cm2)的偏置功率密度,进行实验。注意,下电极为12.5cm×12.5cm。另外,抗蚀剂膜厚为1.5微米,气压为1.0Pa,气体组分为CF4/Cl2 =30/30sccm(注意,sccm表示标准条件下的体积流速(cm3/分钟))。此外,ICP功率为500W,即,ICP功率密度为1.02W/cm2。注意,整个说明书中,ICP功率除以ICP面积(直径为25cm)的值取作ICP功率密度(W/cm2)。 
从图1可以理解,偏置功率密度越大,锥角α越小。另外,简单地调节偏置功率密度,可以形成希望的锥角α=5度-85度(较好是20-70度)。 
注意,图7A示出了偏置功率设为20W(偏置功率密度:0.128W/cm2)时的截面SEM照片;图7B示出了偏置功率设为30W(偏置功率密度:0.192W/cm2)时的截面SEM照片;图7C示出了偏置功率设为40W(偏置功率密度:0.256W/cm2)时的截面SEM照片;图8A示出了偏置功率设为60W(偏置功率密度:0.384W/cm2)时的截面SEM照片;图8B示出了偏置功率设为100W(偏置功率密度:0.64W/cm2)时的截面SEM照片。从图7A-8B的每幅照片可以观察到,锥角α形成在20-70度的范围内,通过改变偏置功率密度,可以控制锥角α。 
可以认为这是由于钨和抗蚀剂间的选择性变小和抗蚀剂的再处理现象发生所造成的。 
(实验2) 
图2示出了锥角α与CF4的特定流速间的关系。用CF4/Cl2=20/40sccm、30/30sccm和40/20sccm的气体组分进行实验。气体压力为1.0Pa,偏置功率密度为0.128W/cm2,抗蚀剂膜厚度为1.5微米,ICP功率为500W(ICP功率密度为1.02W/cm2)。 
从圈2可以知道,CF4的特定流速越大,钨和抗蚀剂间的选择性越大,布线的锥角α越大。另外,底膜的粗糙度变小。关于底膜的粗糙度, 认为是由于CF4流速的增大(Cl2的流速减小)造成腐蚀的弱各向异性的缘故。另外,通过简单地调节CF4的特定流速,可以形成为5-85度(较好是60-80度)的希望锥角α。 
(实验3) 
通过设定频率为13.56MHz、ICP功率为400W、500W和600W,即设定ICP的功率密度为0.82、1.02和1.22,进行实验。偏置功率为20W(偏置功率密度:0.128W/cm2),抗蚀剂膜厚度1.5微米,气压为1.0Pa,气体组分为CF4/Cl2=30/30sccm。 
在ICP功率密度变大时,钨的腐蚀速率变得较大,但腐蚀速率分布变为最差。另外,没发现锥角的特殊变化。 
(实验4) 
以1.0Pa和2.0Pa的气体压力进行实验。ICP功率为500W(ICP功率密度:1.02W/cm2),气体组分CF4/Cl2=30/30sccm,偏置功率为20W(偏置功率密度:0.128W/cm2),抗蚀剂膜厚1.5微米。 
随着真空度变高,钨腐蚀速率变快,各向异性变强。另外,在2.0Pa时,锥形变为倒锥形。 
(实验5) 
将腐蚀气体的总流速设定为60sccm和120sccm,进行实验。气体压力为1.0Pa,ICP功率为500W(ICP功率密度:1.02W/cm2),气体组分CF4/Cl2=30/30sccm,偏置功率为20W(偏置功率密度:0.128W/cm2),抗蚀剂膜厚1.5微米。 
在腐蚀气体总流速较大的情况下,腐蚀速率变大一点。 
从上述实验的结果可知,锥角与钨和抗蚀剂间的选择性有关系,因为锥角主要受偏置功率密度条件的影响。图3示出了锥角与钨和抗蚀剂间选择性的关系。 
偏置功率密度的改变对钨和抗蚀剂间选择性的影响大于对钨腐蚀速率的影响,并且,如果偏置功率密度变大,则存在钨与抗蚀剂间选择性下降的趋势。图9A示出了钨和抗蚀剂的腐蚀速率与偏置功率密度间的关系,而图9B示出了钨和抗蚀剂间选择性与偏置功率密度间的关系。 
即,如图6A和6B所示,在腐蚀钨时,同时腐蚀抗蚀剂,因此,如果钨和抗蚀剂间的选择性大,则锥角变大,如果钨和抗蚀剂间的选 择性小,则锥角变小。 
另外,如果以相同方式使CF4的特定流速较小,则存在钨和抗蚀剂间选择性下降的趋势。图10A示出了钨和抗蚀剂的腐蚀速率与特定CF4气体流速间的关系,图10B示出了钨和抗蚀剂间选择性与特定CF4 流速间的关系。 
另外,图11A示出了钨和抗蚀剂与ICP功率密度间的关系,图11B示出了钨和抗蚀剂间选择性与ICP功率密度间的关系。 
用由氮氧化硅膜构成的底膜(200nm厚)形成于绝缘基片上、且金属层叠膜(氮化钨膜和钨膜)形成于底膜上的试验片作在上述每个实验中腐蚀的试验片,但利用本发明,也可以利用选自钨膜、具有钨化合物作其主要成分的金属化合物膜薄膜、具有钨合金作其主要成分的金属合金膜中的一种薄膜或各薄膜层叠的层叠结构。然而,注意,不能应用与底膜的选择性等于或小于2.5的膜,和腐蚀速率极小的情况。例如,W-Mo合金膜(按重量计,W∶Mo =52∶48)与底膜(SiOxNy)的选择性等于或小于约1.5,腐蚀速率较小,为约50Bm/分钟,因此,从可加工的观点来看,是不合适的。 
这里示出了钨膜作为一个实例,但对于一般公知的耐热导电材料(例如Ta、Ti、Mo、Cr、Nb和Si)来说,在使用ICP腐蚀装置时,图形的边缘容易制造成锥形。例如,如果选择腐蚀速率为140-160nm/分钟且选择率为6-8的Ta膜,则与腐蚀速率为70-90nm/分钟且选择率为2-4的W膜相比,其具有优异的值。因此,从可加工性角度出发,Ta膜也是合适的,但Ta的电阻率为20-30μΩcm,比W膜的电阻率10-16μΩcm稍高,这成为一个问题。 
另外,用CF4和Cl2的气体混合物作上述干腐蚀的腐蚀气体,但不特别限于此,可以用选自C2F6和C4F8中的含氟反应气和选自Cl2、SiCl4 和BCl3的含氯气体的混合气。 
此外,不特别限于本发明的腐蚀条件,对于例如使用ICP腐蚀装置(松下电器型号:E645),且使用四氟化碳气体(CF4)和氯气(Cl2)的情况来说,操作都可以在以下范围内适当地确定腐蚀条件。 
腐蚀气总流速:60-120sccm 
特定腐蚀气体流速:CF4/Cl2=30/30sccm-50/10sccm 
气压:1.0Pa-2.0Pa 
(腐蚀气体气氛的压力) 
ICP功率密度:0.61W/cm2-2.04W/cm2(ICP功率:300W-1000W),频率为13MHz-60Mhz 
偏置功率密度:0.064W/cm2-3.2W/cm2(偏置功率:10W-500W),频率为100kHz-60MHz,较好为6MHz-29MHz 
基片温度:0℃-80℃,较好是70℃±10℃ 
注意,整个说明书中,术语“电极”表示术语“布线”的一部分,并表示与其它布线电连接的位置,或互连半导体层的位置。因此,为方便起见,尽管适当地区分“布线”和“电极”的应用,但使用“电极”一般意义上说包括“布线”。 
下面利用以下展示的各实施例详细介绍具有上述结构的本发明。 
(实施例1) 
利用图12和13介绍本发明的实施例1。这里介绍一种有源矩阵基片,该基片上具有同时制造的像素TFT和像素部分的存储电容器及形成于像素部分的外围的驱动电路TFT。 
实施例1的结构具有形成于有绝缘表面的基片101上的TFT,如图12所示。较好是使用玻璃基片或石英基片作基片101。如果耐热性可以接受的话,也可以使用塑料基片。此外,如果制造反射型显示器件,则还可以用具有形成于每个表面的绝缘膜的硅基片、金属基片或不锈钢基片作基片。 
其上形00成有TFT的基片101的表面上具有由含硅绝缘膜(整个说明书中一般是指氧化硅膜、氮化硅膜或氮氧化硅膜)构成的底膜102。例如,形成厚10-200nm(较好为50-100nm)的氮氧化硅膜102a和厚50-200nm(较好为100-150nm)的氢化氮氧化硅膜102b的层叠膜,所说氮氧化硅膜是利用等离子体CVD,由SiH4、NH3和N2O制造的,所说氢化氮氧化硅膜是由SiH4、NH3和H2类似制造的。这里示出了底膜102的两层结构,但也可以形成单层绝缘膜或具有两层以上的层叠膜。 
另外,在底膜102上形成TFT的有源层。用通过结晶具有非晶结构的半导体膜得到的结晶半导体膜作有源层。可以用例如激光退火、热退火(固相生长方法)、快速热退火(RTA法)或根据日本专利申请公开平7-130652中公开的技术利用催化元素的结晶法作结晶方 法。注意,非晶半导体膜和微晶半导体膜可作为具有非晶结构的半导体膜,也可以用例如非晶硅锗膜等具有非晶结构的化合物半导体膜。 
利用等离子体CVD或溅射,由含硅的绝缘膜,形成厚40-150nm覆盖上述TFT有源层的栅绝缘膜130。在实施例1中形成厚120nm的氮氧化硅膜。另外,通过在SiH4和N2O中掺入O2制造的氮氧化硅膜内具有减小的固定电荷密度,因此,可作为实际应用的材料。自然,栅绝缘膜不限于这类氮氧化硅膜,可以用单层或层叠结构的其它含硅绝缘膜。 
形成于栅绝缘膜上的栅电极118-122和电容电极123采用具有层叠结构的耐热导电材料,所说层叠结构由导电金属氮化物膜形成的导电层(A)和由金属膜形成的导电层(B)构成。导电层(B)由选自Ta、Ti和W中的元素、或上述元素作其主要成分的合金、或上述元素组合的合金膜形成。在实施例1中,构图形成为导电层(A)、50nm厚的WN膜和形成为导电层(B)、250nm厚的W膜构成的导电层叠膜,完成栅电极118-122和电容器电极123。其中导电层(B)是通过利用纯度为6N的W靶、并引入Ar气和氮(N2)气的溅射形成的。注意,进行腐蚀,在栅电极118-123的边缘形成锥形部分。该腐蚀工艺利用ICP腐蚀装置进行。该技术的细节如本发明的实施模式中所介绍的。实施例1中,利用CF4和Cl2的气体混合物作腐蚀气、用每种气体30sccm的流速、设定为3.2W/cm2(频率:13.56MHz)的ICP功率密度、设定为0.224W/cm2(频率:13.56MHz)的偏置功率密度、和1.0Pa的气体压力进行腐蚀。利用这些腐蚀条件,在栅极118-122和电容电极123的边缘部分形成锥形部分,其中厚度从边缘部分向着内部逐渐增大。该角度可以制成为25-35度,较好是30度。 
注意,为了在形成具有锥形的栅电极118-122和电容电极123时进行腐蚀而不留下任何残留物,进行重叠腐蚀,其中腐蚀时间增加10-20%,因此,栅绝缘膜130具有实际变薄的部分。 
另外,在实施例1中,为形成LDD区,用在其边缘具有锥形部分的栅电极118-122作掩模,通过离子掺杂,以自对准方式,在有源层中掺入产生n型或p型导电的杂质元素。另外,为形成合适且希望的LDD区,用抗蚀剂图形作掩模,通过离子掺杂,在有源层内掺入产生n型或p型导电的杂质元素。 
于是在驱动电路的第一p沟道TFT(A)200a中,形成有源层内的沟道形成区206、与栅极重叠的LDD区207、由高浓度p型杂质区构成的源区208、和漏区209。第一n沟道TFT(A)201a在有源层内具有沟道形成区210、由低浓度n杂质区构成且与栅极119重叠的LDD区211、由高浓度n型杂质区构成的源区212和漏区213。与栅极119重叠的LDD区表示为Lov,对于沟道长度为3-7微米的沟道来说,在沟道的纵向,其长度为0.1-1.5微米,较好是0.3-0.8微米。Lov的长度控制栅电极119的厚度和锥形部分的角度。 
另外,类似地,驱动电路的第二p沟道TFT(A)202a的有源层具有沟道形成区214、与栅极120重叠的LDD区215、由高浓度p型杂质区形成的源区216和漏区217。在第二n沟道TFT(A)203a中,有源层具有沟道形成区218、与栅电极121重叠的LDD区219、由高浓度n型杂质区形成的源区220和漏区221。LDD区219具有与LDD区211相同的结构。像素TFT204在有源层内具有沟道形成区222a和222b、由低浓度n型杂质区形成的LDD区223a和223b、由高浓度n杂质区形成的源或漏区225-227。LDD区223a和223b具有与LDD区211相同的结构。此外,存储电容205由电容布线123、栅绝缘膜和与像素TFT204的漏区227连接的半导体层228和229形成。图12中,驱动电路的n沟道TFT和p沟道TFT具有单栅结构,其中一个栅极提供在源和漏对之间,像素TFT具有双栅结构,但所有TFT都可以给予单栅结构,在源和漏对之间提供多个栅极的多栅结构也不会造成问题。 
另外,有覆盖栅电极的保护绝缘膜142和绝缘膜130。保护绝缘膜可由氧化硅膜、氮氧化硅膜、氮化硅膜或这些膜组合的层叠膜构成。 
此外,还有由有机绝缘材料构成的、覆盖保护绝缘膜142的层间绝缘膜143。可用例如聚酰亚胺、丙烯酸、聚酰胺、聚酰亚胺酰胺和BCB(苯并环丁烯)作有机树脂材料。 
另外,层间绝缘膜143上具有源布线和漏布线,用于通过接触孔连接形成于各有源层上的源区和漏区。注意,源布线和漏布线具有层叠结构,该层叠结构由参考数字144a-154a表示的Ti和铝的层叠膜和参考数字144b-154b表示的透明导电膜构成。另外,漏布线153a和153b还用作像素电极,透明导电膜的合适材料有氧化铟和氧化锌合金(In2O3 -ZnO)和氧化锌(ZnO),为了另外增大透射率和导电性,可以使用例如加入了镓(Ga)的氧化锌(ZnO:Ga)等材料。 
利用上述结构,构成每种电路的TFT的结构可以根据像素TFT和驱动电路要求的规格优化,可以加强半导体器件的工作性能和可靠性。此外,通过用具有耐热性的导电材料形成栅电极,LDD区和源区和漏区的激活变得较容易。 
此外,在形成通过栅绝缘膜与栅极重叠的LDD区期间,通过形成具有为控制导电类型掺入的杂质元素浓度梯度的LDD区,预计可以增强特别是漏区附近的电场驰豫效应。 
在作为透射型液晶显示器件时,可应用图12所示的有源矩阵基片。 
下面利用图13介绍应用图12所示有源矩阵基片的有源矩阵型液晶显示器件。 
首先,构图有源矩阵基片上的树脂膜,形成棒状间隔件405a-405e和406。间隔件的位置可任意设定。注意,可以利用通过分散尺寸为几微米的晶粒形成间隔件的方法。 
然后,在有源矩阵基片的像素部分中,由例如聚酰亚胺树脂等材料形成校准膜407,以使液晶取向。形成校准膜后,进行研磨处理,使液晶分子取向,以便具有某一固定的预定倾角。 
在相对侧的相对基片401上形成光屏蔽膜402、透明导电膜403、和校准膜404。光屏蔽膜402由例如Ti膜、Cr膜或Al膜形成,厚为150-300nm。然后,利用密封部件408将其上形成有像素部分和驱动电路的有源矩阵基片和相对基片接合在一起。 
然后,在两基片间注入液晶材料409。液晶材料可使用已知的液晶材料。例如,除TN液晶外,也可以使用指示透射率随电场连续变化的电-光响应的无阈值反铁电混合液晶。某些无阈值反铁电混合液晶具有V形电-光响应特性。于是完成了图13所示的反射型有源矩阵液晶显示器件。 
(实施例2) 
利用图14,实施例2示出了一个制造使用不同于上述实施例1(顶栅TFT)的底栅TFT的显示器件的实例。 
首先,在绝缘基片1801上溅射形成金属层叠膜。金属层叠膜用氮 化钨膜作底层,用W膜作顶层。注意,与基片接触的底膜也可由例如表示为SiOxNy的氮氧化硅膜形成。然后,通过光刻形成用于得到希望栅布线图形的抗蚀掩模。 
需要例如栅绝缘膜和沟道形成区等结构形成于底栅TFT的栅布线上。为了增强底栅结构TFT的特性、在栅布线上形成覆盖膜和栅绝缘膜的耐压,栅布线1802-1805的锥角较好是等于或小于60度,更好是等于或小于40度。 
然后,如本发明的实施模式中介绍的,利用ICP腐蚀装置,并选择合适的偏置功率和特定气体流速,使栅布线1802-1805的锥角等于或小于60度,更好是等于或小于40度。随后的处理可使用已知技术,这里不再具体介绍。 
图14中,参考数字1814表示CMOS电路,参考数字1815表示n沟道TFT,1816表示像素TFT,1817表示层间绝缘膜,1818a表示像素电极,1818b表示ITO膜。形成ITO膜1818b的目的是通过粘合剂1822与例如FPC 1823等外部端子连接。另外,参考数字1819表示液晶材料,1820表示相对电极。此外,参考数字1801表示第一基片,1808表示密封区,1807和1809-1812表示棒形间隔件,1821表示第二基片。 
注意,可以自由组合实施例2和实施例1。 
(实施例3) 
图15A-15F展示了利用本发明在绝缘表面上形成各种布线结构的例子。图15A示出了由钨作其主要成分的材料1501构成、且形成于具有绝缘表面的膜(或基片)1500上的单层结构布线的剖面图。该布线通过构图由采用纯度为6N(99.9999%)的靶、用一种气体如氩(Ar)气作溅射气体的溅射形成的膜形成。注意,通过将基片温度设为等于或低于300℃,并将溅射气体压力设为等于或高于1.0Pa,来控制应力,其它条件(例如溅射功率)可由操作者适当地确定。 
在进行上述构图时,根据例如偏置功率密度,利用本发明实施模式中所介绍的方法控制锥角α。 
这样得到的布线1501的截面形状具有希望的锥角α。另外,布线1501中几乎没有杂质元素,特别是可使所含氧量等于或小于30ppm,使电阻率等于或小于20μΩcm,一般为6-15μΩcm。另外,可以将膜应力控制在-5×1010-5×1010达因/cm2。 
图15B示出了与实施例1的栅极类似的两层结构。注意,氮化钨(WNx)用作下层,钨用作上层。另外,注意,氮化钨膜1502的厚度可以设为从10-50nm(较好是10-30nm),钨膜1503的厚度可以设为200-400nm(较好是250-350nm)。实施例3中,利用溅射,在不暴露于大气的情况下,连续层叠两层膜。 
图15C是利用绝缘膜1505覆盖由具有钨作其主要成分的材料构成、且形成于具有绝缘表面的膜(或基片)1500上的布线1504的例子。绝缘膜1505由氮化硅膜、氧化硅膜和氮氧化硅膜SiOxNy(其中0<x,y<1)形成,或由这些膜组合的层叠膜形成。 
图15D是用氮化钨膜1507覆盖由具有钨作其主要成分的材料构成、且形成于具有绝缘表面的膜(或基片)1500上的布线1506的表面的例子。注意,如果对图15A所示状态的布线进行例如等离子体硝化等硝化处理,则可以得到图15D的结构。 
图15E是用氮化钨膜1510和1508覆盖由具有钨作其主要成分的材料构成、且形成于具有绝缘表面的膜(或基片)1500上的布线1509的例子。注意,如果对图15B所示状态的布线进行例如等离子体硝化等硝化处理,则可以得到图15E的结构。 
图15F是形成图15E状态后利用绝缘膜1511覆盖的例子。绝缘膜1511可由氮化硅膜、氧化硅膜、氮氧化硅膜或这些膜的层叠膜形成。 
所以,本发明可应用于各种布线结构。可以自由地组合实施例3的结构与实施例1和2所示结构。 
(实施例4) 
实施例4中介绍了一种将本发明应用于在硅基片上制造的反射型液晶显示器件的情况。代替实施例1中包括结晶硅膜的有源层,直接在硅基片(硅晶片)中掺入产生n型或p型导电的杂质元素,可以实现这种TFT结构,另外,该结构是反射型的,因此,可以用具有高反射率(例如,铝、银、或它们的合金(Al-Ag合金))的金属膜等作像素电极。 
注意,可以自由地组合实施例4的结构与实施例1-3的结构。 
(实施例5) 
当在常规MOSFET上形成层间绝缘膜,然后在其上形成TFT时,可以应用本发明。换言之,可以实现三锥结构的半导体器件。另外, 可以便用例如SIMOX、Smart-cut(SOITEC公司的一种商标)或ELTRAN(佳能公司的一种商标)等SOI基片。 
注意,可以自由组合实施例5的结构与实施例1-4的结构。 
(实施例6) 
可以将本发明应用于有源矩阵EL显示器。图16示出了一个例子。 
图16是有源矩阵EL显示器的电路图。参考数字81表示像素部分,X方向驱动电路82和Y方向驱动电路83形成于其外围。另外,像素部分81中的每个像素包括开关TFT 84、电容器85、电流控制TFT86和有机EL元件87,开关TFT84接X方向信号线88a(或88b),和Y方向信号线89a(或89b,89c)。另外,电源线90a和90b接电流控制TFT86。 
在本实施例中的有源矩阵EL显示器中,通过组合图12中的p沟道TFT200a或202a和图12中的n沟道TFT201a或203a,可以形成用于X方向驱动电路82、Y方向驱动电路83和电流控制TFT86的TFT。用于开关TFT84的TFT可由图12中的n沟道TFT204形成。 
可以自由组合本发明的有源矩阵EL显示器与实施例1-5的结构。 
(实施例7) 
下面结合图17介绍实施例1中图13所示有源矩阵液晶显示器件的结构。有源矩阵基片(第一基片)包括形成于玻璃基片801上的像素部分802、栅侧驱动电路803和源侧驱动电路804。像素部分的像素TFT805(对应于图13中的像素TFT204)是n沟道TFT,并与像素电极806和存储电极807(对应于图13中的存储电容205)连接。 
外围中的驱动电路由CMOS电路作为基础。栅侧驱动电路803和源侧驱动电路804分别通过栅布线808和源布线809连接像素部分802。另外,输入-输出布线(连接布线)812和813设于与用于将信号传输到驱动电路的FPC810连接的外部输入-输出端子811中。参考数字814是相对基片(第二基片)。 
注意,尽管本说明书中图17所示的半导体器件是指有源矩阵液晶显示器件,但图17所示的用FPC完成的液晶屏板一般称作液晶组件。因此,可以称该实施例的有源矩阵液晶显示器件作液晶组件。 
(实施例8) 
通过实施本发明制造的TFT可应用于各种电-光器件。即,本发明可应用于引入这种电-光器件作显示部分的所有电子设备。 
这些电子设备的例子包括:视频摄像机、数字摄像机、头戴式显示器(眼镜式显示器)、可穿式显示器、汽车导航系统、个人电脑和便携式信息终端(例如移动电脑,便携式电话,电子计事本等)。图18A-18F示出这些电子设备的例子。 
图18A示出了个人电脑,包括:主体2001、图像输入部分2002、显示部分2003、键盘2004。本发明可应用于图像输入部分2002、显示部分2003或其它信号驱动电路。 
图18B示出了视频摄像机,包括:主体2101、显示部分2102、音频输入部分2103、操作开关2104、电池2105和图像接收部分2106。本发明可应用于显示部分2102、音频输入部分2103或其它信号控制电路。 
图18C示出了便携式电脑,包括:主体2201、摄像部分2202、图像接收部分2203、操作开关2204和显示部分2205。本发明可应用于显示部分2205或其它信号驱动电路。 
图18D示出了眼镜式显示器,包括:主体2301、显示部分2302、臂部2303。本发明可应用于显示部分2302或其它信号驱动电路。 
图18E示出了采用存储有程序的记录媒质(此后称之为记录媒质)的播放器,包括:主体2401、显示部分2402、扬声器单元2403、记录媒质2404和操作开关2405。注意,使用DVD(数字通用盘)或CD作该装置的记录媒质,能够再现音乐程序,显示图像,并进行游戏,或用于国际互联网。本发明可应用于显示器件2402和其它信号驱动电路。 
图18F示出了数字摄像机,包括:主体2501、显示部分2502、目镜部分2503、操作开关2504、和图像接收单元(图中未示出)。本发明可应用于显示单元2502或其它信号驱动电路。 
如上所述,本发明的应用范围很宽,可应用于各种领域的电子设备。另外,本实施例的电子设备可利用实施例1-7的任何一种组合实现。 
(实施例9) 
通过实施本发明制造的TFT可应用于各种电-光器件。即,本发 明可应用于引入这种电-光器件作显示部分的电子设备。 
关于这种电子设备,可以给出投影仪(背置型或前置型)等。图19A-19D示出了几个例子。 
图19A示出了前置型投影仪,它包括投影系统2601和屏2602。本发明可应用于构成投影系统2601的一部分的液晶显示器件2808或其它信号控制电路。 
图19B示出了背置型投影仪,它包括主体2701、投影系统2702、反射镜2703、屏2704。本发明可应于构成投影系统2702一部分的液晶显示器件2808或其它信号控制电路。 
图19C是展示图19A和19B中的显示器件2601和2702的结构实例的示图。投影系统2601和2702包括:光源光学系统2801、反射镜2802和2804-2806、分光镜2803、棱镜2807、液晶显示器件2808、相差板2809、和投影光学系统2810构成。投影光学系统2810由包括透镜的光学系统构成。尽管本实施例示出了三板系统的例子,但并不限于这种系统,也可以采用单板系统光学系统。操作者可以在图19C中箭头所示的光学路径中适当地设置例如光学透镜、偏振膜、调相膜、IR膜等。 
此外,图19D示出了图19C的光源光学系统2801的结构的实例。该例中,光源光学系统2801包括反射器2811、光源2812、透镜阵列2813和2814、偏振转换元件2815及会聚透镜2816。顺便提及,图19D所示的光源光学系统是一个实例,本发明不限于该图所示的结构。例如,操作者可以在该光源光学系统中适当地设置光学透镜、偏振膜、调相膜、IR膜等。 
如上所述,本发明的应用范围非常广泛,可应用于各种领域的电子设备。另外,本例的电子设备可利用实施例1-3和7的任何组合的结构实现。然而,如果本实施例的投影系统是透射型液晶显示器件,无需说它们不能应用于反射型液晶显示器件。 
通过适当地设置通过能够控制布线的锥角α的偏置功率和特定气体流速等条件,可以提高相对于底膜的选择性,同时,根据本发明可以得到希望的锥角α。结果,形成于布线上的膜的覆盖较好,因此可以减少例如布线剥落、布线漏电和短路等缺陷。 
另外,可以腐蚀得使该部分内具有良好的分布,并可以得到均匀的 布线形状。 
另外,本发明可应用于接触孔等的开口工艺。 

Claims (26)

1.一种制造有源矩阵显示器件的方法,包括:
在绝缘基片上形成金属膜;
当对电极施加偏置功率时通过ICP腐蚀来腐蚀金属膜以形成布线,其中所述绝缘基片由电极支撑,
其中所述布线具有锥角在5°至60°的范围内的锥形侧表面,并且所述锥角由所述偏置功率密度来控制。
2.根据权利要求1的方法,其中,通过采用腐蚀气体来进行所述ICP腐蚀,所述腐蚀气体包含第一反应气体和第二反应气体,所述第一反应气体包含氟,所述第二反应气体包含氯。
3.根据权利要求1的方法,其中,所述金属膜包括选自包含钨、钽、钛和钼的组的金属。
4.根据权利要求1的方法,其中,所述布线是栅布线。
5.根据权利要求1的方法,其中,通过采用多螺旋线圈来进行所述ICP腐蚀。
6.根据权利要求1的方法,其中,所述布线具有锥角为40°或更小的锥形侧表面。
7.根据权利要求1的方法,其中,所述金属膜包括氮化钨的第一层和形成在第一层上的钨的第二层。
8.根据权利要求1的方法,其中,所述有源矩阵显示器件是有源矩阵液晶显示器件。
9.一种制造有源矩阵显示器件的方法,包括:
在绝缘基片上形成金属膜;
当对电极施加偏置功率时通过ICP腐蚀来腐蚀金属膜以形成包括薄膜晶体管的栅电极的栅布线,其中所述绝缘基片由电极支撑,
其中所述栅布线具有锥角在5°至60°的范围内的锥形侧表面,并且所述锥角由所述偏置功率密度来控制。
10.根据权利要求9的方法,其中,通过采用腐蚀气体来进行所述ICP腐蚀,所述腐蚀气体包含第一反应气体和第二反应气体,所述第一反应气体包含氟,所述第二反应气体包含氯。
11.根据权利要求9的方法,其中,所述金属膜包括选自包含钨、钽、钛和钼的组的金属。
12.根据权利要求9的方法,其中,通过向多螺旋线圈施加功率产生所述等离子体。
13.根据权利要求9的方法,其中,所述布线具有锥角为40°或更小的锥形侧表面。
14.根据权利要求9的方法,其中,所述金属膜包括氮化钨的第一层和形成在第一层上的钨的第二层。
15.根据权利要求9的方法,还包括以下步骤:
在栅电极上形成栅绝缘膜;以及
在栅电极上形成半导体层且栅绝缘膜介于其间。
16.根据权利要求15的方法,其中,通过采用腐蚀气体来进行所述ICP腐蚀,所述腐蚀气体包含第一反应气体和第二反应气体,所述第一反应气体包含氟,所述第二反应气体包含氯。
17.根据权利要求15的方法,其中,所述金属膜包括选自包含钨、钽、钛和钼的组的金属。
18.根据权利要求15的方法,其中,通过采用多螺旋线圈来进行所述ICP腐蚀。
19.根据权利要求15的方法,其中,所述布线具有锥角为40°或更小的锥形侧表面。
20.根据权利要求15的方法,其中,所述金属膜包括氮化钨的第一层和形成在第一层上的钨的第二层。
21.一种制造有源矩阵显示器件的方法,包括:
在绝缘基片上形成金属膜;
在所述金属膜上形成抗蚀剂掩模图形;
当对电极施加偏置功率时通过ICP腐蚀来腐蚀所述抗蚀剂掩模图形和金属膜以形成包括栅电极的栅布线,在所述室中绝缘基片由电极支撑;以及
在栅电极上形成栅绝缘膜;以及
在栅电极上形成半导体层且栅绝缘膜介于其间,
其中所述栅布线具有锥角在5°至60°的范围内的锥形侧表面,并且所述锥角由所述偏置功率密度和所述腐蚀气体的气体流速来控制。
22.根据权利要求21的方法,其中,通过采用腐蚀气体来进行所述ICP腐蚀,所述腐蚀气体包含第一反应气体和第二反应气体,所述第一反应气体包含氟,所述第二反应气体包含氯。
23.根据权利要求21的方法,其中,所述金属膜包括选自包含钨、钽、钛和钼的组的金属。
24.根据权利要求21的方法,其中,通过采用多螺旋线圈来进行所述ICP腐蚀。
25.根据权利要求21的方法,其中,所述布线具有锥角为40°或更小的锥形侧表面。
26.根据权利要求21的方法,其中,所述金属膜包括氮化钨的第一层和形成在第一层上的钨的第二层。
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Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001035808A (ja) * 1999-07-22 2001-02-09 Semiconductor Energy Lab Co Ltd 配線およびその作製方法、この配線を備えた半導体装置、ドライエッチング方法
TW480554B (en) * 1999-07-22 2002-03-21 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
TWI286338B (en) * 2000-05-12 2007-09-01 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
US6872604B2 (en) * 2000-06-05 2005-03-29 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a light emitting device
US6809012B2 (en) * 2001-01-18 2004-10-26 Semiconductor Energy Laboratory Co., Ltd. Method of making a thin film transistor using laser annealing
JP2002246369A (ja) * 2001-02-15 2002-08-30 Sharp Corp 薄膜ドライエッチング方法
JP4926329B2 (ja) 2001-03-27 2012-05-09 株式会社半導体エネルギー研究所 半導体装置およびその作製方法、電気器具
SG116443A1 (en) * 2001-03-27 2005-11-28 Semiconductor Energy Lab Wiring and method of manufacturing the same, and wiring board and method of manufacturing the same.
JP4854874B2 (ja) * 2001-06-22 2012-01-18 東京エレクトロン株式会社 ドライエッチング方法
DE10133873B4 (de) 2001-07-12 2005-04-28 Infineon Technologies Ag Verfahren zur Herstellung von Kontakten für integrierte Schaltungen
JP2003045874A (ja) 2001-07-27 2003-02-14 Semiconductor Energy Lab Co Ltd 金属配線およびその作製方法、並びに金属配線基板およびその作製方法
US6773944B2 (en) 2001-11-07 2004-08-10 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
JP4131813B2 (ja) * 2002-10-24 2008-08-13 株式会社半導体エネルギー研究所 プラズマエッチング方法及び半導体装置の作製方法
US7485579B2 (en) * 2002-12-13 2009-02-03 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
KR20050052029A (ko) * 2003-11-28 2005-06-02 삼성에스디아이 주식회사 박막트랜지스터
JP4519512B2 (ja) * 2004-04-28 2010-08-04 株式会社半導体エネルギー研究所 半導体装置の作製方法、除去方法
TWI382455B (zh) * 2004-11-04 2013-01-11 Semiconductor Energy Lab 半導體裝置和其製造方法
KR20060059565A (ko) * 2004-11-29 2006-06-02 삼성전자주식회사 다층 배선, 이의 제조 방법 및 이를 갖는 박막트랜지스터
CN101313413B (zh) * 2005-11-18 2011-08-31 株式会社半导体能源研究所 光电转换装置
JP4865361B2 (ja) * 2006-03-01 2012-02-01 株式会社日立ハイテクノロジーズ ドライエッチング方法
TWI316295B (en) 2006-05-17 2009-10-21 Au Optronics Corp Thin film transistor
TWI329232B (en) * 2006-11-10 2010-08-21 Au Optronics Corp Pixel structure and fabrication method thereof
JP4346636B2 (ja) 2006-11-16 2009-10-21 友達光電股▲ふん▼有限公司 液晶表示装置
US20090035939A1 (en) * 2007-07-31 2009-02-05 Motorola, Inc. Fabrication method to minimize ballast layer defects
JP5377940B2 (ja) * 2007-12-03 2013-12-25 株式会社半導体エネルギー研究所 半導体装置
CN102024696B (zh) * 2009-09-11 2012-08-22 中芯国际集成电路制造(上海)有限公司 开口及其形成方法
CN102054755B (zh) * 2009-11-10 2014-09-03 中芯国际集成电路制造(上海)有限公司 互连结构及其形成方法
JP5709505B2 (ja) * 2010-12-15 2015-04-30 東京エレクトロン株式会社 プラズマ処理装置、プラズマ処理方法、および記憶媒体
US20130184535A1 (en) 2012-01-10 2013-07-18 The Board Of Trustees Of The Leland Stanford Junior University Expandable tissue retraction devices
KR20140129249A (ko) * 2012-03-02 2014-11-06 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 텅스텐 소결체 스퍼터링 타깃 및 그 타깃을 사용하여 성막한 텅스텐 막
CN103117219B (zh) * 2013-01-30 2015-08-26 常州同泰光电有限公司 一种可控形貌的刻蚀方法
US10062493B2 (en) * 2013-11-26 2018-08-28 Samsung Electro-Mechanics Co., Ltd. Electronic component and circuit board having the same mounted thereon
JP6431278B2 (ja) * 2014-04-18 2018-11-28 株式会社ジャパンディスプレイ 表示装置用基板
FR3027380A1 (fr) * 2014-10-17 2016-04-22 Commissariat Energie Atomique Dispositif de refroidissement par liquide caloporteur pour composants electroniques
CN105655231B (zh) * 2014-11-13 2018-07-06 北京北方华创微电子装备有限公司 一种刻蚀用掩膜组及应用其的衬底刻蚀方法
KR102430573B1 (ko) * 2015-05-14 2022-08-08 엘지디스플레이 주식회사 박막 트랜지스터 및 이를 포함한 백플레인 기판
JP6510067B2 (ja) * 2015-11-06 2019-05-08 シャープ株式会社 表示基板、表示装置及び表示基板の製造方法
CN105609415B (zh) * 2015-12-25 2018-04-03 中国科学院微电子研究所 一种刻蚀方法
JP6828595B2 (ja) * 2017-05-29 2021-02-10 三菱電機株式会社 半導体装置の製造方法
WO2019094502A1 (en) 2017-11-07 2019-05-16 Prescient Surgical, Inc. Methods and apparatus for prevention of surgical site infection
JP6665888B2 (ja) 2018-06-22 2020-03-13 セイコーエプソン株式会社 電気光学装置および電子機器
KR102565148B1 (ko) * 2018-06-27 2023-08-18 서울바이오시스 주식회사 플립칩형 발광 다이오드 칩 및 그것을 포함하는 발광 장치
CN109671622A (zh) * 2018-12-20 2019-04-23 深圳市华星光电半导体显示技术有限公司 Cu膜、薄膜晶体管及阵列基板的制备方法
US11631529B2 (en) * 2019-03-19 2023-04-18 Tdk Corporation Electronic component and coil component

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5185058A (en) * 1991-01-29 1993-02-09 Micron Technology, Inc. Process for etching semiconductor devices
US5302240A (en) * 1991-01-22 1994-04-12 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5580385A (en) * 1994-06-30 1996-12-03 Texas Instruments, Incorporated Structure and method for incorporating an inductively coupled plasma source in a plasma processing chamber
US5779926A (en) * 1994-09-16 1998-07-14 Applied Materials, Inc. Plasma process for etching multicomponent alloys
US5880035A (en) * 1992-06-29 1999-03-09 Sony Corporation Dry etching method
CN1221809A (zh) * 1997-11-14 1999-07-07 西门子公司 Al基金属层的刻蚀方法

Family Cites Families (148)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US16028A (en) * 1856-11-04 Throstle spinning-machine
US55841A (en) * 1866-06-26 Improved brick-machine
US110941A (en) * 1871-01-10 Improvement in book-cases for schools
US17685A (en) * 1857-06-30 Improvement in self-acting rakes for harvesters
US52950A (en) * 1866-03-06 Iproveivient in tailorsj measures
US49197A (en) * 1865-08-01 Improved life-boat
US6705A (en) * 1849-09-11 Jointed pawl
US30322A (en) * 1860-10-09 Machine pob straightening bale-hoops
US13022A (en) * 1855-06-05 peters
US3115379A (en) * 1961-11-29 1963-12-24 United Carr Fastener Corp Electrical connector
US4233109A (en) 1976-01-16 1980-11-11 Zaidan Hojin Handotai Kenkyu Shinkokai Dry etching method
US4394182A (en) 1981-10-14 1983-07-19 Rockwell International Corporation Microelectronic shadow masking process for reducing punchthrough
US4851363A (en) 1986-07-11 1989-07-25 General Motors Corporation Fabrication of polysilicon fets on alkaline earth alumino-silicate glasses
US4885074A (en) 1987-02-24 1989-12-05 International Business Machines Corporation Plasma reactor having segmented electrodes
JPS6432627A (en) 1987-07-29 1989-02-02 Hitachi Ltd Low-temperature dry etching method
JPH0194664A (ja) 1987-10-05 1989-04-13 Nec Corp 電界効果トランジスタ
JPH01207973A (ja) * 1988-02-16 1989-08-21 Seiko Epson Corp Mos型半導体装置の製造方法
JP2695822B2 (ja) 1988-03-22 1998-01-14 株式会社日立製作所 プラズマエッチング方法
JPH0687501B2 (ja) 1988-09-29 1994-11-02 シャープ株式会社 半導体装置のゲート電極の製造方法
JP2923962B2 (ja) 1989-02-02 1999-07-26 ソニー株式会社 エッチング方法
JPH03147328A (ja) 1989-11-01 1991-06-24 Toshiba Corp 半導体装置の製造方法
JPH04261017A (ja) 1991-02-14 1992-09-17 Mitsubishi Electric Corp 薄膜トランジスタアレイ基板の製造方法
US5153540A (en) * 1991-04-01 1992-10-06 Amphenol Corporation Capacitor array utilizing a substrate and discoidal capacitors
FR2680276B1 (fr) * 1991-08-05 1997-04-25 Matra Mhs Procede de controle du profil de gravure d'une couche d'un circuit integre.
JP3238437B2 (ja) 1991-09-26 2001-12-17 株式会社東芝 半導体装置およびその製造方法
DE69325110T2 (de) * 1992-03-13 1999-12-09 Kopin Corp Am kopf getragene anzeigevorrichtung
US6262784B1 (en) * 1993-06-01 2001-07-17 Samsung Electronics Co., Ltd Active matrix display devices having improved opening and contrast ratios and methods of forming same and a storage electrode line
KR970010652B1 (ko) 1992-07-06 1997-06-30 가부시키가이샤 한도오따이 에네루기 겐큐쇼 박막형 반도체 장치 및 그 제작방법
US5470768A (en) 1992-08-07 1995-11-28 Fujitsu Limited Method for fabricating a thin-film transistor
JPH06132257A (ja) 1992-10-22 1994-05-13 Toshiba Corp 半導体素子の製造方法
JP3587537B2 (ja) * 1992-12-09 2004-11-10 株式会社半導体エネルギー研究所 半導体装置
TW435820U (en) 1993-01-18 2001-05-16 Semiconductor Energy Lab MIS semiconductor device
JP3352744B2 (ja) 1993-01-18 2002-12-03 株式会社半導体エネルギー研究所 Mis型半導体装置の作製方法
US5830787A (en) 1993-03-18 1998-11-03 Lg Semicon Co., Ltd. Method for fabricating a thin film transistor
JP3474604B2 (ja) 1993-05-25 2003-12-08 三菱電機株式会社 薄膜トランジスタおよびその製法
TW264575B (zh) * 1993-10-29 1995-12-01 Handotai Energy Kenkyusho Kk
JP3285438B2 (ja) 1993-10-29 2002-05-27 三菱電機株式会社 半導体記憶装置
US5923962A (en) * 1993-10-29 1999-07-13 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
JP3431033B2 (ja) 1993-10-29 2003-07-28 株式会社半導体エネルギー研究所 半導体作製方法
JPH07202047A (ja) 1994-01-11 1995-08-04 Fujitsu Ltd 半導体装置の製造方法
US5413669A (en) * 1994-02-07 1995-05-09 Applied Materials, Inc. Metal CVD process with post-deposition removal of alloy produced by CVD process
JP3398453B2 (ja) 1994-02-24 2003-04-21 株式会社東芝 薄膜トランジスタの製造方法
US5980767A (en) * 1994-02-25 1999-11-09 Tokyo Electron Limited Method and devices for detecting the end point of plasma process
US5528082A (en) * 1994-04-28 1996-06-18 Xerox Corporation Thin-film structure with tapered feature
JPH07321328A (ja) * 1994-05-27 1995-12-08 Hitachi Ltd 薄膜トランジスタ駆動液晶表示装置およびその製法
JP3312083B2 (ja) 1994-06-13 2002-08-05 株式会社半導体エネルギー研究所 表示装置
TW321731B (zh) * 1994-07-27 1997-12-01 Hitachi Ltd
US5795208A (en) * 1994-10-11 1998-08-18 Yamaha Corporation Manufacture of electron emitter by replica technique
JPH08116065A (ja) 1994-10-12 1996-05-07 Sony Corp 薄膜半導体装置
JPH08122821A (ja) * 1994-10-28 1996-05-17 Hitachi Ltd 液晶表示装置およびその製造方法
EP0742847B1 (en) 1994-11-30 2000-05-24 Micron Technology, Inc. A method of depositing tungsten nitride using a source gas comprising silicon
US5716534A (en) * 1994-12-05 1998-02-10 Tokyo Electron Limited Plasma processing method and plasma etching method
JPH08199377A (ja) 1995-01-24 1996-08-06 Sony Corp プラズマエッチング装置およびプラズマエッチング方法
JP3329128B2 (ja) * 1995-03-28 2002-09-30 ソニー株式会社 半導体装置の製造方法
US6042686A (en) 1995-06-30 2000-03-28 Lam Research Corporation Power segmented electrode
JP3535615B2 (ja) * 1995-07-18 2004-06-07 株式会社ルネサステクノロジ 半導体集積回路装置
JP3535276B2 (ja) 1995-07-28 2004-06-07 株式会社半導体エネルギー研究所 エッチング方法
JPH0955508A (ja) 1995-08-10 1997-02-25 Sanyo Electric Co Ltd 薄膜トランジスタ及びその製造方法
TW279240B (en) * 1995-08-30 1996-06-21 Applied Materials Inc Parallel-plate icp source/rf bias electrode head
KR0186206B1 (ko) * 1995-11-21 1999-05-01 구자홍 액정표시소자 및 그의 제조방법
TW309633B (zh) 1995-12-14 1997-07-01 Handotai Energy Kenkyusho Kk
JP3188167B2 (ja) 1995-12-15 2001-07-16 三洋電機株式会社 薄膜トランジスタ
JP2865039B2 (ja) 1995-12-26 1999-03-08 日本電気株式会社 薄膜トランジスタ基板の製造方法
KR0179792B1 (ko) * 1995-12-27 1999-04-15 문정환 고밀도 플라즈마 식각장비를 이용한 슬로프 콘택 홀 형성방법
US6036878A (en) * 1996-02-02 2000-03-14 Applied Materials, Inc. Low density high frequency process for a parallel-plate electrode plasma reactor having an inductive antenna
KR970064327A (ko) * 1996-02-27 1997-09-12 모리시다 요이치 고주파 전력 인가장치, 플라즈마 발생장치, 플라즈마 처리장치, 고주파 전력 인가방법, 플라즈마 발생방법 및 플라즈마 처리방법
JP3208079B2 (ja) 1996-02-27 2001-09-10 松下電器産業株式会社 高周波電力印加装置及びプラズマ処理装置
JP3844538B2 (ja) 1996-03-22 2006-11-15 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5702258A (en) * 1996-03-28 1997-12-30 Teradyne, Inc. Electrical connector assembled from wafers
US5824606A (en) * 1996-03-29 1998-10-20 Lam Research Corporation Methods and apparatuses for controlling phase difference in plasma processing systems
JP3574270B2 (ja) * 1996-04-17 2004-10-06 三菱電機株式会社 Alテーパドライエッチング方法
US6043100A (en) * 1996-04-19 2000-03-28 Weaver; Kevin Chip on tape die reframe process
JP3593212B2 (ja) 1996-04-27 2004-11-24 株式会社半導体エネルギー研究所 表示装置
JP3961044B2 (ja) 1996-05-14 2007-08-15 シャープ株式会社 電子回路装置
JPH09326494A (ja) 1996-06-04 1997-12-16 Semiconductor Energy Lab Co Ltd 半導体回路およびその形成方法
US6008139A (en) * 1996-06-17 1999-12-28 Applied Materials Inc. Method of etching polycide structures
US5667631A (en) * 1996-06-28 1997-09-16 Lam Research Corporation Dry etching of transparent electrodes in a low pressure plasma reactor
US6209480B1 (en) * 1996-07-10 2001-04-03 Mehrdad M. Moslehi Hermetically-sealed inductively-coupled plasma source structure and method of use
TW349234B (en) 1996-07-15 1999-01-01 Applied Materials Inc RF plasma reactor with hybrid conductor and multi-radius dome ceiling
KR100241287B1 (ko) * 1996-09-10 2000-02-01 구본준 액정표시소자 제조방법
JPH1098162A (ja) 1996-09-20 1998-04-14 Hitachi Ltd 半導体集積回路装置の製造方法
JP3305961B2 (ja) 1996-09-26 2002-07-24 株式会社東芝 多結晶シリコン薄膜トランジスタの製造方法
US5923999A (en) 1996-10-29 1999-07-13 International Business Machines Corporation Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device
US6445004B1 (en) 1998-02-26 2002-09-03 Samsung Electronics Co., Ltd. Composition for a wiring, a wiring using the composition, manufacturing method thereof, a display using the wiring and a manufacturing method thereof
US5883007A (en) 1996-12-20 1999-03-16 Lam Research Corporation Methods and apparatuses for improving photoresist selectivity and reducing etch rate loading
JPH10189998A (ja) * 1996-12-20 1998-07-21 Sony Corp 表示用薄膜半導体装置及びその製造方法
JP4356117B2 (ja) * 1997-01-29 2009-11-04 財団法人国際科学振興財団 プラズマ装置
JPH10229197A (ja) 1997-02-17 1998-08-25 Sanyo Electric Co Ltd 薄膜トランジスタ、薄膜トランジスタの製造方法
JPH10233511A (ja) * 1997-02-21 1998-09-02 Toshiba Corp 薄膜トランジスタ装置及び薄膜トランジスタ装置の製造方法並びに液晶表示装置
JPH10240164A (ja) 1997-03-03 1998-09-11 Toshiba Corp 駆動回路一体型表示装置
JP4187819B2 (ja) 1997-03-14 2008-11-26 シャープ株式会社 薄膜装置の製造方法
JPH10268254A (ja) 1997-03-26 1998-10-09 Seiko Epson Corp 液晶表示装置
TW376547B (en) 1997-03-27 1999-12-11 Matsushita Electric Ind Co Ltd Method and apparatus for plasma processing
JP3019021B2 (ja) * 1997-03-31 2000-03-13 日本電気株式会社 半導体装置及びその製造方法
JP2937255B2 (ja) 1997-05-02 1999-08-23 日本電気株式会社 透明導電膜のパターニング方法
JPH10326772A (ja) 1997-05-26 1998-12-08 Ricoh Co Ltd ドライエッチング装置
JPH1117185A (ja) 1997-06-20 1999-01-22 Hitachi Ltd 液晶表示装置及びその製造方法
KR100445060B1 (ko) * 1997-06-30 2004-11-16 주식회사 하이닉스반도체 반도체장치의금속배선형성방법
JP4167328B2 (ja) 1997-08-04 2008-10-15 東芝松下ディスプレイテクノロジー株式会社 薄膜のドライエッチング方法および薄膜半導体装置の製造方法
TW374853B (en) * 1997-08-04 1999-11-21 Toshiba Corp Dry etching method of thin film and method for manufacturing thin film semiconductor device
JP3374717B2 (ja) 1997-09-11 2003-02-10 セイコーエプソン株式会社 液晶表示パネルの製造方法
US6680223B1 (en) 1997-09-23 2004-01-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
TW381187B (en) * 1997-09-25 2000-02-01 Toshiba Corp Substrate with conductive films and manufacturing method thereof
JPH11111634A (ja) 1997-10-02 1999-04-23 Ishikawajima Harima Heavy Ind Co Ltd N型半導体膜の形成方法
US6541164B1 (en) * 1997-10-22 2003-04-01 Applied Materials, Inc. Method for etching an anti-reflective coating
JPH11176805A (ja) 1997-11-14 1999-07-02 Siemens Ag 半導体装置の製造方法
US6433841B1 (en) 1997-12-19 2002-08-13 Seiko Epson Corporation Electro-optical apparatus having faces holding electro-optical material in between flattened by using concave recess, manufacturing method thereof, and electronic device using same
US6323132B1 (en) * 1998-01-13 2001-11-27 Applied Materials, Inc. Etching methods for anisotropic platinum profile
TWI226470B (en) 1998-01-19 2005-01-11 Hitachi Ltd LCD device
TW556013B (en) 1998-01-30 2003-10-01 Seiko Epson Corp Electro-optical apparatus, method of producing the same and electronic apparatus
JP3262059B2 (ja) * 1998-02-12 2002-03-04 日本電気株式会社 半導体装置の製造方法
US5917199A (en) 1998-05-15 1999-06-29 Ois Optical Imaging Systems, Inc. Solid state imager including TFTS with variably doped contact layer system for reducing TFT leakage current and increasing mobility and method of making same
US6362027B1 (en) * 1998-07-08 2002-03-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, active matrix substrate, method of manufacturing the semiconductor device and method of manufacturing the active matrix substrate
US6246524B1 (en) * 1998-07-13 2001-06-12 Semiconductor Energy Laboratory Co., Ltd. Beam homogenizer, laser irradiation apparatus, laser irradiation method, and method of manufacturing semiconductor device
JP3883706B2 (ja) * 1998-07-31 2007-02-21 シャープ株式会社 エッチング方法、及び薄膜トランジスタマトリックス基板の製造方法
US6209106B1 (en) * 1998-09-30 2001-03-27 International Business Machines Corporation Method and apparatus for synchronizing selected logical partitions of a partitioned information handling system to an external time reference
US6909114B1 (en) * 1998-11-17 2005-06-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having LDD regions
US6365917B1 (en) 1998-11-25 2002-04-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP4230029B2 (ja) * 1998-12-02 2009-02-25 東京エレクトロン株式会社 プラズマ処理装置およびエッチング方法
US6556702B1 (en) 1999-01-06 2003-04-29 Applied Materials, Inc. Method and apparatus that determines charged particle beam shape codes
US6259106B1 (en) * 1999-01-06 2001-07-10 Etec Systems, Inc. Apparatus and method for controlling a beam shape
US6261406B1 (en) * 1999-01-11 2001-07-17 Lsi Logic Corporation Confinement device for use in dry etching of substrate surface and method of dry etching a wafer surface
US6475836B1 (en) * 1999-03-29 2002-11-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US6284637B1 (en) * 1999-03-29 2001-09-04 Chartered Semiconductor Manufacturing Ltd. Method to fabricate a floating gate with a sloping sidewall for a flash memory
EP1049167A3 (en) 1999-04-30 2007-10-24 Sel Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
GB9912724D0 (en) 1999-06-01 1999-08-04 Cambridge Positioning Sys Ltd Radio positioning system
EP2500941A3 (en) 1999-06-02 2017-05-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US6431112B1 (en) * 1999-06-15 2002-08-13 Tokyo Electron Limited Apparatus and method for plasma processing of a substrate utilizing an electrostatic chuck
TW480554B (en) 1999-07-22 2002-03-21 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
US6541294B1 (en) 1999-07-22 2003-04-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP2001035808A (ja) 1999-07-22 2001-02-09 Semiconductor Energy Lab Co Ltd 配線およびその作製方法、この配線を備えた半導体装置、ドライエッチング方法
JP3538084B2 (ja) 1999-09-17 2004-06-14 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6646287B1 (en) 1999-11-19 2003-11-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device with tapered gate and insulating film
US6825488B2 (en) 2000-01-26 2004-11-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7023021B2 (en) 2000-02-22 2006-04-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
JP4700160B2 (ja) * 2000-03-13 2011-06-15 株式会社半導体エネルギー研究所 半導体装置
TW513753B (en) * 2000-03-27 2002-12-11 Semiconductor Energy Lab Semiconductor display device and manufacturing method thereof
JP2001283990A (ja) * 2000-03-29 2001-10-12 Sumitomo Wiring Syst Ltd ノイズ除去部材及び導電性線材とノイズ除去部材との取付構造
US7525165B2 (en) 2000-04-17 2009-04-28 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and manufacturing method thereof
JP4588167B2 (ja) 2000-05-12 2010-11-24 株式会社半導体エネルギー研究所 半導体装置の作製方法
US6746901B2 (en) 2000-05-12 2004-06-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating thereof
TWI286338B (en) 2000-05-12 2007-09-01 Semiconductor Energy Lab Semiconductor device and manufacturing method thereof
TW480576B (en) 2000-05-12 2002-03-21 Semiconductor Energy Lab Semiconductor device and method for manufacturing same
US6872604B2 (en) * 2000-06-05 2005-03-29 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a light emitting device
TW501282B (en) 2000-06-07 2002-09-01 Semiconductor Energy Lab Method of manufacturing semiconductor device
JP2003045874A (ja) * 2001-07-27 2003-02-14 Semiconductor Energy Lab Co Ltd 金属配線およびその作製方法、並びに金属配線基板およびその作製方法
US6623280B2 (en) * 2001-11-13 2003-09-23 International Business Machines Corporation Dual compliant pin interconnect system
US6652318B1 (en) * 2002-05-24 2003-11-25 Fci Americas Technology, Inc. Cross-talk canceling technique for high speed electrical connectors

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5302240A (en) * 1991-01-22 1994-04-12 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
US5185058A (en) * 1991-01-29 1993-02-09 Micron Technology, Inc. Process for etching semiconductor devices
US5880035A (en) * 1992-06-29 1999-03-09 Sony Corporation Dry etching method
US5580385A (en) * 1994-06-30 1996-12-03 Texas Instruments, Incorporated Structure and method for incorporating an inductively coupled plasma source in a plasma processing chamber
US5779926A (en) * 1994-09-16 1998-07-14 Applied Materials, Inc. Plasma process for etching multicomponent alloys
CN1221809A (zh) * 1997-11-14 1999-07-07 西门子公司 Al基金属层的刻蚀方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
JP平1-207973A 1989.08.21
JP特开平10-233511A 1998.09.02
同上.

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JP2001035808A (ja) 2001-02-09
KR100727274B1 (ko) 2007-06-13
EP1071124A2 (en) 2001-01-24
CN1881537A (zh) 2006-12-20
EP1071124A3 (en) 2001-10-24
TW523833B (en) 2003-03-11
US20050266593A1 (en) 2005-12-01
CN1567078B (zh) 2013-03-27
KR100670577B1 (ko) 2007-01-19

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