CN1868068A - 完全耗尽型绝缘衬底硅cmos逻辑 - Google Patents

完全耗尽型绝缘衬底硅cmos逻辑 Download PDF

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CN1868068A
CN1868068A CNA2004800296753A CN200480029675A CN1868068A CN 1868068 A CN1868068 A CN 1868068A CN A2004800296753 A CNA2004800296753 A CN A2004800296753A CN 200480029675 A CN200480029675 A CN 200480029675A CN 1868068 A CN1868068 A CN 1868068A
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L·福布斯
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Micron Technology Inc
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Abstract

在绝缘衬底硅CMOS存储器装置中使用提取器植入区。该提取器区域被反向偏压以便从部分耗尽的存储器单元的体区中去除少数载流子。这使得该体区被完全耗尽而没有不利的浮体效应。

Description

完全耗尽型绝缘衬底硅CMOS逻辑
技术领域
本发明一般涉及绝缘衬底硅(silicon-on-insulator)器件，尤其涉及完全耗尽型绝缘衬底硅逻辑。
背景技术
计算机和其它电子装置的速度和性能提升要求构成装置的集成电路有更佳性能。使得集成电路更快的一种方法是减少构成该器件的晶体管的大小。但是，随着晶体管变得更小且更快，经过晶体管之间的连接的延迟相对于晶体管速度变得更大。
加速集成电路的替换技术是使用替代半导体。例如，绝缘衬底硅(SOI)技术提供优于等效CMOS技术的25-35％的性能提升。SOI表示在诸如氧化硅或玻璃的绝缘体顶上设置硅薄层。然后，将晶体管构建于该SOI薄层上。SOI层减小了晶体管的电容，使得它们更快地运行。
图1示出了典型的SOI半导体。晶体管形成于绝缘体102上的硅层101中。绝缘体形成于基片103顶上。在硅层101内，形成了漏极/源极区105和106。栅极107形成于部分耗尽的沟道109上。浮体110在耗尽区112内并且是由部分耗尽而形成的。
然而，SOI技术形成了重要的技术挑战。用于SOI晶体管的硅膜必须是理想的结晶硅。但是，绝缘体层不是结晶的。很难形成理想的氧化物上的结晶硅或者具有其它绝缘体的硅，因为绝缘体层的结晶属性与纯硅大不相同。如果未获得理想的结晶硅，则缺陷将会乘机进入SOI膜。这会劣化晶体管性能。
此外，如果p型体与植入区相接触，将出现该体区的很高的电阻，特别是在晶体管较宽的情况下。碰撞电离会引起较大的电流通过该电阻并使该体正向偏压，从而导致瞬变。
这种浮体效应的一种替换是完全耗尽的蓝宝石衬底硅(SOS)半导体。这种类型的半导体没有部分耗尽的硅层或浮体。但是，它们仍存在问题，其中漏电流不保持恒定因为当晶体管处于操作饱和区时漏极电压增加。相反，电流“弯曲”达到较高的值。明显地，浮体上或源极附近载流子的聚集是不期望的。
出于以上原因并由于以下阐述的其它理由，这些理由是本领域熟练技术人员通过阅读和理解本说明书后显而易见的，本领域需要一种方法来控制使用SOI技术的部分耗尽型CMOS器件中不利的浮体效应。
发明内容
不利的浮体效应引起的上述问题和其它问题为本发明所涉及并将通过阅读和学习以下说明书加以理解。
本发明包含一种方法，用于在绝缘衬底硅器件中生成完全耗尽的体结构。该方法提供了与体结构耦合的提取器接触件(extractor contact)。提供提取器电压以使该提取器接触件被反向偏压并去除该体结构中的少数载流子。
本发明的另一些实施例包括改变范围的方法和装置。
附图说明
图1示出了典型的绝缘衬底硅晶体管的剖视图。
图2示出了本发明的绝缘衬底硅晶体管的一个实施例的俯视图。
图3示出了使用本发明的反向偏压提取器接触件方法的一个实施例的完全耗尽型绝缘衬底硅倒相器的剖视图。
图4示出了使用本发明的一个方法实施例来完全耗尽绝缘衬底硅晶体管的NROM闪存单元的剖视图。
图5示出了图4的NROM闪存单元的俯视图。
图6示出了典型的现有技术的部分耗尽型NROM闪存单元的剖视图。
图7示出了使用本发明的提取器接触件反向偏压方法的一个实施例的完全耗尽型NROM闪存单元的剖视图。
图8示出了使用本发明的提取器接触件反向偏压方法的一个实施例的完全耗尽型垂直NROM闪存单元的剖视图。
图9示出了根据本发明的完全耗尽型绝缘衬底硅晶体管的电子系统。
具体实施方式
在本发明的以下详细描述中，参考作为说明书一部分的附图，其中通过说明示出可以实施本发明的特殊实施例。附图中，相同标号贯穿若干附图描述了基本相似的组件。充分详细地描述这些实施例以使本领域的熟练技术人员能实施本发明。可以使用其它实施例，且可以进行结构、逻辑和电气变化而不背离本发明的范围。因此，以下详细描述不被认为是限制性的，且本发明的范围仅由所附权利要求书及其等效物限定。
图2示出了本发明的绝缘衬底硅(SOI)NMOS晶体管的一个实施例的俯视图。本发明使用体接触件的反向偏压，该体接触件也被称作提取器，来提供完全耗尽型晶体管。提取器从部分耗尽的MOS器件的体区中去除少数载流子。这消除了其中由于当器件在饱和模式中运行时漏极电压增加引起的漏极电流不保持恒定的效应。
图2所示的SOI晶体管由两个漏极/源极区201和202构成。在一个实施例中，这些区域是硅层中形成的n+阱。这些区域201和202的宽度表示为W。在一个实施例中，宽度是1微米或以下。替换实施例可使用其它宽度。在另一实施例中，可以通过并联晶体管来实现1微米以上宽度的晶体管。
p+区提取器接触件205形成于硅层内基本上邻近于两个漏极/源极区201和202。在诸如PMOS器件的可选实施例中，提取器接触件205将在n+硅区域上实现。栅极207形成于漏极/源极区201和202之上并在它们之间。
图3示出了使用本发明的反向偏压的提取器的SOI倒相器的一个实施例的剖视图。该倒相器由两个晶体管构成，NMOS器件320和PMOS器件321。每个晶体管320和321都有相关联的提取器接触件310和311。每个提取器310和311都耦合到每个晶体管的体结构301和302。NMOS体结构301由p-型硅构成而PMOS体结构302由n-型硅构成。
每个晶体管320和321分别具有相关联的控制栅极307和308。控制栅极307位于漏极/源极区(未示出)之上。还示出了绝缘体305和基片306。
提取器310和311相对于基片电压被反向偏压。为了将PMOS晶体管321的提取器302反向偏压，施加大于漏极电压VDD的电压。通过施加小于接地电位的电压来将NMOS晶体管的提取器301反向偏压。
在一个实施例中，高于VDD和低于接地的对提取器节点偏压所需的附加电压可以通过本领域公知的电荷泵电路生成。未示出这些泵。
本发明的提取器反向偏压将部分耗尽SOI结构变成没有浮体区的完全耗尽的结构。电荷由浮体生成或者靠近源极。将通过扩散电流去除漏电流或碰撞电离生成的任何过剩电荷，而不是沿着高电阻p型体区的漂移电流。
基于电子陷入的闪存是公知的并且是通常使用的电子组件。更小的单元大小对于低比特成本和高密度闪存来说总是较重要的问题之一。常规的平面NOR闪存单元需要大量接触件。NAND闪存是在较长比特序列的末端处具有接触件的一系列装置。这导致很大的比特密度。
氮化物只读存储器(NROM)闪存装置采用氮化硅层中的电荷陷入。NROM装置可以用CMOS工艺实现。
SOI当前已用于NROM闪存单元。图4示出了将本发明的一个方法实施例用于完全耗尽型绝缘衬底硅晶体管的NROM闪存单元的剖视图。图4的NROM闪存单元是具有虚假接地比特线的NOR阵列单元。
NROM闪存单元由绝缘体411上的SOI层410构成。在该实施例中，比特线401和402是n型区域。当反向偏压该提取器接触件(图5中示出)时，比特线之间的体区403被完全耗尽。氧化物-氮化物-氧化物(ONO)区域405位于控制栅极406和硅层410之间。
图5示出了图4的NROM闪存单元的俯视图。该示图示出了比特线401和402以及控制栅极406。提取器接触件501和502是耗尽体403上的p型区域。
采用部分耗尽的NROM闪存单元的一个问题在于浮体在擦除操作期间引起问题。当负擦除电位施加于NROM装置中的控制栅极时，部分耗尽体终止许多电场线，如图6的剖视图所示。在这种情况下，体电位负浮动，使得尝试擦除存储在ONO复合栅极绝缘体605中的电荷603的电场601变得更小并使擦除速度更慢。
本发明的提取器反向偏压法可应用于NROM闪存单元，以提升擦除速度。此外，擦除速度将不会由于如部分耗尽器件中出现的浮体效应而随时间漂移和改变。
图7示出了使用用于完全耗尽绝缘衬底硅晶体管的本发明的一个方法实施例的NROM闪存单元的剖视图。ONO层705中存储的电荷703由电场701擦除而不存在擦除速度的漂移。完全耗尽体710不像部分耗尽器件中那样存在对电场701的负效应。
虽然图4-7的实施例示出了NROM闪存单元，但可选实施例可以使用S01上的常规闪存单元。如果存在浮体，则负控制栅极电位通过浮动栅极耦合到浮体。随后，浮体变为负电位。这减小了用于负控制栅极到源极擦除的电场，因此减慢了擦除操作。本发明的完全耗尽的SOI晶体管体消除了该效应。
图8示出了垂直NROM 301，它可以使用本发明的反向偏压的提取器来制造完全耗尽体结构。如图8所示，垂直NROM801包括从基片800向外延伸的垂直金属氧化物半导体场效应晶体管(MOSFET)801。MOSFET801具有第一源极/漏极区802，它在该n沟道实施例中包括与n型掺杂层分层的高掺杂的(n+)n型区域。MOSFET 801包括类似结构的第二源极/漏极区806。
沟道区805分别位于第一和第二源极/漏极区802和806之间的垂直柱中。如图8的实施例所示，在与沟道区805相对地位于垂直柱旁边的同时，栅极809通过栅极绝缘体807与沟道区805分开。
在图8所示的实施例中，栅极绝缘体807包括由氧化物-氮化物-氧化物(ONO)组合物807构成的栅极绝缘体。在以下讨论的可选实施例中，栅极绝缘体807包括选自通过湿氧化形成的二氧化硅(SiO2)、氮氧化硅(SON)、富含硅的氧化物(SRO)和富含硅的氧化铝(Al2O3)的栅极绝缘体。在一个实施例中，栅极绝缘体807具有约10纳米(nm)的厚度。
在其它实施例中，栅极绝缘体807包括选自富含硅的氧化铝绝缘体、包含硅纳米颗粒的富含硅的氧化物、包含碳化硅纳米颗粒的氧化硅绝缘体和碳氧化硅绝缘体的栅极绝缘体807。在又一实施例中，栅极绝缘体807包括选自氧化物-氧化铝(Al2O3)-氧化物复合层、氧化物-碳氧化硅-氧化物复合层和氧化物-氮化物-氧化铝复合层的复合层。
氧化铝顶层具有较高的介电常数，使得该层可较厚，以阻止到控制栅极和从控制栅极到氮化物存储层的隧穿。可选实施例使用其它高介电常数绝缘体作为顶层。
在其它实施例中，栅极绝缘体807包括包含复合层或者选自硅(Si)、钛(Ti)和钽(Ta)的两种或多种材料的非化学计量单层的栅极绝缘体807。
图9示出了与处理器910耦合并结合了本发明的SOI存储器单元的一个实施例的存储器装置900的功能框图。处理器910可以是微处理器、处理器或某些其它类型的控制电路系统。存储器装置900和处理器910形成电子系统920的一部分。
存储器装置包括SOI结构的存储器单元930的阵列，如以上各实施例中所描述的。在一个实施例中，存储器单元是非易失性浮动栅极存储器单元且存储器阵列930排列于行和列的存储体中。
提供地址缓冲电路940以锁存地址输入连接A0-Ax942上提供的地址信号。地址信号由行解码器944和列解码器946接收并解码，以访问存储器阵列930。得益于该描述，本领域的熟练技术人员可以理解：地址输入连接的数量取决于存储器阵列930的密度和架构。这样，地址数量随存储器单元计数和存储体和块计数的增加而增加。
存储器装置900通过利用检测/锁存电路950系统检测存储器阵列列中的电压或电流变化来读取存储器阵列930中的数据。在一个实施例中，检测/锁存电路系统耦合为从存储器阵列930中读取并锁存一行数据。包含数据输入和输出缓冲电路系统960用于多个数据连接件962上与控制器910的双向数据通信。提供写电路系统955以将数据写到存储器阵列。
控制电路系统970解码控制连接件972上提供的来自处理器910的信号。这些信号被用于控制存储器阵列930上的操作，包括数据读、数据写和擦除操作。控制电路系统970可以是状态机、序列发生器或某些其它类型的控制器。
图9所示的闪存装置已被简化以帮助存储器特点的基本理解。闪存的内部电路系统和功能的更详细理解是本领域熟练技术人员已知的。
结论
总之，使用SOI技术的部分耗尽CMOS器件中的浮体效应是许多逻辑和存储器应用中不期望的。在静态CMOS逻辑和SRAM存储器中，浮体造成阈值电压和切换速度可变以及特殊逻辑门的切换历史的复杂功能。在动态逻辑DRAM存储器中，浮体引起剩余电荷泄漏和短保留时间，这会导致数据损失。常规闪存和NROM存储器经受由于浮体引起的减少的擦除电场并较慢的擦除时间。导致完全耗尽体结构的本发明的反向偏压提取器的使用基本上减小或消除了这些不期望的效应。
尽管这里已说明并描述了特殊实施例，本领域的普通技术人员可以理解，被计算用于实现相同目的的任何结构都可替换所示的特殊实施例。本发明的许多适应将是本领域普通技术人员显而易见的。因此，本申请旨在覆盖本发明的任何适应或变型。

Claims (21)

1.一种用于在具有基片的绝缘衬底硅器件中生成完全耗尽体结构的方法，该方法包括：
提供与所述体结构耦合的提取器接触件；以及
提供一提取器电压，使得所述提取器接触件被反向偏压且所述体结构中的少数载流子被去除。
2.如权利要求1所述的方法，其特征在于，所述基片处于接地电位。
3.如权利要求1所述的方法，其特征在于，所述提取器接触件耦合到所述绝缘体上的p型硅。
4.如权利要求1所述的方法，其特征在于，所述提取器接触件耦合到所述绝缘体上的n型硅。
5.如权利要求1所述的方法，其特征在于，所述绝缘衬底硅器件具有漏极区且所述方法还包括将漏极电压施加于所述漏极区。
6.如权利要求5所述的方法，其特征在于，所述提取器电压大于所述漏极电压。
7.如权利要求2所述的方法，其特征在于，所述提取器电压小于所述基片电位。
8.一种用于在具有基片、控制栅极、漏极区和源极区的PMOS绝缘衬底硅器件中生成完全耗尽体结构的方法，所述方法包括：
将提取器电压施加于与所述体结构耦合的提取器接触件；以及
将基片电压施加于所述基片，以使所述提取器电压大于所述基片电压。
10.如权利要求8所述的方法，其特征在于，所述提取器接触件耦合到基片上的n型硅。
11.如权利要求8所述的方法，其特征在于，还包括将正电压施加于控制栅极以擦除所述器件中存储的电荷。
12.一种用于在具有基片、控制栅极、漏极区和源极区的NMOS绝缘衬底硅器件中生成完全耗尽体结构的方法，该方法包括：
将提取器电压施加到与所述体结构耦合的提取器接触件上；以及
将基片电压施加到所述基片上，使得所述提取器电压小于所述基片电压。
13.如权利要求12所述的方法，其特征在于，所述提取器接触件耦合到所述基片上的p型硅。
14.如权利要求12所述的方法，其特征在于，还包括将负电压施加于所述控制栅极上，以擦除所述器件中存储的电荷。
15.一种用于在使用绝缘衬底硅结构的NROM闪存器件中生成完全耗尽体区的方法，所述器件具有基片、控制栅极、漏极区和源极区，所述方法包括：
将提取器电压施加于与所述体结构耦合的提取器接触件；以及
将基片电压施加于所述基片上，使得所述提取器电压小于所述基片电压。
16.如权利要求15所述的方法，其特征在于，所述提取器接触件由p型硅构成。
17.一种在基片上具有绝缘衬底硅结构的晶体管，所述晶体管
漏极区，它包括第一掺杂材料并形成于绝缘衬底硅中；
源极区，它包括第一掺杂材料并形成于绝缘衬底硅中；
控制栅极，它形成于所述漏极和源极区上并基本位于它们之间；以及
提取器接触件，它包括第二掺杂材料并耦合到基本在所述漏极和源极区之间的耗尽区，所述耗尽区响应于提取器接触件的反向偏压被完全耗尽。
18.如权利要求17所述的晶体管，其特征在于，所述第一掺杂材料由n型硅构成，且所述第二掺杂材料由p型硅构成。
19.如权利要求17所述的晶体管，其特征在于，所述第一掺杂材料由p型硅构成，且所述第二掺杂材料由n型硅构成。
20.一种具有基片上的绝缘衬底硅结构的垂直多比特存储器单元，所述存储器单元包括：
从基片向外水平延伸的垂直金属氧化物半导体场效应晶体管(MOSFET)，所述MOSFET具有第一源极/漏极区，第二源极/漏极区，所述第一和第二源极/漏极区之间的沟道区，以及与通过高介电常数栅极绝缘体与沟道区分开的栅极，它可以将第一电荷存入第一存储区并将第二电荷存入第二存储区；
第一传输线，它耦合到所述第一源极/漏极区；
第二传输线，它耦合到所述第二源极/漏极区；以及
提取器接触件，它耦合到所述沟道区以使所述提取器接触件上的反向偏压完全耗尽所述沟道区。
21.一种电子系统，包括：
处理器；以及
与所述处理器耦合的存储器装置，其中所述存储器装置包括具有含绝缘衬底硅结构的多个存储器单元的存储器阵列，每个存储器单元都包括：
漏极区，它包括第一掺杂材料并形成于绝缘衬底硅中；
源极区，它包括第一掺杂材料并形成于绝缘衬底硅中；
控制栅极，它形成于所述漏极和源极区上并基本位于它们之间；以及
提取器接触件，它包括第二掺杂材料并耦合到基本在所述漏极和源极区之间的耗尽区，所述耗尽区响应于提取器接触件的反向偏压被完全耗尽。
22.如权利要求21所述的电子系统，其特征在于，所述存储器单元是垂直存储器单元。
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CN102592669B (zh) * 2011-01-13 2017-08-08 株式会社半导体能源研究所 半导体装置及半导体存储装置

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US20110204431A1 (en) 2011-08-25
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