CN1860602A - 高性能应变互补金属氧化物半导体器件 - Google Patents

高性能应变互补金属氧化物半导体器件 Download PDF

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CN1860602A
CN1860602A CNA2004800284756A CN200480028475A CN1860602A CN 1860602 A CN1860602 A CN 1860602A CN A2004800284756 A CNA2004800284756 A CN A2004800284756A CN 200480028475 A CN200480028475 A CN 200480028475A CN 1860602 A CN1860602 A CN 1860602A
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CN100530589C (zh
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布鲁斯·B·多丽斯
奥利格·G·格卢申科夫
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GlobalFoundries Inc
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Abstract

本发明涉及一种半导体器件和制造方法，该半导体器件和制造方法提供具有带突悬的浅槽隔离的n沟道场效应晶体管(nFET)，该突悬在与电流方向平行的方向上及在与电流横贯的方向上突悬在Si－SiO2界面上。所述器件和方法还提供具有带突悬的浅槽隔离的p沟道场效应晶体管(pFET)，该突悬在与电流横贯的方向上突悬在Si－SiO2界面上。但是，用于该pFET的所述浅槽隔离在与电流方向平行的方向上没有突悬。

Description

高性能应变互补金属氧化物半导体器件
技术领域
本发明总地涉及半导体器件及其制造方法，更特别地，涉及一种互补金属氧化物半导体(CMOS)器件，其包括浅槽隔离(STI)突悬界面从而防止器件中氧化引起的压缩应力。
背景技术
CMOS器件可利用各种工艺技术制造。一种方法需要在松弛的(relaxed)硅锗(SiGe)层上制造应变硅(Si)层。随着锗(Ge)浓度增大，Si晶格中的应变增大。这主要因为这样的应变影响性能(例如电子和空穴迁移率)。虽然应变可改善n沟道场效应晶体管(nFET)中的电子迁移率，但是p沟道场效应晶体管(pFET)中的性能改善(即空穴迁移率的提高)成为更大的挑战。在小量的拉伸应变的情况下pFET中的空穴迁移率初始表现稍微的下降，但是随着更高的应变而线性增大。
相对于电流沿纵方向施加的压缩应力会导致空穴迁移率的显著增加，但是也会降低电子迁移率。一般在CMOS制造中用来隔离离散的元件(discretecomponent)从而防止干扰的浅槽隔离(STI)工艺易受氧化导致的体积膨胀引起的应力的的影响。该应力能显著影响性能，例如通过减小nFET电子迁移率而负面影响性能。
特别地，与STI的垂直部分相邻地定位的Si易受氧化引起的应力的影响。在栅极氧化或栅级堆叠的再氧化期间Si会变得氧化。由于多次栅极氧化的使用氧化部分会表现出显著增大的厚度，这在制造高性能逻辑电路中是常见的。增大的厚度在硅有源区域中引起应力，其会影响性能，例如通过降低nFET电子迁移率而负面影响性能。
应力源接近晶体管栅极时，这样的氧化引起的压缩应力对性能的影响被放大。现代CMOS芯片具有在公共硅衬底中并列的数百万有源器件。随着小型化和在单个衬底上引入更多有源器件的努力持续下去，这样的应力源足够接近从而显著地影响性能变得更加可能。
本发明专注于克服上述问题中的一个或更多。
发明内容
在本发明的第一方面中，一种半导体结构形成在衬底上，包括具有至少一个突悬(overhang)的至少一个浅槽隔离，所述至少一个突悬被选择性配置来防止该衬底的确定部分中的氧化引起的应力。
在本发明的另一方面中，一种半导体结构形成在衬底上。该结构包括第一场效应晶体管，该第一场效应晶体管具有源极、漏极、栅极、以及从该源极到该漏极的电流方向。该结构还包括用于该第一场效应晶体管的第一浅槽隔离。该第一浅槽隔离具有至少一个突悬，其被配置来防止沿与该第一场效应晶体管的电流方向平行的方向的氧化引起的应力。
在本发明的再一方面中，提供一种形成半导体结构的工艺。该工艺需要形成第一浅槽隔离。该浅槽隔离具有至少一个突悬，其配置来防止氧化引起的沿第一确定方向的应力。在该工艺中，形成一种结构，包括硅层、在该硅层上的二氧化硅层、以及在该二氧化硅层上的硅氮化物层。该硅氮化物层、该二氧化硅层和该硅衬底的一部分被蚀刻从而形成槽。该槽中该硅氮化物层的侧壁部分被蚀刻从而产生该硅氮化物层相对于该槽的凹进。浅槽隔离形成在该槽中，其在实施例中具有突悬。
附图说明
图1示出根据本发明一示例性实施用于使用的具有氧化物和氮化物层的硅衬底；
图2示出根据本发明一示例性实施用于使用的在氮化物表面上具有构图的光致抗蚀剂图像的硅衬底；
图3示出根据本发明一示例性实施用于使用的具有槽的蚀刻的半导体结构；
图4示出根据本发明一示例性实施用于使用的具有浅槽隔离的半导体结构；
图5示出根据本发明一示例性实施用于使用的具有带突悬的浅槽隔离的半导体结构；
图6示出去除氮化物层和减小氧化物厚度之后的具有带突悬的浅槽隔离的半导体结构；
图7示出浅槽隔离围绕的有源器件(例如nFET或pFET)的顶平面图；
图8示出根据本发明一示例性实施例的pFET器件；
图9示出根据本发明一示例性实施例的nFET器件；
图10示出沿与电流横贯的方向具有STI突悬的示例性pFET器件的平行于栅极的视图；以及
图11示出沿与电流横贯的方向具有STI突悬的nFET器件的平行于栅极的视图。
具体实施方式
本发明采用与掩模结合的硅氮化物(Si3N4)拉回(pull-back)工艺，所述掩模用于防止Si3N4拉回沿一些或全部pFET器件的纵向分量执行。所得半导体结构具有对于nFET器件存在于沿电流方向及横贯电流方向的突悬结构(这里称为突悬、SiO2突悬、以及STI突悬)。由于压缩应力，为了增强性能，对于pFET器件没有二氧化硅(SiO2)突悬出现在与电流方向平行的方向上。
然而，对于pFET器件该结构在与电流横贯的方向上具有SiO2突悬从而避免源自压缩应力的性能下降。突悬结构通过阻挡对下面的Si的接近而防止氧化。没有突悬，则在与浅槽隔离相邻的垂直Si-SiO2界面处的Si将易受氧化和伴随的体积膨胀的影响，尤其在栅极氧化和再氧化工艺步骤期间。相信所得半导体结构能够使pFET性能改善而有很小或没有nFET性能下降。另外，利用标准失效分析技术例如扫描电子显微镜(SEM)，突悬结构是可检测的。
参照图1，硅衬底110、衬垫(pad)二氧化硅(SiO2)层120和衬垫硅氮化物(Si3N4)层130被提供。举例来说，硅衬底可以是硅晶片(wafer)、形成在硅晶片上的外延层或者绝缘体上硅(SOI)衬底。二氧化硅层120可为约2nm至70nm厚，且可以沉积或生长在晶片上。例如，二氧化硅层120可以通过热氧化或者通过低压化学气相沉积(LPCVD)形成。接着，在约10至400nm范围内的硅氮化物层130可通过LPCVD沉积。
现在参照图2，然后可进行光刻工艺从而在硅氮化物层130之上构图光致抗蚀剂图像210。然后可利用干或湿蚀刻工艺(例如利用构图的光致抗蚀剂作为掩模通过反应离子蚀刻)蚀刻相反图案(inverse pattern)从而形成槽(trench)结构，如本领域所公知的。
现在参照图3，可实施干或湿蚀刻工艺从而蚀刻未被光致抗蚀剂图像210覆盖的硅氮化物130、二氧化硅120和一些量的硅衬底110。以此方式，穿过层110、120和130形成槽310和320。
接着，参照图4，槽310和320可被填充以SiO2，例如通过利用例如化学气相沉积(CVD)或等离子体CVD工艺在衬底的表面之上沉积SiO2。然后所沉积的SiO2可利用例如反应离子蚀刻(RIE)、化学机械抛光、或者其结合被平坦化。以此方式，浅槽隔离410和420被形成。这些浅槽隔离410和420没有呈现出突悬。
为了形成具有突悬的浅槽隔离，沉积SiO2以填充槽之前，部分硅氮化物层130被蚀刻，使得它们相对于槽的侧壁后退或拉回(pull-back)，如图5所示。硅氮化物层130可例如通过在氧化物沉积和化学机械抛光之前在槽310和320中引入蚀刻剂诸如甘油酸酯缓冲的氢氟酸来被蚀刻(即“被拉回”)。在此步骤中将被蚀刻的硅氮化物的量将取决于全部制造工艺，本发明的教导结合到该全部制造工艺中。通常，该量应足以能够形成突悬，该突悬足以防止器件的确定部分中的氧化。然而，突悬不应干扰器件上的其它结构。以示例而不是限制的方式，延伸超过STI-衬底界面0.01μm至0.5μm(微米)的突悬应足以防止氧化而不导致干扰。
为了控制形成突悬的位置，光致抗蚀剂或硬掩模可被选择性应用从而防止蚀刻剂(例如甘油酸酯缓冲的氢氟酸)底切确定区域。被光致抗蚀剂或硬掩模保护的区域将不表现出突悬的形成所需的拉回。用于沉积和构图硬掩模或光致抗蚀剂的工艺在半导体制造领域是公知的。然后硬掩模或光致抗蚀剂在随后的处理步骤中可被去除。
然后，通过SiO2的沉积和平坦化，例如RIE或化学机械抛光，结构510和520被形成，如图5所示。槽形成和拉回之后来自氧化物层120的部分SiO2 122-128(图6)可保留。由于这些部分122-128由与T形结构510和520相同的材料构成，所以在后面的图中该部分与T形结构未区别开。
由于硅氮化物层130从槽的侧壁拉回，所以图5的浅槽隔离结构分别形成T形或阶梯部分510a和520a(例如嵌入在层110和120中的狭窄部分)，从而形成层120之上的突悬。因此，这些浅槽隔离结构510和520的顶水平部分或阶梯部分510a和520a现在分别突悬于垂直Si-SiO2界面620-626之上且因此抑制界面的Si部分的氧化。结果，沟道区域中氧化引起的压缩可被防止。
这样，拉回使得能够形成所沉积的SiO2的突悬，从而保护Si-SiO2界面620-626处的被覆盖的垂直部分Si免于被氧化。氧化引起的应变可被该突悬抑制，否则其会降低性能。包括nFET的CMOS电路可具有带突悬的STI结构，该突悬在与电流方向平行的方向上或者在与电流横贯的方向上，从而防止沿Si-SiO2界面的Si氧化。相反，pFET器件可具有沿横向的突悬，但是根据图4在与电流方向平行的方向上没有突悬。
接着，在图6中，硅氮化物层130(图5)通过例如热磷酸被去除。此时，实施传统工艺流程中使用的形成源极和漏极区的阱注入。然后定时氢氟酸蚀刻可用来准备用于栅极氧化的硅表面。氧化物层120、510和520通过这样的蚀刻减小厚度。
虽然已经描述了示例性材料和STI突悬形成以及半导体制造工艺，但是本发明不限于这些方面。另外的和不同的材料和制造步骤，包括不同的蚀刻剂和拉回以及突悬形成技术可被应用而不偏离本发明的范围。
半导体中的每个有源器件可具有包围该器件的浅槽隔离。通常浅槽隔离包括四个侧部。以示例而不是限制的方式，图7提供包围有源器件的浅槽隔离710的顶平面图，该有源器件包括栅极电极720和有源硅区域730。浅槽隔离710包括平行于电流方向的两个侧部740和750以及与电流方向横贯的两个侧部760和770。此外，侧部可具有STI突悬或可以没有突悬。平行于电流方向的侧部740和/或750上的突悬是平行于电流方向的突悬。与电流方向横贯的侧部760和/或770上的突悬是与电流方向横贯的突悬。
现在参照图8，示例性pFET器件被示出。该示例性器件包括浅槽隔离带侧部410和420的，侧部410和420没有在与电流方向平行的的方向上的突悬。对于pFET，STI突悬可设置在横向。该有源器件可包括全部以传统方式形成的传统栅极电介质845、栅极电极830以及侧壁间隔物820和835。也可设置用于源极和漏极接触的硅化物(例如TiSi2、TaSi2或MoSi2)810和840。
现在参照图9，示例性nFET器件被示出。该器件包括带侧部510和520的浅槽隔离，侧部510和520具有在与电流方向平行的方向上的突悬。该有源器件可包括传统栅极电介质945、栅极电极930以及侧壁间隔物920和940。也可设置用于源极和漏极接触的硅化物(例如TiSi2、TaSi2或MoSi2)910和950。突悬防止垂直Si-SiO2界面附近氧化引起的鸟喙部的形成。因此，将降低nFET的电子迁移率的氧化引起的压缩应力被避免。
现在参照图10，根据本发明一示例性实施例的pFET器件的平行于栅极930的剖视图示出沿与电流横贯的方向的STI突悬1010和1020。STI突悬1010和1020防止沿横向形成氧化引起的压缩应力(例如形成鸟喙部)，从而防止空穴迁移率的下降。沿横向的STI突悬可利用如用来形成在平行于电流方向的方向上的STI突悬的技术来形成(例如硅氮化物拉回工艺)。
类似地，图11提供示例性nFET器件的平行于栅极830的剖视图，其示出沿与电流横贯的方向的STI突悬1110和1120。STI突悬1110和1120防止沿横向的氧化引起的压缩应力形成，从而防止电子迁移率的下降。此外，沿横向的STI突悬可利用与用来形成在平行于电流方向的方向上的STI突悬的技术相同的技术形成(例如硅氮化物拉回工艺)。
应力效应反相关于与有源器件的距离。氧化引起的压缩应力源越接近于有源器件，则对性能的影响越大。相反，场效应晶体管栅极与氧化引起的压缩应力源(例如鸟喙部形成)之间的距离越大，则对性能的影响越不明显。此外，与确定有源结构(例如晶体管栅极的最近的边缘)超过确定距离的氧化引起的压缩应力源(例如鸟喙部形成)不会明显影响该结构的性能(例如电子或空穴迁移率)。因此，在本发明的一个实施例中，如果STI与确定结构之间的距离小于或等于所述确定距离，则STI突悬可被实施。所述确定距离可根据会影响所引起的应力的大小的因素而变化。举例来说，这样的因素可包括：隔离、电介质和硅衬底之间的热失配(thermal mismatch)；氮化物掩模的本征应力；以及制造步骤和条件。因为超过该距离的应力源不会对性能有明显影响，所以在这样的情况下STI突悬的形成不能保证用于应力减小目的。以示例而不是限制的方式，距nFET或pFET的最近的边缘5.0μm(微米)或更大的距离可以足以避免性能降低。
因此依照示例性实施的STI突悬结构可被选择性配置来防止鸟喙部形成，其中这样的形成导致的压缩应力将降低性能。诸如器件类型(例如nFET或pFET)、距有源器件的距离、以及电流方向的考虑会影响突悬是否将形成以及突悬的布置。虽然对于nFET来说STI突悬可设置在与电流方向平行和横贯的两个方向，但是pFET可具有沿横向的STI突悬，而在实施例中不应具有沿平行方向的突悬。选择性配置还可考虑STI与有源器件之间的距离(例如STI与附近的栅极之间的距离)。如果该距离防止与STI相邻的鸟喙部形成对性能有任何明显影响，那么突悬可被省略。
尽管根据示例性实施例描述了本发明，但是本领域技术人员将意识到，可在所附权利要求的思想和范围内通过修改实践本发明。

Claims (22)

1.一种形成在衬底上的半导体结构，包括具有至少一个突悬的浅槽隔离，所述突悬被选择性配置来防止所述衬底的确定部分中氧化引起的应力。
2.如权利要求1所述的半导体结构，还包括：
器件，其具有带电流方向的源极和漏极，
其中所述至少一个突悬中的一个被选择性配置来防止氧化引起的在与所述电流方向平行的方向上的应力。
3.如权利要求1所述的半导体结构，还包括：
器件，其具有带电流方向的源极和漏极，
其中所述至少一个突悬中的一个被选择性配置来防止氧化引起的在横贯所述电流方向的方向上的应力。
4.如权利要求1所述的半导体结构，其中：
所述衬底的所述确定部分是与所述浅槽隔离相邻的Si-SiO2界面；且
所述至少一个突悬延伸超过所述Si-SiO2界面，防止在所述Si-SiO2界面或其附近的氧化。
5.如权利要求1所述的半导体结构，还包括：
第一器件，其具有源极和漏极，该源极和漏极具有用于该第一器件的电流方向；以及
第二器件，其具有源极和漏极，该源极和漏极具有用于该第二器件的电流方向；
其中该浅槽隔离包括
用于所述第一器件的第一浅槽隔离侧部，其具有至少一个突悬，所述至少一个突悬被配置来防止氧化引起的在与所述第一器件的所述电流方向平行的方向上的应力；以及
用于所述第一器件的第二浅槽隔离侧部，其具有至少一个突悬，所述至少一个突悬被配置来防止氧化引起的在与所述第一器件的所述电流方向横贯的方向上的应力；以及
用于所述第二器件的第三浅槽隔离侧部，其具有至少一个突悬，所述至少一个突悬被配置来防止氧化引起的在与所述第一器件的所述电流方向横贯的方向上的应力。
6.如权利要求5所述的半导体结构，其中所述浅槽隔离还包括用于所述第二器件的第四浅槽隔离侧部，该第四浅槽隔离没有突悬。
7.一种形成在衬底上的半导体结构，包括：
n沟道场效应晶体管，其具有源极、漏极、栅极、以及从该源极到该漏极的电流方向；以及
用于该n沟道场效应晶体管的第一浅槽隔离，该第一浅槽隔离具有第一浅槽隔离侧部，该第一浅槽隔离侧部具有至少一个突悬，所述至少一个突悬被配置来防止氧化引起的在与所述n沟道场效应晶体管的所述电流方向平行的方向上的应力。
8.如权利要求7所述的半导体结构，其中用于所述n沟道场效应晶体管的所述第一浅槽隔离还包括：
第二浅槽隔离侧部，其横贯所述第一浅槽隔离侧部且具有至少一个突悬，所述至少一个突悬被配置来防止氧化引起的在与所述n沟道场效应晶体管的所述电流方向横贯的方向上的应力。
9.如权利要求8所述的半导体结构，还包括：
p沟道场效应晶体管，该p沟道场效应晶体管具有源极、漏极、栅极、以及从该源极到该漏极的电流方向；
用于该p沟道场效应晶体管的第二浅槽隔离，其具有第三浅槽隔离侧部，所述第三浅槽隔离侧部没有突悬；以及
用于该p沟道场效应晶体管的该第二浅槽隔离还具有第四浅槽隔离侧部，该第四浅槽隔离侧部横贯该第三浅槽隔离侧部且具有至少一个突悬，该至少一个突悬被配置来防止氧化引起的在与该p沟道场效应晶体管的所述电流方向横贯的方向上的应力。
10.如权利要求9所述的半导体结构，其中被配置来防止氧化引起的在横贯该电流方向的方向上的应力的所述突悬防止空穴迁移率的降低。
11.如权利要求9所述的半导体结构，其中：
从所述n沟道场效应晶体管的所述栅极到用于所述n沟道场效应晶体管的所述第一浅槽隔离的所述第一浅槽隔离侧部的距离小于或等于一距离，在该距离内与所述第一浅槽隔离相邻的氧化引起的应力将会影响n沟道场效应晶体管的性能，且
从所述n沟道场效应晶体管的所述栅极到用于所述n沟道场效应晶体管的所述第一浅槽隔离的所述第二浅槽隔离侧部的距离小于或等于一距离，该距离内与所述第二浅槽隔离相邻的氧化引起的应力将会影响所述n沟道场效应晶体管的性能。
12.如权利要求1所述的半导体结构，其中所述突悬包括T形结构。
13.如权利要求12所述的半导体，其中所述衬底的所述确定部分是与所述浅槽隔离相邻的Si-SiO2界面。
14.如权利要求13所述的半导体，其中所述突悬包括延伸超过所述Si-SiO2界面约0.01微米至0.5微米的水平部分。
15.如权利要求9所述的半导体结构，其中从所述p沟道场效应晶体管的所述栅极到用于所述p沟道场效应晶体管的所述第二浅槽隔离的所述第四浅槽隔离侧部的距离小于或等于一距离，该距离内与所述第四浅槽隔离侧部相邻的氧化引起的应力将会影响所述p沟道场效应晶体管的性能。
16.如权利要求15所述的半导体结构，其中从所述p沟道场效应晶体管的所述栅极到所述第四浅槽隔离侧部的距离小于或等于约5.0微米。
17.如权利要求11所述的半导体结构，其中从所述n沟道场效应晶体管的所述栅极到所述第一浅槽隔离侧部的距离小于或等于约5.0微米。
18.如权利要求12所述的半导体结构，其中从所述n沟道场效应晶体管的所述栅极到所述第二浅槽隔离侧部的距离小于或等于约5.0微米。
19.一种形成半导体结构的方法，包括：
形成包括硅层、在该硅层上的二氧化硅层、以及在该二氧化硅层上的硅氮化物层的结构；
在该结构上形成浅槽隔离，该浅槽隔离具有：具有至少一个突悬的第一浅槽隔离侧部，该至少一个突悬被配置来防止氧化引起的沿第一确定方向的应力；以及第二浅槽隔离侧部，该第二浅槽隔离侧部横贯所述第一浅槽隔离侧部且没有突悬。
20.如权利要求19所述的方法，其中所述形成所述浅槽隔离的步骤包括：
蚀刻所述硅氮化物层、所述二氧化硅层以及所述硅层的一部分从而形成槽；
蚀刻所述槽中所述硅氮化物层的侧壁部分来产生所述硅氮化物层相对于所述槽的凹进以用于所述第一浅槽隔离侧部；以及
将二氧化硅沉积到所述槽和凹进中从而形成所述浅槽隔离，所述浅槽隔离具有带突悬的第一浅槽隔离侧部。
21.如权利要求20所述的方法，还包括形成具有源极、漏极、栅极、以及从该源极到该漏极的电流方向的场效应晶体管的步骤。
22.如权利要求21所述的方法，其中从所述场效应晶体管的所述栅极到所述第一浅槽隔离侧部的距离小于或等于一距离，该距离内与所述第一浅槽隔离侧部相邻的氧化引起的应力将会影响所述场效应晶体管的性能。
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US7847358B2 (en) 2010-12-07
WO2005038875A3 (en) 2005-08-25
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US20050082634A1 (en) 2005-04-21
US7119403B2 (en) 2006-10-10
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US20060270136A1 (en) 2006-11-30
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