CN1823416A - 可堆叠的集成电路封装和用于其的方法 - Google Patents

可堆叠的集成电路封装和用于其的方法 Download PDF

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CN1823416A
CN1823416A CNA2004800200074A CN200480020007A CN1823416A CN 1823416 A CN1823416 A CN 1823416A CN A2004800200074 A CNA2004800200074 A CN A2004800200074A CN 200480020007 A CN200480020007 A CN 200480020007A CN 1823416 A CN1823416 A CN 1823416A
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integrated circuit
lead wire
conductive lead
circuit encapsulation
stackable integrated
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赫姆·P·塔奇亚
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SanDisk Corp
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SanDisk Corp
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Abstract

本发明揭示用于堆叠具有引线的集成电路封装的改进的设备和方法。根据一实施例，一集成电路封装的引线被暴露且具有焊料球，使得可电连接堆叠于其上的另一集成电路封装的相应引线。所述堆叠导致相对于一衬底的集成电路密度的增加，然而所述堆叠的集成电路封装仍能够具有一整体较薄或较低的轮廓。

Description

可堆叠的集成电路封装和用于其的方法
技术领域
本发明涉及集成电路封装，且尤其涉及可堆叠的集成电路封装。
背景技术
随着存储器集成电路(IC)封装越来越小和其存储器密度越来越大的趋势，需要封装集成电路的进步。一个最新进步包括在一单IC封装内堆叠多个集成电路晶粒。所述内部封装堆叠包括在一较大晶粒上堆叠一较小晶粒。所述晶粒中的每一个均导线接合到一衬底。此类型的堆叠已(例如)用于相同功能的晶粒(例如，两个闪存晶粒)或不同功能的晶粒(例如，一个闪存晶粒和一个SRAM晶粒)。两个或三个晶粒的堆叠已用于堆叠式芯片级封装(堆叠式CSP)和堆叠式薄型小尺寸封装(TSOP)。
除单个IC封装内的晶粒堆叠外，IC封装自身可为可堆叠的。常规而言，需要专门的连接器或模块来堆叠集成电路封装。然而，不幸地是，专门连接器或模块的成本冲击对所述堆叠技术来说是一个缺点。因此，需要不取决于专门连接器或模块的用于集成电路封装的改进的堆叠技术。
发明内容
本发明涉及用于堆叠具有引线的集成电路封装的改进的设备和方法。根据一实施例，一集成电路封装的引线被暴露且具有焊料球，使得可电连接堆叠于其上的另一集成电路封装的相应引线。所述堆叠导致相对于一衬底的集成电路密度增加，然而所堆叠的集成电路封装仍能够具有一整体较薄或较低的轮廓。
改进的设备和方法尤其适用于堆叠相同大小(且通常相同功能)的集成电路封装。所述集成电路封装用途的一个实例为含有两个或两个以上类似大小的存储器存储集成电路封装的堆叠的非易失性存储器集成电路产品。
本发明可以多种方式实施，包括如一系统、设备、装置或方法。以下论述本发明的若干实施例。
如一可堆叠的集成电路封装，本发明的一实施例至少包括：一引线框，其具有一内部区域和一外部区域，所述外部区域具有复数个导电引线，且所述导电引线的每一个均具有一不可焊区域和一可焊区域；至少一晶粒，其电连接到所述引线框的内部区域；和一包封材料(encapsulant material)，其环绕所述引线框的至少大部分内部区域和至少一晶粒，借此形成可堆叠的集成电路封装，所述引线框外部区域处的导电引线的至少可焊区域被暴露。
如一提供非易失性数据存储的存储器卡，本发明的一实施例至少包括：一具有一顶面和一底面的第一可堆叠的集成电路封装，和一具有一顶面和一底面的第二可堆叠的集成电路封装。所述第二可堆叠的集成电路封装堆叠在所述第一可堆叠的集成电路芯片上。所述第一可堆叠的集成电路封装至少包括：一第一引线框，其具有一内部区域和一外部区域，所述外部区域具有复数个导电引线，且所述导电引线的每一个均具有一不可焊区域和一可焊区域；至少一晶粒，其电连接到所述第一引线框的内部区域；和一包封材料，其环绕所述第一引线框的至少大部分内部区域和至少一晶粒，借此形成第一可堆叠的集成电路封装，所述第一引线框外部区域处的导电引线的至少可焊区域被暴露；和第一焊料球，其提供于每一导电引线的可焊区域上。所述第二可堆叠的集成电路封装至少包括：一第二引线框，其具有一内部区域和一外部区域，所述外部区域具有复数个导电引线，且所述导电引线的每一个均具有一不可焊区域和一可焊区域；至少一晶粒，其电连接到所述第二引线框的内部区域；和一包封材料，其环绕所述引线框的至少大部分内部区域和至少一晶粒，借此形成第二可堆叠的集成电路封装，所述第二引线框外部区域处的导电引线的至少可焊区域被暴露；和第二焊料球，其提供于每一导电引线的可焊区域上。当所述第二可堆叠的集成电路封装堆叠于所述第一可堆叠的集成电路芯片上时，所述第二焊料球将第二可堆叠的集成电路封装的导电引线电连接到第一可堆叠的集成电路封装的导电引线中的相应导电引线。
如一种用于形成一可堆叠的集成电路封装的方法，本发明的一实施例至少包括以下行为：获得一具有复数个导电引线的金属引线框；将一第一晶粒附着到所述金属引线框的一内部区域；使用导电链将第一晶粒电连接到金属引线框的外部区域；包封所述第一晶粒、所述导电链和金属引线框的大部分，使得所述金属引线框外部区域处的导电引线的外围部分不被包封；和将一焊料沉积物附着到所述金属引线框外部区域处的每一导电引线。
如一电子装置，本发明的一实施例至少包括：一印刷电路板、一第一可堆叠的集成电路封装和一第二可堆叠的集成电路封装。所述第一可堆叠的集成电路封装具有第一延伸导电引线，所述第一延伸导电引线的每一个均具有一不可焊区域和一可焊区域，且在每一所述第一延伸导电引线的可焊区域处具有第一焊料沉积物。所述第二可堆叠的集成电路封装具有第二延伸导电引线，所述第二延伸导电引线的每一个均具有一不可焊区域和一可焊区域，且在每一所述第二延伸导电引线的可焊区域处具有第二焊料沉积物。第一可堆叠的集成电路封装安装于印刷电路板上，且所述第一焊料沉积物用于将第一可堆叠的集成电路封装的第一延伸导电引线至少电耦接到所述印刷电路板。第二可堆叠的集成电路封装堆叠于第一可堆叠的集成电路封装上，且所述第二焊料沉积物用于将第二可堆叠的集成电路封装的第二延伸导电引线至少电耦接到所述第一可堆叠的集成电路封装的第一延伸导电引线中的个别第一延伸导电引线。因此，所述第二可堆叠的集成电路封装的第二延伸导电引线经由第一可堆叠的集成电路封装的第一延伸导电引线电耦接(且可能以机械方式耦接)到印刷电路板。
本发明的其它方面和优点将从以下详细描述结合附图而变得显而易见，其以实例方式说明本发明的原理。
附图说明
通过以下详细描述结合附图将不难理解本发明，其中类似参考数字指示类似结构元件，且其中：
图1A为一根据本发明的一实施例的集成电路封装的俯视图。
图1B为一根据本发明的一实施例的图1A中所示的集成电路封装的侧视图。
图2A为一根据本发明的一实施例的集成电路封装的侧视图。
图2B为一图2A中所示的集成电路封装的导电引线中的一个导电引线的分解图。
图3为一根据本发明的一实施例的集成电路封装形成过程的流程图。
图4为一根据本发明的一实施例的集成电路封装的一横截面图。
图5为一根据本发明的另一实施例的集成电路封装的一横截面图。
图6为一根据本发明的一实施例的集成电路封装的组装的、堆叠布置的侧视图。
图7A为一根据本发明的另一实施例的集成电路封装的俯视图。
图7B为一图7A中所说明的集成电路封装的侧视图。
具体实施方式
本发明涉及用于堆叠具有引线的集成电路封装的改进的设备和方法。根据一实施例，一集成电路封装的引线被暴露且具有焊料球，使得可电连接堆叠于其上的另一集成电路封装的相应引线。所述堆叠导致相对于一衬底的集成电路密度增加，然而所述堆叠的集成电路封装仍能够具有一整体较薄或较低的轮廓。
改进的设备和方法尤其适用于堆叠相同大小(且通常相同功能)的集成电路封装。所述集成电路封装的用途的一个实例为一含有两个或两个以上类似大小的存储器存储集成电路封装的堆叠的非易失性存储器集成电路产品。
以下参考图1A-7B论述本发明的此方面的实施例。然而，所属领域的技术人员将不难了解，本文所给出的关于这些图的详细描述是出于解释的目的，因为本发明延伸超过这些有限的实施例。
图1A为一根据本发明的一实施例的集成电路封装100的俯视图。所述集成电路封装100包括一具有从其向外延伸的复数个导电引线104的封装外壳102。所述导电引线104表示一引线框的外部部分，所述引线框的内部部分驻留于封装外壳102内。另外，所述封装外壳102包封电耦接到所述引线框的内部区域的至少一个集成电路晶粒。因此，所述导电引线104提供到所述封装外壳102内的至少一个集成电路晶粒的电连接。
所述集成电路封装100的一个特征为其是可堆叠的。换句话说，不同的集成电路封装100可彼此堆叠于其上。通常，所述集成电路封装100垂直地彼此上下堆叠；然而，所述堆叠的定向不需要为垂直的。以下将更详细地描述有关堆叠所述集成电路封装100的另外细节。然而，为促进所述堆叠，所述集成电路封装100的导电引线104被设计成具有一可焊区域106和一不可焊区域108。每一导电引线104的不可焊区域108可属于单个区域或多个区域。例如，如图1A中所示，每一导电引线104在可焊区域106的每一侧上均具有一不可焊区域108。在一实施例中，由于引线104为所述引线框的一部分，所以其为导电的。例如，所述引线框且因此所述导电引线104可由诸如铜或金的导电金属制成。
可以许多不同方式形成或提供每一导电引线104的可焊区域106和不可焊区域108。在一实施中，假设导电引线104由既导电又可焊的材料制成，那么导电引线104上的可焊区域106可简单地表示导电引线104自身的一部分。在此实施中，为使所述导电引线104的不可焊区域是不可焊的，将一不可焊材料应用到不可焊区域108。如一实例，所述不可焊材料可为一金属层(例如，铝、铜或镍或金属合金)，其为不可焊的且将提供(例如，沉积)于导电引线104的不可焊区域108处。在另一实例中，所述不可焊材料可为一如模塑化合物的电介质。所述模塑化合物也称为包封材料。在其中将模塑化合物用于提供不可焊区域108的情况下，所述模塑化合物可(例如)与封装外壳102的模塑化合物相同和/或与其接近。尽管使用不可焊区域108，但导电引线104仍导电。
尽管图1A属于集成电路封装100的一俯视图，但应认识到，通常所述导电引线104的顶面和底面将包括类似的可焊区域和不可焊区域。此外，尽管图1A中所示的集成电路封装100在其四个侧面中的两个侧面处具有导电引线104，但应注意，一般所述集成电路封装100可在其侧面中的一个或一个以上处具有导电引线104。
图1B为一根据本发明的一实施例的图1A中所示的集成电路封装100的侧视图。在此实施例中，相对于封装外壳102中央提供引线104。在其它实施例中，可相对于封装外壳102在其它垂直位置中提供引线。例如，引线104可与封装外壳102的底部或顶部对准。不管所述引线的位置，所述集成电路封装较薄并因此具有一较低的轮廓。例如，集成电路封装100的高度(或厚度)约为0.5-1.5毫米(mm)。可广泛改变集成电路封装100的长度和宽度，诸如(例如)从5×5mm的较小大小到35×35mm的较大大小。例如，在一实施例中，所述集成电路封装100可称为一引线框芯片级封装(引线框CSP)。引线框CSP的实例包括方形扁平无引线(QFN)和小尺寸无引线(SON)封装。
图2A为一根据本发明的一实施例的集成电路封装200的侧视图。图2A中所示的集成电路封装200类似于图1B中所示的集成电路封装100。更具体地说，图2A中所示的集成电路封装200包括一封装外壳202，所述封装外壳202具有从所述封装外壳202延伸的导电引线204。另外，一焊料球206提供于从封装外壳202延伸出来的每一导电引线204上。所述焊料球206用于将集成电路封装200的导电引线204电连接到一衬底(例如，印刷电路板)或另一相同或类似的集成电路封装(例如，当被堆叠时)。在一实施中，导电引线204具有一约100-250微米的高度(厚度)，所述焊料球具有一约0.5-1.5mm的直径，且所述整个集成电路封装200的高度(厚度)在0.5-1.5mm的范围内。在一实施例中，焊料球的直径(更特定地说，焊料球的高度)类似于整个集成电路封装200的高度(厚度)。
图2B为图2A中所示的集成电路封装200的导电引线204中的一个导电引线的分解图。在所述分解图中，导电引线204中的一个导电引线描绘为从封装外壳202向外延伸。所述导电引线204被显示具有一提供于导电引线204的顶面上的焊料球206。更特定地说，焊料球206粘附到导电引线104顶面的可焊区域208。另一方面，为在导电引线204顶面上提供一不可焊区域，将一不可焊材料层210提供于属于不可焊区域的区域中的导电引线204的顶面上。例如，所述不可焊材料层210可为导电但不可焊的金属或金属合金(例如，铝、铜或镍)。如另一实例，所述不可焊材料层210可为有机材料。
所述不可焊区域的有益影响为当焊料球206被加热到一熔融状态时，所述焊料球206不会在不可焊区域上流动，且因此会大体上将其形状保持为一焊球。尽管当所述焊料球206被加热到一熔融状态时，可从一类似于球的形状(见图2B)稍微变形，但焊料球206的整个高度大体上保持相同。如果不存在所述不可焊区域，那么焊料球206将在导电引线204的顶面上回流，并因此将丢失其做为一球的所有特征，且将具有一从其原始高度动态减小的所得高度。
还应注意，所述导电引线204的底侧经类似构造，使得其具有一可焊区域212和一不可焊区域。所述不可焊区域通过在属于不可焊区域的区域中的导电引线204的底面上提供一不可焊材料层而形成。在图2B所示的实施例中，可焊区域212不包括一焊料球，因为通常所述导电引线204的每一个均具有一提供于顶面或底面上的焊料球。然而，在其中集成电路封装200彼此堆叠的情况下，来自一封装的焊料球206可用于在可焊区域212处连接到另一集成电路封装的导电引线204。
图3为一根据本发明的一实施例的集成电路封装形成过程300的流程图。所述集成电路封装形成过程300最初开始于提供一引线框302。通常，所述引线框为一形成于一薄片中的个别引线框阵列，使得复数个集成电路封装可同时产生。因此，相对于图3，可将所述引线框视为属于一个别引线框阵列。
提供引线框302后，将晶粒(集成电路芯片)附着到引线框304。此处，引线框阵列内的每一引线框实体可接收一个或一个以上的晶粒，且所述一个或一个以上的晶粒会连接到特定引线框实体。所述晶粒可以各种方式附着到引线框304。例如，对于一给定的引线框实体而言，可使用一粘着剂附着一晶粒。在所述实例中，可经由一可提供于晶粒与引线框之间的中间晶粒附着垫将所给定的引线框实体直接附着到所述引线框或间接附着到所述引线框。接着，将所述晶粒电连接到引线框306。此处，可以许多不同方式提供电连接。在一实施中，将所述晶粒导线接合到引线框。在另一实施中，焊料球将所述晶粒连接到引线框。
接下来，包封晶粒和引线框308。所述晶粒和引线框的包封形成一保护所述晶粒、电连接和引线框的封装体(或外壳)。一模塑化合物或包封材料用于形成封装体。虽然如此，用于所述阵列内的每一引线框实体的引线框的外围引线保持暴露。接着，将焊料球附着到这些暴露的引线310。由于如以上所描述形成暴露的引线，所述焊料球甚至当处于一熔融状态时也能够大体上保持其形状。
在这点上，已制备复数个集成电路封装并将其呈现于个别引线框阵列上。现在，将所述阵列单一化成单独的集成电路封装312。所述单一化可根据特定应用和集成电路封装类型而改变。例如，所述单一化可通过机械冲孔操作和/或锯切操作实现。集成电路封装与阵列结构分离后，所述集成电路封装形成过程300完成并结束。
图4为一根据本发明的一实施例的集成电路封装400的横截面图。所述集成电路封装400为本发明的一实施例的单晶粒实施。例如，集成电路封装400可表示图2A所示的集成电路封装200的一实施。例如，可根据以上相对于图3所描述的集成电路封装形成过程300进行集成电路封装400的形成。更特定地说，可将集成电路封装400构造于引线框402的周围(方框302)。此处，引线框402属于个别引线框阵列的个别引线框实体。所述引线框402可视为包括一内部区域和一外部区域。所述外部区域主要含有延伸超过集成电路封装400的封装体405的引线404。通过晶粒附着垫406将晶粒408附着到引线框402(方框304)。可通过粘着剂将晶粒附着垫406附着到引线框402的内部区域，并可用粘着剂将晶粒408附着到晶粒附着垫406。使用导线接合410将晶粒408电连接到引线框402(方框306)。一模塑化合物412形成封装体405，并包封引线框402的内部区域、晶粒附着垫406、晶粒408和导线接合410(方框308)。其后，将焊料球414提供于引线框402的引线404上(方框310)。所述集成电路封装400表示一可以阵列方式同时形成并接着在过程结束时进行单一化的单个实体，借此形成个别化的集成电路封装(方框312)。
图5为一根据本发明的另一实施例的集成电路封装500的横截面图。集成电路封装500包括所述集成电路封装500内复数个彼此上下堆叠的晶粒。例如，尽管引线框的垂直位置不同，但所述集成电路封装500可表示图2A中所示的集成电路封装200的一实施方案。例如，也可根据以上相对于图3所描述的集成电路封装形成过程300完成集成电路封装500的形成。更特定地说，可将集成电路封装500构造于引线框502的周围(方框302)。此处，引线框502属于个别引线框阵列的个别引线框实例。所述引线框502可视为包括一内部区域和一外部区域。所述外部区域主要含有延伸超过集成电路封装500的封装体505的引线504。第一晶粒506可具有一暴露于集成电路封装500的第一表面处的表面。可使用或不使用晶粒附着垫(未显示)将第一晶粒506附着到引线框502。使用导线接合510将第一晶粒506电连接到引线框502(方框306)。将一第二晶粒508堆叠于第一晶粒506上。可通过粘着剂和/或通过晶粒附着垫(未显示)将第二晶粒508附着到第一晶粒506。使用导线接合511将第二晶粒508电连接到引线框502(方框306)。一模塑化合物512形成封装体505，并包封引线框402的内部区域、第一晶粒506、第二晶粒508和导线接合510、511(方框308)。其后，将焊料球414提供于引线框502的引线504上(方框310)。所述集成电路封装400表示一可以一阵列方式同时形成并接着在过程结束时进行单一化的单个实例，借此形成个别化的集成电路封装(方框312)。
可使用各种替代方式来堆叠集成电路封装500内的晶粒506和508(以及可能另外的晶粒)。例如，2004年6月3日申请的题为“INTEGRATED CIRCUIT PACKAGE HAVINGSTACKED INTEGRATED CIRCUITS AND METHOD THEREFOR”的国际专利申请案第
号中描述的方法或技术，且其以引用的方式并入本文中。
在一实施中，集成电路封装500属于一非易失性存储器集成电路封装。所述集成电路封装500内的晶粒可具有相同功能或不同功能。例如，所述两个晶粒可属于存储器芯片，或所述晶粒中的一个属于存储器芯片，且所述晶粒中的另一个可属于一控制器芯片。
图6为一根据本发明的一实施例的集成电路封装的组装的、堆叠布置600的侧视图。所述被堆叠的集成电路封装为(例如)图2A中所示的集成电路封装200。所述堆叠布置600在衬底602上形成集成电路封装的堆叠。在一实施例中，所述衬底602为一印刷电路板(PCB)。在另一实施例中，所述衬底602为弯曲带(Flex Tape)。衬底602的顶面包括用于耦接到置于所述衬底602的顶部上的集成电路封装的导电迹线。
堆叠布置600包括：一第一集成电路封装604，其包括第一引线606和第一焊料球608；和一第二集成电路封装610，其包括第二引线612和第二焊料球614。第一集成电路封装604的引线606经由第一焊料球608耦接到衬底602的导电迹线。第二集成电路封装610堆叠于第一集成电路封装604上。在此实施例中，第二集成电路封装610与第一集成电路封装604具有相同的物理尺寸(即，大小)。当第二集成电路封装610堆叠于第一集成电路封装604上时，第二焊料球614用于将第二集成电路封装610的第二引线612中的个别第二引线连接到第一集成电路封装604的那些相应第一引线606。因此，第一和第二集成电路封装604、610的类似引线通过第二焊料球614分别彼此电连接，且也经由第一焊料球608连接到衬底602上的相应导电迹线。
集成电路封装604和610相对于衬底602的堆叠布置600可用于多种不同的电子装置中。当电子装置要保持较小时，所述堆叠布置600尤其有用，因此希望将所述堆叠集成电路封装(以及所述衬底)的厚度保持较薄。例如，所述电子装置可为一存储器卡。在一存储器卡的情况下，第一和第二集成电路芯片封装604和610可为存储器芯片封装，当彼此堆叠时，其在不消耗衬底602的顶面上的另外面积的情况下提供双倍存储器容量的能力，然而所述堆叠集成电路封装的高度可保持较薄(假设所述堆叠集成电路封装中的每一个的高度都较薄)。
图7A为一根据本发明的另一实施例的集成电路封装700的俯视图。图7B为一图7A中所说明的集成电路封装700的侧视图。当以模塑化合物形成所述不可焊区域时，集成电路封装700表示图1A、图1B和图2A中所示的集成电路封装100、200的一实施例。所述集成电路封装700包括一封装外壳702，所述封装外壳702具有复数个从其向外延伸的导电引线704。然而，在此实施例中，也将形成封装外壳702的模塑化合物提供于导电引线704的不可焊区域上。此另外模塑化合物706通常与封装外壳702成一体或与其邻近，且被同时应用，使得当形成所述封装外壳702时，形成额外模塑化合物706。在其中所述模塑化合物最初也应用于整个导电引线704上的情况下，将移除(如通过蚀刻过程)模塑化合物以暴露导电引线704的可焊区域。导电引线704的不可焊区域上的模塑化合物的厚度可(例如)约为0.2-0.3mm。同样，在此实施例中，将焊料块708附着到导电引线704的可焊区域。焊料块708能够将其高度保持为如其它实施例中所使用的焊料球的高度。如集成电路100一样，集成电路封装700是可堆叠的。
更一般地说，以上所利用的焊料球和焊料块为焊料元件或焊料沉积物。所述焊料元件或沉积物的几何形状可随应用而改变。所述焊料元件或沉积物的几何形状可(例如)包括至少一球和一块几何形状。应了解，使用焊料球的那些实施例可替代地使用焊料块，且反之亦然。如本文中所使用，术语“焊料球”不需要一纯粹的球形。例如，焊料球可主要以一圆形、球形、半球形或小于半球形的方式成形。
根据本发明的集成电路封装可用于存储器系统。本发明可进一步涉及一包括如上所论述的存储器系统的电子系统。存储器系统一般用于存储用于各种电子产品的数字数据。通常所述存储器系统可从电子系统移除，因此，所存储的数字数据可携带。这些存储器系统可称为存储器卡。根据本发明的存储器系统可具有相对较小的外形尺寸(formfactor)，且可用于存储如以下的电子产品的数字数据：照相机、手提或笔记本电脑、网卡、网络器械、机顶盒、手提或其它较小音频播放器/记录器(例如，MP3装置)和医疗监控器。存储器卡的实例包括一PC卡(原来为PCMCIA装置)、闪存卡、闪存盘、多媒体卡和ATA卡。例如，所述存储器卡可使用闪存或EEPROM型存储器单元来存储数据。更一般地说，存储器系统不仅可涉及一存储器卡，而且涉及一存储器棒或一些其它半导体存储器产品。
本发明的优点很多。不同的实施例或实施可得到以下优点中的一个或一个以上的优点。本发明的一个优点为薄集成电路封装表现为可堆叠的。本发明的另一优点为可低成本获得集成电路封装的可堆叠性，而不需要专门的连接器或模块来堆叠所述集成电路封装。本发明的又一优点为高密度存储器产品可通过将提供存储器存储的集成电路封装堆叠在一起而获得。
从所述书面描述可明了本发明的很多特征和优点，且因此希望上述权利要求覆盖本发明的所有所述特征和优点。此外，由于所属领域的技术人员容易做出很多修改和改变，因此，不希望将本发明限制于所说明和描述的精确构造和操作。因此，所有适当的修改和等同物均可在本发明的范围内。

Claims (34)

1.一种可堆叠的集成电路封装，其包含：
一引线框，其具有一内部区域和一外部区域，所述外部区域具有复数个导电引线，且所述导电引线的每一个均具有一不可焊区域和一可焊区域；
至少一晶粒，其电连接到所述引线框的所述内部区域；和
一包封材料，其环绕所述引线框的所述内部区域的至少大部分和所述至少一个晶粒，借此形成所述可堆叠的集成电路封装，而所述引线框的所述外部区域处的所述导电引线的至少所述可焊区域被暴露。
2.根据权利要求1所述的可堆叠的集成电路封装，其中所述不可焊区域是导电的。
3.根据权利要求1所述的可堆叠的集成电路封装，其中在所述不可焊区域内，所述导电引线的每一个均具有一提供于所述引线框的所述导电引线的一导电可焊底部材料上的不可焊材料层。
4.根据权利要求3所述的可堆叠的集成电路封装，其中所述不可焊材料为一不可焊金属。
5.根据权利要求4所述的可堆叠的集成电路封装，其中所述不可焊金属至少包括一金属合金。
6.根据权利要求4所述的可堆叠的集成电路封装，其中所述不可焊金属包括铝、铜和镍中至少一者。
7.根据权利要求3所述的可堆叠的集成电路封装，其中所述不可焊材料为一电绝缘体。
8.根据权利要求3所述的可堆叠的集成电路封装，其中所述不可焊材料为一有机材料。
9.根据权利要求8所述的可堆叠的集成电路封装，其中所述电绝缘体为所述包封材料。
10.根据权利要求1所述的可堆叠的集成电路封装，其中所述引线框的所述外部区域处的所述导电引线的所述不可焊区域未被暴露，但被所述包封材料覆盖。
11.根据权利要求1所述的可堆叠的集成电路封装，其中所述导电引线的每一个均具有一顶侧和一底侧，且
其中所述导电引线的每一个的所述顶侧和所述底侧均具有一不可焊区域和一可焊区域。
12.根据权利要求1所述的可堆叠的集成电路封装，其中所述导电引线的每一个均具有一顶侧和一底侧，且
其中所述导电引线的每一个的所述不可焊区域和所述可焊区域应用到所述导电引线的所述顶侧和所述底侧。
13.根据权利要求1所述的可堆叠的集成电路封装，其中所述可堆叠的集成电路封装进一步包含提供于所述导电引线的每一个的所述可焊区域上的至少一个焊料沉积物。
14.根据权利要求13所述的可堆叠的集成电路封装，其中所述导电引线的每一个的所述不可焊区域用于分别将所述至少一个焊料沉积物限制到所述导电引线的每一个的所述可焊区域。
15.根据权利要求13所述的可堆叠的集成电路封装，其中所述至少一个焊料沉积物具有一球、一球体或一球或一球体的一部分的形状。
16.根据权利要求13所述的可堆叠的集成电路封装，其中所述集成电路封装为一引线框芯片级封装。
17.根据权利要求1-16中任一权利要求所述的可堆叠的集成电路封装，其中所述集成电路封装的厚度小于或等于约1.5毫米。
18.一种提供非易失性数据存储的存储器卡，其包含：
一第一可堆叠的集成电路封装，其具有一顶面和一底面，所述第一可堆叠的集成电路封装至少包括：
一第一引线框，其具有一内部区域和一外部区域，所述外部区域具有复数个导电引线，且所述导电引线的每一个均具有一不可焊区域和一可焊区域；
至少一晶粒，其电连接到所述第一引线框的所述内部区域；
一包封材料，其环绕所述第一引线框的所述内部区域的至少大部分和所述至少一个晶粒，借此形成所述第一可堆叠的集成电路封装，所述第一引线框的所述外部区域处的所述导电引线的至少所述可焊区域被暴露；和
第一焊料球，其提供于所述导电引线的每一个的所述可焊区域上，
一第二可堆叠的集成电路封装，其具有一顶面和一底面，所述第二可堆叠的集成电路封装至少包括：
一第二引线框，其具有一内部区域和一外部区域，所述外部区域具有复数个导电引线，且所述导电引线的每一个均具有一不可焊区域和一可焊区域；
至少一晶粒，其电连接到所述第二引线框的所述内部区域；
一包封材料，其环绕所述引线框的所述内部区域的至少大部分和所述至少一个晶粒，借此形成所述第二可堆叠的集成电路封装，而所述第二引线框的所述外部区域处的所述导电引线的至少所述可焊区域被暴露；和
第二焊料球，其提供于所述导电引线的每一个的所述可焊区域上，
其中所述第二可堆叠的集成电路封装堆叠于所述第一可堆叠的集成电路芯片上，且其中所述第二焊料球将所述第二可堆叠的集成电路封装的所述导电引线电连接到所述第一可堆叠的集成电路封装的所述导电引线中的相应导电引线。
19.根据权利要求18所述的存储器卡，
其中所述存储器卡进一步包含一具有信号迹线的衬底，且
其中所述第一焊料球将所述第一可堆叠的集成电路封装的所述导电引线电连接到所述衬底上的所述信号迹线。
20.根据权利要求18或19所述的存储器卡，其中所述第一和第二可堆叠的集成电路芯片具有相同的大小和功能。
21.根据权利要求18或19所述的存储器卡，其中所述第一和第二可堆叠的集成电路芯片是相同的。
22.一种用于形成一可堆叠的集成电路封装的方法，所述方法包含：
获得一具有复数个导电引线的金属引线框；
将一第一晶粒附着到所述金属引线框的一内部区域；
使用导电链将所述第一晶粒电连接到所述金属引线框的一外部区域；
包封所述第一晶粒、所述导电链和所述金属引线框的大部分，使得所述金属引线框的所述外部区域处的所述导电引线的一外围部分未被包封；和
将一焊料沉积物附着到所述金属引线框的所述外部区域处的所述导电引线的每一个。
23.根据权利要求22所述的方法，其中所述导电链为导线接合。
24.根据权利要求22所述的方法，其中所述导电链为焊料球。
25.根据权利要求22所述的方法，其中所述导电引线的每一个在所述导电引线的所述外围部分处均具有一不可焊区域和一可焊区域。
26.根据权利要求25所述的方法，其中在所述包封期间形成所述导电引线的每一个的所述不可焊区域。
27.根据权利要求26所述的方法，
其中操作所述包封以使用一模塑材料进行包封，且
其中，在所述包封期间，放置于所述导电引线的所述外围部分处的所述不可焊区域上的所述模塑材料使所述导电引线的此部分不可焊。
28.根据权利要求25-27中任一权利要求所述的方法，其中在形成所述集成电路封装之前，在所述金属引线框上形成所述导电引线的每一个的所述不可焊区域。
29.根据权利要求28所述的方法，其中将一不可焊材料层提供于所述导电引线的每一个的所述不可焊区域上。
30.根据权利要求29所述的方法，其中所述不可焊材料为铝、镍或铜中的至少一者。
31.根据权利要求22-27中任一权利要求所述的方法，其中所述方法进一步包含：
在所述包封之前，将一第二晶粒附着到所述第一晶粒，并使用导电链将所述第二晶粒电连接到所述金属引线框的所述外部区域。
32.根据权利要求22所述的方法，其中所述导电引线的每一个的所述焊料沉积物具有一球、一球体或一球或一球体的一部分的形状。
33.一种电子装置，其包含：
一印刷电路板；
一第一可堆叠的集成电路封装，其具有第一延伸导电引线，所述第一延伸导电引线的每一个均具有一不可焊区域和一可焊区域，且在所述第一延伸导电引线的每一个的所述可焊区域处具有第一焊料沉积物；和
一第二可堆叠的集成电路封装，其具有第二延伸导电引线，所述第二延伸导电引线的每一个均具有一不可焊区域和一可焊区域，且在所述第二延伸导电引线的每一个的所述可焊区域处具有第二焊料沉积物，
其中所述第一可堆叠的集成电路封装安装于所述印刷电路板上，且所述第一焊料沉积物用于将所述第一可堆叠的集成电路封装的所述第一延伸导电引线至少电耦接到所述印刷电路板，且
其中所述第二可堆叠的集成电路封装堆叠于所述第一可堆叠的集成电路封装上，且所述第二焊料沉积物用于将所述第二可堆叠的集成电路封装的所述第二延伸导电引线至少电耦接到所述第一可堆叠的集成电路封装的所述第一延伸导电引线中相应的第一延伸导电引线，借此经由所述第一可堆叠的集成电路封装的所述第一延伸导电引线将所述第二可堆叠的集成电路封装的所述第二延伸导电引线至少电耦接到所述印刷电路板。
34.根据权利要求23所述的电子装置，其中所述电子装置为一存储器卡。
CNA2004800200074A 2003-06-16 2004-06-03 可堆叠的集成电路封装和用于其的方法 Pending CN1823416A (zh)

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