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Publication numberCN1809923 A
Publication typeApplication
Application numberCN 200480017639
PCT numberPCT/GB2004/002440
Publication date26 Jul 2006
Filing date9 Jun 2004
Priority date23 Jun 2003
Also published asCN100435329C, DE602004032433D1, EP1636840A1, EP1636840B1, US7253506, US20050003583, WO2004114405A1
Publication number200480017639.5, CN 1809923 A, CN 1809923A, CN 200480017639, CN-A-1809923, CN1809923 A, CN1809923A, CN200480017639, CN200480017639.5, PCT/2004/2440, PCT/GB/2004/002440, PCT/GB/2004/02440, PCT/GB/4/002440, PCT/GB/4/02440, PCT/GB2004/002440, PCT/GB2004/02440, PCT/GB2004002440, PCT/GB200402440, PCT/GB4/002440, PCT/GB4/02440, PCT/GB4002440, PCT/GB402440
Inventors戴维吉廷
Applicant大动力公司
Export CitationBiBTeX, EndNote, RefMan
External Links: SIPO, Espacenet
Micro lead frame package and method to manufacture the micro lead frame package
CN 1809923 A
Abstract  translated from Chinese
本发明包括一种适合于接收半导体单元片和多个无源元件的引线框基片。 The present invention comprises a lead frame adapted to receive a semiconductor substrate and a plurality of die passive components. 引线框基片优选地由单片导电材料如铜形成,并且可以安装到引线框封装中或直接安装到电路板上。 Preferably, the lead frame substrate formed from a single piece such as a copper conductive material, and may be mounted to a lead frame package or mounted directly to the circuit board. 引线框基片包括适合于接收半导体单元片和无源元件的安装表面。 Lead frame substrate comprises a mounting surface adapted to receive a semiconductor die and passive components. 安装表面通过临时和/或永久连接条链接到一起。 Link to the mounting surface by a temporary and / or permanent connection strips together. 一种制造引线框封装的方法其中包括步骤:形成引线框基片、将模制料应用到引线框基片上以将每个安装表面和连接条固定在适当位置、去除临时连接条、将半导体元件安装到引线框基片上,以及在引线框基片上应用封装材料以封装半导体元件。 A method of manufacturing a lead frame package, including the steps of: forming a lead frame substrate, the molding material is applied to the lead frame substrate surface and to each of the mounting strap is fixed in place, removing the temporary connection bars, a semiconductor element mounted on the lead frame substrate, and the application of the encapsulating material on the lead frame substrate to encapsulate the semiconductor elements.
Claims(42)  translated from Chinese
1.一种引线框基片,包括:多个连接条;适合于接收半导体单元片的半导体单元片盘;通过所述多个连接条链接到一起并链接到所述半导体单元片盘的多个终端盘,所述多个终端盘的每个被配置以接收无源元件和焊线;以及将所述引线框基片的所述半导体单元片盘、所述多个终端盘,以及所述多个连接条固定在一起的模制料。 1. A lead frame substrate, comprising: a plurality of connection bars; adapted to receive a semiconductor die in a semiconductor die plate; link via the plurality of connection bars together and linked to said plurality of semiconductor die plate terminal plate, each of said plurality of terminals disc is configured to receive a passive element and bonding wires; the semiconductor die and the leadframe disc substrate, said plurality of terminals disc, and the multi- a connecting bar secured together molding material.
2.根据权利要求1的引线框基片,其中所述半导体单元片盘、所述多个终端盘,以及所述多个连接条具有来自共同材料件的单体结构。 2. The lead frame substrate according to claim 1, wherein said semiconductor die plate, said plurality of terminal plate, and said plurality of connection bars having a structure derived from a monomer of a common piece of material.
3.根据权利要求1或2的引线框基片,其中所述半导体单元片盘、所述多个终端盘,以及所述多个连接条包括导热和导电材料。 The lead frame substrate according to claim 1 or 2, wherein said semiconductor die plate, said plurality of terminal plate, and said connecting bar comprises a plurality of thermally and electrically conductive material.
4.根据前述权利要求的任一个的引线框基片,其中所述导热和导电材料包括铜。 4. A lead frame according to any one of the preceding claims the substrate, wherein said thermally and electrically conductive material comprises copper.
5.根据前述权利要求的任一个的引线框基片,其中所述半导体单元片盘、所述多个终端盘,以及所述多个连接条包括顶面和底面。 5. A lead frame according to any one of the preceding claims the substrate, wherein said semiconductor die plate, said plurality of terminal plate, and said plurality of connection bars include a top and bottom surfaces.
6.根据权利要求5的引线框基片,其中所述模制料不覆盖所述顶面和底面。 6. The lead frame substrate according to claim 5, wherein said molding material does not cover the top and bottom surfaces.
7.根据前述权利要求的任一个的引线框基片,还包括位于引线框基片周边附近的多个引线。 7. A lead frame according to any one of the preceding substrate claims, further comprising a plurality of leads of the lead frame substrate near the periphery.
8.根据权利要求7的引线框基片,其中所述模制料将所述多个引线固定在所述模制料中。 8. The lead frame substrate according to claim 7, wherein said molding material for the plurality of leads fixed to the molding compound.
9.根据前述权利要求的任一个的引线框基片,其中所述多个连接条将所述半导体单元片盘电连接到所述多个终端盘。 According to any one of the preceding claims leadframe substrate, wherein said plurality of connecting strips to the semiconductor die is electrically connected to said plurality of disk terminals disc.
10.根据前述权利要求的任一个的引线框基片,其中所述多个连接条将所述多个终端盘电连接到一起。 10. A lead frame according to any one of the preceding substrate claims, wherein said plurality of connecting bar of the plurality of terminals electrically connected to the disc together.
11.根据前述权利要求的任一个的引线框基片,其中所述多个连接条包括永久连接条和临时连接条。 11. comprises a permanent connection bars and temporary connection bars lead frame according to any one of the preceding substrate claims, wherein said plurality of connecting bar.
12.根据权利要求11的引线框基片,其中所述临时连接条将所述多个终端盘固定到相对于彼此的适当位置。 12. The lead frame substrate according to claim 11, wherein the temporary connection of said plurality of terminal strip is fixed to the disc proper position relative to each other.
13.根据权利要求11或12的引线框基片,其中在将引线框基片安装到引线框上之前从引线框基片中去除所述临时连接条。 13. The lead frame substrate according to claim 11 or 12, wherein prior to the lead frame substrate being mounted on the lead frame strip to remove the temporary connection from the lead frame substrate.
14.根据前述权利要求的任一个的引线框基片,其中引线框基片包括基本上均匀的厚度。 14. A lead frame according to any one of the substrates of the preceding claims, wherein the lead frame substrate comprises a substantially uniform thickness.
15.根据前述权利要求的任一个的引线框基片,其中引线框基片被配置以安装到电路板上。 15. A lead frame according to any one of the preceding claims the substrate, wherein the lead frame substrate is configured to be installed to the circuit board.
16.根据权利要求15的引线框基片,其中当引线框基片安装到电路板上时,仅所述半导体单元片盘和所述多个引线接触电路板。 16. The lead frame substrate according to claim 15, wherein when the lead frame substrate is mounted on a circuit board, only said semiconductor die and said plurality of lead plate contact circuit board.
17.根据权利要求1~16的任一个的引线框基片,引线框基片包括多个半导体单元片盘,所述多个半导体单元片盘的每个适合于接收半导体单元片,其中所述多个终端盘通过所述多个连接条链接到一起并链接到所述多个半导体单元片盘,并且所述模制料将所述引线框基片的所述多个半导体单元片盘、所述多个终端盘、所述多个连接条,以及所述多个引线固定在一起。 17. The lead frame substrate according to any one of claims 1 to 16, the lead frame substrate comprising a plurality of semiconductor die plate, the plurality of semiconductor die disc each adapted to receive a semiconductor die, wherein said a plurality of terminals through said plurality of discs connecting bar linked together and linked to said plurality of semiconductor die plate, and the molding material for the leadframe substrate said plurality of semiconductor die plate, the a plurality of terminals of said disc, said plurality of connecting strips, and the plurality of leads are secured together.
18.根据权利要求17的引线框基片,其中当引线框基片安装到电路板上时仅所述多个半导体单元片盘和所述多个引线接触电路板。 18. The lead frame substrate according to claim 17, wherein said plurality of semiconductor die only when the disc substrate is mounted to the lead frame and the circuit board of the plurality of leads contact the circuit board.
19.根据权利要求17或18的引线框基片,其中所述多个连接条将所述多个半导体单元片盘电连接到所述多个终端盘。 19. The lead frame substrate according to claim 17 or claim 18, wherein said plurality of connecting bar of the plurality of semiconductor die plate of said plurality of terminals electrically connected to the disc.
20.根据权利要求17~19的任一个的引线框基片,其中所述框架、所述多个连接条、所述多个半导体单元片盘,以及所述多个终端盘具有来自共同导电材料件的单体结构。 20. any one of 17 to 19 lead frame substrate according to claim, wherein said frame, said plurality of connection bars, said plurality of semiconductor die plate, and a disc having the plurality of terminals from a common conductive material single structural member.
21.一种引线框封装,包括:具有中心部分的外壳以及位于所述外壳周边附近的多个引线;以及安装到所述中心部分上的根据权利要求1~16的引线框基片,所述引线框基片电耦连到所述多个引线的至少一个。 21. A lead frame package, comprising: a housing having a central portion and a plurality of leads located around the periphery of said housing; and mounted to the central portion as claimed in claim 1 to the lead frame substrate 16, the leadframe substrate electrically coupled to at least one of said plurality of leads.
22.根据权利要求21的引线框封装,其中在将所述引线框基片安装到所述中心部分上之前从所述引线框基片中去除所述临时连接条。 22. The lead frame package according to claim 21, wherein prior to mounting the lead frame substrate on said central portion to said temporary connection is removed from the lead frame strip substrate.
23.根据权利要求21或22的引线框封装,还包括封装材料,所述封装材料将所述多个连接条每个的、所述半导体单元片盘的、所述多个终端盘每个的以及所述模制料的所述顶面封装。 23. The lead frame package according to claim 21 or 22, further comprising a packaging material, the packaging material of each of said plurality of connection bars, said semiconductor die plate, each of said plurality of terminals disc and the molding material of the top surface of the package.
24.一种引线框封装,包括:具有中心部分的外壳以及位于所述外壳周边附近的多个引线;安装到所述中心部分上的根据权利要求17~20的任一个的引线框基片,所述引线框基片电耦连到所述多个引线的至少一个。 24. A lead frame package, comprising: a housing having a central portion and a plurality of leads located around the periphery of said housing; mounted to the central portion as claimed in any one of claim 17 to 20 of the lead frame substrate, The lead frame substrate electrically coupled to at least one of said plurality of leads.
25.根据权利要求21~24的任一个的引线框封装,其中所述外壳包括塑料。 25. 21 to 24 according to any claim of a lead frame package, wherein said housing comprises plastic.
26.一种引线框封装,包括:具有包括导电部分和不导电部分的顶面的电路板;以及安装到所述电路板的所述顶面上的根据权利要求1~20中任一个的引线框基片。 26. A lead frame package, comprising: including a conductive portion and having a non-conductive portion of the top surface of the circuit board; and a circuit board mounted to the top surface of the claims 1 to 20 according to any one of the leads block substrate.
27.根据权利要求26的引线框封装,其中所述引线框基片的多个引线和所述引线框基片的所述半导体单元片盘电耦连到所述电路板的所述导电部分。 27. The lead frame package according to claim 26, wherein said lead frame substrate and a plurality of leads of said lead frame substrate of the semiconductor die plate electrically coupled to the conductive portion of said circuit board.
28.一种制造引线框基片的方法,引线框基片被配置以接收半导体单元片和分立无源元件,该方法包括步骤:(a)在导电材料片中形成引线框基片,引线框基片包括至少一个半导体单元片盘、多个终端盘,以及将半导体单元片盘和多个终端盘链接到一起的多个临时和永久连接条;(b)将模制料应用到所述步骤(a)中所形成的引线框基片;以及(c)从引线框基片中去除多个临时连接条。 28. A method of manufacturing a lead frame substrate, the lead frame substrate is configured to receive a semiconductor die, and discrete passive components, the method comprising the steps of: (a) in the conductive sheet material forming the lead frame substrate, the lead frame substrate comprises at least one semiconductor die plate, a plurality of terminals disc, and a semiconductor die plate and a plurality of terminals a plurality of discs linked together temporary and permanent connection bars; (b) the molding material is applied to the step a lead frame substrate (a), formed; and (c) removing the plurality of temporary connection bars from the lead frame substrate.
29.根据权利要求28的方法,其中:步骤(a)包括在导电材料中形成多个引线框基片,多个引线框基片的每个包括通过多个临时连接条和多个永久连接条链接到一起的至少一个半导体单元片盘和多个终端盘;步骤(b)包括将模制料应用到所述步骤(a)中所形成的多个引线框基片的每个上;以及步骤(c)包括从每个引线框基片中去除多个临时连接条。 Each includes a plurality of temporary connection bars and by a plurality of permanent connection bars plurality of lead frame substrates of step (a) comprises a plurality of lead frame substrates formed in the conductive material,: 29. The method according to claim 28, wherein and a step; step (b) each of the lead frame substrate comprising a plurality of molding material applied to the said step (a) is formed; and linked together, at least one semiconductor die plate and a plurality of terminal plate (c) comprises removing the plurality of temporary connection bars from each lead frame substrate.
30.根据权利要求29的方法在步骤(c)之后还包括步骤:(d)将粘合带应用到每个引线框基片的背面;(e)将分立无源元件安装到终端盘上;(f)将半导体单元片安装到每个半导体单元片盘上;(g)形成焊接连接;以及(h)在所述步骤(a)中所形成的每个引线框基片上应用封装材料,封装材料将所述步骤(e)中所安装的分立无源元件、所述步骤(f)中所安装的半导体单元片,以及所述步骤(g)中所形成的焊接连接封装。 After 30. The method of claim 29 in step (c) further comprises the step of: (d) the adhesive tape is applied to the back of each lead frame substrate; (e) the discrete passive components mounted on the terminal plate; (f) the semiconductor die is mounted on each of the semiconductor die plate; (g) forming a solder connection; and (h) applied to each lead frame substrate in said step (a) formed in the package material, the package The welding of the semiconductor material die discrete passive components said step (e) is installed, said step (f), installed, and said step (g) formed in the connecting package.
31.根据权利要求30的方法,还包括:(i)将材料片分成独立单元,独立单元的每个包含引线框基片。 31. The method of claim 30, further comprising: (i) the piece of material into individual units, individual units containing a lead frame of each substrate.
32.根据权利要求28~31的任一个的方法,其中所述步骤(b)中应用模制料还包括将该至少一个半导体单元片盘、多个终端盘、多个临时连接条,以及多个永久连接条固定在模制料中。 32. The method of any one of claim 28 to claim 31, wherein said step (b) the application of the molding material further comprises at least one semiconductor die plate, a plurality of terminal plate, a plurality of temporary connection bars, and more permanent connection strips fixed in the molding compound.
33.根据权利要求28~32的任一个的方法,其中所述步骤(a)中形成每个引线框基片通过冲压处理来实现。 33. The method of any one of claims 28 to 32, wherein said step (a) in each lead frame substrate formed by press processing to achieve.
34.根据权利要求28~32的任一个的方法,其中所述步骤(a)中形成每个引线框基片通过刻蚀处理来实现。 34. The method of any one of claim 28 to claim 32, wherein said step (a) is formed in each of the lead frame substrate by etching processing to achieve.
35.根据权利要求28~34的任一个的方法,其中所述步骤(c)中去除多个临时连接条通过冲压处理来实现。 35. The method of any one of claims 28 to 34, wherein said step (c) a plurality of temporary connection bars are removed by punching processing to achieve.
36.根据权利要求28~34的任一个的方法,其中所述步骤(c)中去除多个临时连接条通过刻蚀处理来实现。 36. The method of any one of claims 28 to 34, wherein said step (c) a plurality of temporary connection bars are removed by etching treatment to achieve.
37.根据权利要求28~34的任一个的方法,其中所述步骤(c)中去除多个临时连接条通过激光切割处理来实现。 37. The method of any one of claims 28 to 34, wherein said step (c) a plurality of temporary connection bars are removed by laser cutting process to achieve.
38.根据权利要求28~34的任一个的方法,其中所述步骤(c)中去除多个临时连接条通过研磨处理来实现。 38. The method of any one of claims 28 to 34, wherein said step (c) a plurality of temporary connection bars are removed by polishing treatment to achieve.
39.根据权利要求28的方法在步骤(b)和(c)之间还包括步骤:(i)将粘合带应用到每个引线框基片的背面;(ii)将分立无源元件安装到终端盘上;(iii)将半导体单元片安装到每个半导体单元片盘上;(iv)形成焊接连接;(v)在所述步骤(a)中所形成的每个引线框基片上应用封装材料,封装材料将所述步骤(ii)中所形成的分立无源元件、所述步骤(iii)中所安装的半导体单元片,以及所述步骤(iv)中所形成的焊接连接封装;以及(vi)去除所述步骤(i)中所应用的粘合带;以及其中步骤(c)包括将刻蚀处理应用到每个引线框基片的背面以去除多个临时连接条。 39. The method of claim 28 in step (b) and (c) further comprises the step between: (i) the adhesive tape is applied to the back of each lead frame substrate; (ii) the discrete passive components are mounted to the terminal plate; (iii) the semiconductor die is mounted on each of the semiconductor die plate; (iv) forming a solder connection; application on (v) each of the lead frame substrate in said step (a) formed in the packaging materials, packaging materials welded semiconductor die discrete passive components of said step (ii) formed in the said step (iii) are installed, and said step (iv) formed in the package is connected; and an adhesive tape (vi) removing said step (i) in the application; and wherein step (c) comprises etching treatment is applied to the back of each lead frame substrate to remove the plurality of temporary connection bars.
40.根据权利要求28~39的方法,其中:步骤(a)包括在材料片中形成引线框基片,其中引线框基片包括至少一个半导体单元片盘、多个终端盘、将半导体单元片盘和多个终端盘链接到一起的多个临时和永久连接条,以及多个永久和临时引线;步骤(b)包括将模制料应用到所述步骤(a)中所形成的引线框基片上,模制料将半导体单元片盘、多个终端盘、多个临时和永久连接条,以及多个永久和临时引线固定在一起;以及步骤(c)包括从引线框基片中去除多个临时连接条和临时引线。 28 to 40. The method according to claim 39, wherein: step (a) is included in the lead frame sheet substrate material is formed, wherein the lead frame substrate comprises at least one semiconductor die plate, a plurality of terminal plate, a semiconductor die plate and a plurality of terminal plate link together a plurality of temporary and permanent connection bars, and a plurality of permanent and temporary leads; leadframe yl step (b) comprises the molding material is applied to said step (a) formed in the on-chip, molding material for the semiconductor die plate, a plurality of terminal plate, a plurality of temporary and permanent connection bars, and a plurality of permanent and temporary leads together; and a step (c) comprises removing the substrate from the plurality of lead frame temporary connection bars and temporary lead.
41.根据权利要求40的方法,其中在所述步骤(a)中形成引线框基片时形成比终端盘、临时连接条,以及临时引线更厚的半导体单元片盘和永久引线。 41. The method of claim 40, wherein the lead frame substrates are formed in said step (a) is formed to be thicker than the terminal plate, the temporary connection bars and temporary leads of the semiconductor die plate and permanent leads.
42.根据权利要求40或41的方法,其中多个永久或临时引线位于所述步骤(a)中所形成的引线框基片的周边附近。 42. The method according to claim 40 or claim 41, wherein the plurality of permanent or temporary lead in said step (a) formed in the lead frame substrate near the periphery.
Description  translated from Chinese
微引线框封装及制造微引线框封装的方法 Micro leadframe package and micro leadframe package method of manufacturing

技术领域 FIELD

本发明一般地涉及微引线框设计封装及组装领域。 The present invention relates generally to micro-leadframe package design and assembly areas. 更特别地,本发明包括适合于接收至少一个半导体芯片和多个分立无源元件的微引线框基片,其可安装到引线框中或直接安装到电路板上。 More particularly, the present invention include those suitable for receiving at least one semiconductor chip and a plurality of discrete passive components micro lead frame substrate, which can be mounted to a lead frame or mounted directly to the circuit board.

背景技术 BACKGROUND

在热消散和热管理方面,现今功率应用中的多芯片模组(MCM)面临重大挑战。 In the heat dissipation and thermal management, power applications in today's multi-chip module (MCM) is facing major challenges. 连同需要以具有低热阻抗的均匀方式消散热量,还需要减小空间和成本。 Together with the need for a uniform manner with low thermal impedance to dissipate heat, is also a need to reduce space and cost. 封装MCM的常规方法采用焊区栅格阵列(LGA)或球状栅格阵列(BGA)型基片形式,其包括布置在层压基片上的多个芯片(半导体单元片)加上无源元件。 MCM package using conventional methods pad Grid Array (LGA) or ball grid array (BGA) type substrate form, which comprises the laminated substrate disposed on a plurality of chips (semiconductor die) plus the passive components. 基片材料按惯例具有高的热阻抗,甚至借助热管理技术加强后仍然不能满足引线框设计的低热阻抗。 Substrate material having a high thermal impedance conventionally, even after strengthening by means of thermal management techniques still can not meet the low thermal impedance of the lead frame design.

关于功率部件安装表面,常规引线框器件具有优秀热导性和最佳热消散。 Power components installed on the surface, the conventional leadframe device has excellent thermal conductivity and optimum heat dissipation. 但是,常规引线框设计及制造方法限制其在封装中安装多个无源元件的能力。 However, the conventional method of manufacturing a lead frame design and limit its ability to install a plurality of passive elements in the package. 制造适合于接收功率半导体芯片和无源元件的引线框经常关联着长的制造时间、增加的费用,从而一般地不认为是高效的制造选择。 Manufacturing is adapted to receive power semiconductor chips and passive elements of the lead frame is often associated with long manufacturing time, increased costs, and thus generally not considered to be efficient manufacturing choice. 常规引线框适合于仅接收功率半导体芯片。 Conventional lead frame is adapted to receive only the power semiconductor chip. 因此,外部元件必须连接到引线框以确保操作有效性,这也增加成本(购买、布局等)和客户板子的空间。 Thus, external components must be connected to the lead frame to ensure the validity of the operation, which also increases costs (purchase, layout, etc.) and customer board space.

图1A-1B说明常规引线框封装10。 Figure 1A-1B illustrate a conventional lead frame package 10. 引线框包括半导体芯片盘14和布置在引线框10周边附近的多个引线16。 The lead frame comprising a semiconductor chip tray 14 and a plurality of leads disposed on the lead frame 10 near the periphery 16. 制造图1A-1B中所示的无引线半导体芯片封装的常规方法包括步骤:(1)将半导体芯片12贴附到引线框10的单元片盘14上,其中引线框10包括布置在单元片盘14周边附近的多个引线16;(2)将引线框10的引线焊接到半导体单元片上的焊接盘(如图1b中的线18所示);以及(3)以这样的方式在半导体单元片12和引线框10上形成封装体20,即引线框10的每个引线16至少有一部分17从封装体的底部暴露。 Leadless conventional method of manufacturing a semiconductor chip package shown in FIG. 1A-1B comprises the steps of: (1) the semiconductor chip 12 is attached to the lead frame unit 10 of the spool 14, wherein the lead frame 10 includes a die plate disposed 14 near the periphery of the plurality of leads 16; (2) the lead frame leads 10 are welded to the bonding pads (Figure 1b the line 18) on the semiconductor die; and (3) in such a manner in the semiconductor die 12 is formed on the lead frame 10 and the package 20, i.e., the lead frame 16 of each lead 10 at least a portion 17 is exposed from the bottom of the package. 该常规引线框封装10仅支持单个半导体单元片12。 The conventional lead frame package 10 supports only a single semiconductor die 12. 封装10不能支持任何无源元件。 Package 10 can not support any passive components. 因此,无源元件(例如,电阻器和电容器)必然在封装10的外部。 Thus, passive components (e.g., resistors and capacitors) in the exterior of the package 10 is bound.

发明内容 SUMMARY

通过提供一种适合于接收分立无源元件的并可布置到微引线框封装中或直接布置到电路板上的引线框基片,以及进一步提供一种制造引线框的方法,所提出的发明解决这些问题中的许多。 Adapted to the invention by providing a micro leadframe package or directly to the lead frame is disposed on the circuit board substrate, and further provides a method of manufacturing a lead frame, to receiving proposed discrete passive components and is arranged to solve Many of these issues.

本发明的一个方面在于提供一种成本相对低的具有相对简单结构的并在封装中集成功率半导体单元片和无源元件的引线框封装。 One aspect of the present invention is to provide a relatively low cost with a relatively simple structure and integration of the power semiconductor die and passive components in the package lead frame package. 在一种实施方案中,包括电连接到多个终端盘的半导体单元片盘的微引线框基片(“MLF基片”)安装在引线框上。 In one embodiment, includes a plurality of terminals electrically connected to the semiconductor die disc tray micro lead frame substrate ("MLF substrate") is mounted on the lead frame. 半导体单元片盘适合于接收功率半导体单元片(例如,MOSFET)、控制器ASIC、PWM控制器等。 The semiconductor die plate adapted to receive a power semiconductor die (e.g., MOSFET), the controller ASIC, PWM controllers. 终端盘适合于接收分立无源元件(例如,电阻器和电容器)或焊线。 A terminal plate adapted to receive discrete passive components (e.g., resistors and capacitors) or wire bonding. 因此所有半导体元件都位于相同封装中。 Thus all of the semiconductor elements are located in the same package.

本发明的另一个方面在于提供一种可配置MLF基片以满足特定封装要求的封装。 Another aspect of the present invention is to provide a configurable MLF substrate to meet specific packaging requirements of the package. 在一种实施方案中,MLF基片中的终端盘通过临时和永久连接条的组合链接到一起。 In one embodiment, MLF substrate terminal plate by temporary and permanent connection of the combination are linked together. 临时连接条为MLF基片提供刚性,并在最后被去除。 Temporary connection bar provides rigidity for the MLF substrate, and finally removed. 临时连接条不提供最终引线框封装中的终端盘之间的电连接。 Temporary connection shall not provide a final package leadframe terminals electrically connected between the plates. 永久连接条将半导体单元片盘和终端盘电连接到一起。 Permanently connecting bar semiconductor die plate and the terminal plate electrically connected together.

本发明的又一个方面在于提供一种用于半导体封装的MLF基片。 Yet another aspect of the present invention is to provide a method for MLF substrate semiconductor package. 在一种实施方案中,引线框包括具有中心盘的外壳以及在其周边附近的引线。 In one embodiment, the lead frame includes a housing having a center of the disk and in the vicinity of the periphery thereof a lead. MLF基片安装到引线框的中心盘上,并电连接到引线。 MLF substrate is mounted to the center of the disc to the lead frame, and electrically connected to the lead. 因此,引线框封装包括分立无源元件,并节省客户板子空间。 Therefore, leadframe package includes discrete passive components and board space savings customers. 在另一种实施方案中,MLF基片直接安装到客户板子上,使得功率半导体单元片所产生的热量直接消散到客户板子中。 In another embodiment, MLF substrate is mounted directly to the client board, so that heat generated by the power semiconductor die is dissipated directly to the client in the board. 在又一种实施方案中,仅MLF基片的半导体单元片盘和引线接触客户板子。 In yet another embodiment, only the MLF substrate semiconductor die and the lead plate contacts the customer board. MLF基片的底面具有台阶特性,由此接触盘(例如,功率半导体单元片盘、控制器盘,以及引线)比MLF基片的非接触部分(例如,永久连接条)厚。 The bottom surface of the MLF substrate has a step characteristic, whereby the contact plate (e.g., power semiconductor die plate, disk controllers, and lead) than the non-contact portion MLF substrate (e.g., permanent connection bars) thick.

本发明的再一个方面在于提供一种制造包括功率半导体单元片和多个无源元件的引线框封装的方法。 A further aspect of the invention is to provide a method of manufacturing a power semiconductor die comprising a plurality of passive components and a lead frame package. 在一种实施方案中,MLF基片从单片材料冲压出。 In one embodiment, MLF substrate stamped out from a single sheet of material. 可选地,可以通过刻蚀或激光制造方法形成MLF基片。 Alternatively, MLF substrate may be formed by etching or laser manufacturing method. 模制料应用到MLF基片上以支撑半导体单元片和终端盘。 A molding material is applied to the MLF substrate for supporting the semiconductor die and the terminal plate. 优选地,在半导体元件安装到MLF基片上之前去除临时连接条。 Preferably, in the semiconductor element mounted on the MLF substrate prior to removing the temporary connection bars. 在另一种实施方案中,在半导体元件安装到MLF基片上之后去除临时连接条。 In another embodiment, the semiconductor element mounted on the MLF substrate after removing the temporary connection bars. 半导体元件通过表面安装技术安装到MLF基片上。 Surface mount technology semiconductor element mounted on the MLF substrate.

本发明的另一个方面在于使用上述MLF基片制造引线框封装,包括步骤:在MLF基片上应用模制料以便为终端盘、半导体单元片盘、临时连接条和永久连接条提供支撑。 Another aspect of the present invention is manufactured using the MLF substrate leadframe package, comprising steps of: using a molding material so as to provide support for the end plate, a semiconductor die plate, temporary and permanent connection bars connecting bar on the MLF substrate. 一旦已应用模制料,可以去除临时连接条。 Once you have applied the molding material can be removed temporarily connecting strip. 每个功率半导体单元片安装到半导体单元片盘上,并且跨越特定终端盘安装无源元件。 Each power semiconductor die to the semiconductor die mounting plate, mounting plate and across a specific terminal passive element. 在安装好半导体元件并且终端盘和半导体单元片焊接到引线上之后,模制料应用到MLF基片上以封装半导体元件和焊线。 After installing the semiconductor element and the terminal plate and the semiconductor element chip is soldered to the lead, the molding material is applied to the MLF substrate to encapsulate the semiconductor element and bonding wires.

附图说明 Brief Description

图1A-1B说明根据现有技术的常规引线框;图2是根据本发明的MLF基片的一种实施方案的平面图;图3是图2中所示的MLF基片的部分平面图;图4是图2中所示的MLF基片的部分平面图,其说明应用到MLF基片上的模制料;图5是图4中所示的MLF基片的平面图,其说明在已去除临时连接条之后的MLF基片;图6是图5中所示的MLF基片的平面图,其说明安装在MLF基片上的几个分立无源元件;图7是包含MLF基片的引线框封装的一种实施方案的平面图;图8A-8C说明根据本发明的MLF基片的第二实施方案;以及图9A-9B说明根据本发明的MLF基片的第三实施方案。 Figure 1A-1B illustrate a conventional lead frame according to the prior art; FIG. 2 is a plan view according to one embodiment of the MLF substrate of the present invention; FIG. 3 is a partial plan view of the MLF substrate shown in Fig. 2; Fig. 4 is a partial plan view of the MLF substrate shown in FIG. 2, illustrating the molding material is applied to the MLF substrate; Figure 5 is a plan view of the MLF substrate shown in Figure 4, illustrating the temporary connection after the article has been removed The MLF substrate; FIG. 6 is a plan view of the MLF substrate shown in Figure 5, illustrating several discrete passive components mounted on the MLF substrate; FIG. 7 is a MLF substrate comprising a lead frame package embodiment a plan view of the program; Fig. 8A-8C according to a second embodiment of the MLF substrate of the present invention; and Figure 9A-9B illustrate a third embodiment of the MLF substrate of the present invention.

具体实施方式 DETAILED DESCRIPTION

现在将参考图2-9描述本发明的几种实施方案。 2-9 will now be described with reference to FIG. Several embodiments of the present invention. 总的来说,本发明提供一种允许在同一封装中安装功率半导体元件以及无源元件的MLF基片。 Generally, the present invention provides a method that allows MLF substrate mounting a power semiconductor element and a passive element in the same package. 本发明可以应用于但不局限于,在需要多个或单个硅单元片与单个或多个无源元件组合的封装中提供最佳热性能。 The present invention can be applied but not limited to, the need to provide the best thermal performance in multiple or single silicon die with a single or a plurality of passive elements combined package. 通过在封装中布置外部元件,本发明可以代替需要外部无源的现有微引线框产品,从而减小空间和成本。 By arranging external components in the package, the present invention can replace the need for external passive micro leadframe conventional products, thereby reducing the space and cost.

图2说明根据本发明一种实施方案的引线框模板100。 Figure 2 illustrates the lead frame template scheme according to one embodiment of the present invention 100. 引线框模板100优选地由单片导热和导电材料101制成。 Lead frame template 100 is preferably made of a monolithic thermally and electrically conductive material 101. 铜(Cu)、Cu基合金、铁-镍(Fe-Ni)、Fe-Ni基合金等优选地用作引线框模板材料101。 Copper (Cu), Cu-based alloys, iron - nickel (Fe-Ni), Fe-Ni based alloy is preferably used as the lead frame template material 101. 引线框模板100包含其他材料处于本发明的范围和本质之内。 Lead frame template 100 include other materials are within the scope and nature of the present invention. 单片材料101优选地具有适合于焊接或施加其他导电和导热粘附材料(例如,导电环氧树脂)的表面材料抛光。 101 preferably has a single piece of material suitable for welding or applying other electrically and thermally conductive adhesive material (e.g., conductive epoxy) polishing the surface of the material.

在该实施方案中,四个MLF基片102已在单片材料101中形成。 In this embodiment, four MLF substrate 102 has formed in the single sheet of material 101. 引线框模板100可以包括多于或少于四个MLF基片102。 Lead frame template 100 may include more or fewer than four MLF substrate 102. 仅作为例子,可以通过冲压、刻蚀、研磨或激光制造方法形成每个MLF基片102。 Of example only, each MLF substrate 102 may be formed by stamping, etching, milling or laser manufacturing method. 每个MLF基片102优选地通过多个临时连接条104连上单片材料101。 Each MLF substrate 102 preferably by a plurality of temporary connection bars 101 on the single sheet of material 104 is connected. 临时连接条104将MLF基片102紧固于关于单片材料101的适当位置。 Temporary connection bar 104 is fastened to the MLF substrate 102 place on the single sheet of material 101. 如随后将描述的,临时连接条104最后从每个MLF基片102中去除,而不打算用来提供最终封装中的半导体元件之间的电连接。 As will be described later, the temporary connection bars 104 and finally removed from each MLF substrate 102, and does not intend to provide the final package is electrically connected between the semiconductor element.

每个MLF基片102的配置可以改变。 Configure each MLF substrate 102 may be changed. 将安装到MLF基片102上的半导体元件的个数由半导体封装的设计要求规定。 The semiconductor element mounted on the MLF substrate 102 by the number of semiconductor package design requirements specified. 图2说明MLF基片102的一种实施方案。 Figure 2 illustrates one embodiment of the MLF substrate 102. 在该实施方案中,MLF基片102包括半导体单元片盘106a,106b,106c、终端盘108、临时连接条104,以及永久连接条110。 In this embodiment, MLF substrate 102 includes a semiconductor die plate 106a, 106b, 106c, the terminal plate 108, the temporary connection bars 104, and a permanent connection bar 110. 图2中所示的终端盘108形状基本上为矩形。 Shown in Figure 2 the terminal plate 108 is substantially rectangular in shape. 终端盘108包括其他形状例如但不局限于椭圆形、正方形或圆形处于本发明的范围和本质内。 Terminal plate 108 includes other shapes such as, but not limited to, oval, square or round are within the scope and nature of the present invention.

一般地,每个MLF基片102的设计或布局可以预先确定,以满足半导体封装的特定电气要求。 Typically, each MLF substrate 102 design or layout may be predetermined to meet specific electrical requirements of the semiconductor package. 例如,如果每个MLF基片102从材料片101冲压出,那么可以配置冲压模以形成半导体封装所需的准确数目的半导体单元片盘106和终端盘108。 For example, if each MLF substrate 102 punched out from the material sheet 101, then the punching die can be configured to form a desired semiconductor package exact number of semiconductor die plate 106 and terminal plate 108. 在每个MLF基片102之间留下一条材料101,使得多个MLF基片102可以单片转移。 Leave a material 101 between each MLF substrate 102, such that a plurality MLF monolithic substrate 102 may shift.

终端盘108在MLF基片102中形成图案或矩阵。 Terminal plate 108 is formed in a pattern or matrix MLF substrate 102. 如上面所讨论的,终端盘108的图案或矩阵可以很大程度地改变。 As discussed above, the terminal plate 108 can change the pattern or matrix largely. 终端盘108一般地提供两个功能:(1)提供无源元件(例如,图6中所示的电阻器R1,R2,R3,R4)的安装表面;以及(2)提供焊线240的安装表面。 Terminal plate 108 generally provides two functions: (1) providing a passive element (e.g., FIG resistor R1 as shown in 6, R2, R3, R4) of the mounting surface; and (2) providing a bonding wire 240 is installed surface. 不管图案如何,终端盘108通过至少一个临时连接条104和/或至少一个永久连接条110链接到一起。 Regardless of how the pattern, the terminal plate 108 through the at least one temporary connection bar 104 and / or at least one permanent connection bar 110 links together. 终端盘108可以通过多个临时连接条104和/或多个永久连接条110链接到相邻终端盘108。 Terminal plate 108 by a plurality of temporary connection bars 104 and / or a plurality of permanent connection bar 110 links to the adjacent terminal plate 108. 开始时,临时连接条104和永久连接条110为MLF基片102提供刚性。 Initially, a temporary connection section 104 and section 110 MLF permanent connection substrate 102 provides rigidity.

图3更详细地说明终端盘108之间的连接。 Diagram illustrates the connection between the terminal plate 108 in more detail 3. 一般地,相邻终端盘108可以用两种方式的一种链接到一起:(1)相邻终端盘108通过临时连接条104链接(例如,终端盘108a和108g);或者(2)相邻终端盘108通过永久连接条110链接(例如,终端盘108g和108h)。 Generally, the adjacent terminal plate 108 may be a link together two ways: (1) adjacent to the terminal plate 108 by a temporary connection bar 104 links (e.g., terminal plate 108a and 108g); or (2) adjacent to end plate 108 is permanently connected by links section 110 (for example, a terminal plate 108g and 108h). 可以从终端盘108延伸出多个临时连接条104和/或永久连接条110。 Terminal plate 108 may extend from a plurality of temporary connection bars 104 and / or permanent connection bar 110.

图3中所示的MLF基片102的部分包括十二个终端盘108a-108l。 Part of Figure 3 MLF substrate 102 shown comprises twelve termination panel 108a-108l. 现在将描述几个终端盘108之间的连接,以便提供终端盘108如何可以链接到一起的例子。 108 will now be described the connection between several terminals disc, in order to provide an example of how the terminal plate 108 can be linked together. 终端盘108a具有从其延伸出的四个临时连接条104和一个永久连接条110。 Terminal plate 108a has extending therefrom four temporary connection bars 104 and one permanent connection bar 110. 一个临时连接条104将终端盘108a与终端盘108b链接。 A temporary connection section 104 of the terminal plate 108a and 108b link terminal plate. 第二个临时连接条104将终端盘108a链接到终端盘108g。 The second section 104 temporary connection terminal plate 108a link to the terminal plate 108g. 第三和第四个临时连接条104将终端盘108a链接到与终端盘108a相邻的永久连接条110。 The third and fourth temporary connection bar 104 links the termination panel 108a adjacent to the terminal plate 108a of the permanent connection bars 110. 永久连接条110将终端盘108a与终端盘108i链接。 Article 110 is permanently connected to the terminal and the terminal disc tray 108a 108i link. 四个临时连接条104将终端盘108a固定在关于MLF基片102周围元件(例如,终端盘108b,108g)的适当位置,并建立这些元件之间的电连接。 Four temporary connection bars 104 terminal plate 108a is fixed in position on the MLF substrate 102 surrounding components (e.g., the terminal plate 108b, 108g), and to establish an electrical connection between these elements.

终端盘108f说明可以用更少的连接条链接终端盘108。 Terminal plate 108f described with fewer links connecting strip terminal plate 108. 终端盘108f通过永久连接条110链接到终端盘108e,并通过临时连接条104链接到终端盘108l。 Terminal plate 108f permanently connected by a link to the terminal strip 110 plate 108e, and a link to the terminal plate through a temporary connection section 104 108l. 永久连接条110和临时连接条104将终端盘108e固定在适当位置。 Permanent connection bars and temporary connection 110 to the terminal plate 108e strip 104 is fixed in place. 一般地,相邻终端盘108通过单个连接条连接到一起。 Generally, the adjacent terminal plate 108 is connected together by a single strap. 通过多个连接条将相邻终端盘链接到一起处于本发明的范围和本质内。 Through a plurality of connecting terminal strips adjacent link plate to be within the scope and nature of the present invention together.

相邻终端盘108可以通过全是临时连接条104或全是永久连接条110链接到一起。 Adjacent terminal plate 108 may be a temporary connection via a full bar is permanently connected to 104 or Article 110 full link together. 例如,终端盘108l通过四个临时连接条104链接到相邻终端盘。 For example, the terminal plate 108l through four temporary connection bar 104 links to the adjacent end plate. 可选地,终端盘108e仅通过永久连接条110链接到相邻终端盘。 Alternatively, the terminal plate 108e only by permanent connection bar 110 links to the adjacent end plate. 每个临时连接条104显示为具有与永久连接条110不同的性状,这只是为了说明哪些连接条是临时的以及哪些连接条是永久的。 Each temporary connection bar 104 is shown as having a permanent connection bar 110 different characters, just to illustrate what is temporary connection bars connecting bar and which is permanent. 临时和永久连接条104,110具有相同性状或具有与图3所示不同的性状处于本发明的本质和范围内。 Temporary and permanent connection with the same trait or 104,110 pieces have different traits within Figure 3 is the nature and scope of the invention.

图4说明应用到MLF基片102上的模制料(molding compound)112。 Figure 4 illustrates the application to a molding material for (molding compound) MLF 112 on the substrate 102. 模制料112将MLF基片102内的每个元件(例如,终端盘108、半导体单元片盘106,以及连接条104,110)固定到模制料112中。 A molding material 112 of each element within the MLF substrate 102 (e.g., a terminal plate 108, a semiconductor die plate 106, and a connecting bar 104, 110) secured to the molding material 112. 在优选实施方案中,模制料112填充到MLF基片102各处的空白空间或间隙中。 In a preferred embodiment, the molding material 112 is filled into an empty space or gap around the MLF substrate 102 in. MLF基片102中的间隙由MLF基片102中没有布置半导体单元片盘106、终端盘108或连接条104、110的区域定义。 MLF substrate 102 in the gap created by the MLF substrate 102 is not arranged in a semiconductor die plate 106, a terminal plate 108 or the area definition 104, 110 of the connecting bar. 模制料112为MLF基片102提供永久连接条110和临时连接条104之外的额外刚性。 A molding material 112 MLF substrate 102 to provide additional rigidity permanent connection bars and temporary connection bars 110 to 104 outside. 模制料112优选地是环氧树脂或其他电绝缘材料。 A molding material 112 is preferably an epoxy resin or other electrically insulating material.

当应用到MLF基片102上时,模制料112优选地不覆盖半导体单元片盘106或终端盘的顶面或底面,因为它们提供半导体单元片和无源元件的安装表面。 When applied to the MLF substrate 102, the molding material 112 preferably does not cover the top or bottom surface of the semiconductor die plate or end plate 106, because they provide the mounting surface of the semiconductor die and passive components. 因此,模制料112优选地比材料片101薄。 Thus, the molding material 112 is preferably thinner than the material sheet 101. 如果模制料112最初覆盖半导体单元片盘106或终端盘108,那么可以研磨或腐蚀盘的表面以去除模制料112。 If the molding material initially covering the semiconductor unit 112 106 sheet tray or terminal plate 108, then you can ground or surface corrosion disc to remove the molding material 112. 在优选实施方案中,临时连接条104和永久连接条110也不被模制料112覆盖。 In a preferred embodiment, the temporary connection bars 104 and 110 are not permanently connected strip material 112 is molded cover. 但是,用模制料112覆盖临时和永久连接条104、110处于本发明的本质和范围内。 However, with the molding material covering 112 temporary and permanent connection bars 104, 110 are within the spirit and scope of the invention.

图5说明优选地在已应用模制料112之后从MLF基片102中去除临时连接条104。 After 5 illustrates preferably applied in the molding material 112 has been removed from the temporary connection bars 104 MLF substrate 102. 这样地,MLF基片102的元件(例如,终端盘108、连接条110,以及半导体单元片盘106)主要通过模制料112保持在适当位置。 Thus, the element MLF substrate 102 (e.g., a terminal plate 108, a connecting bar 110, and semiconductor die plate 106) mainly by molding material 112 is held in place. 如图5中所示,如果链接的话,终端盘108仅通过永久连接条110链接到相邻终端盘108。 Shown in Figure 5, if the link, then, the terminal plate 108 by only a permanent connection bar 110 links to the adjacent terminal plate 108. 其余的永久连接条110提供链接的终端盘108之间的电连接。 The remaining permanent link connecting bar 110 is electrically connected to the terminal plate 108 between. 例如,当MLF基片102最初形成时,终端盘108a最初具有从其延伸出四个临时连接条104和一个永久连接条110(参见图2-3)。 For example, when the MLF substrate 102 is initially formed, originally having a terminal plate 108a extending therefrom four temporary connection bars 104 and one permanent connection bar 110 (see Figure 2-3). 一旦去除临时连接条104,终端盘108a仅通过单个永久连接条110链接到终端盘108i。 Once the removal of a temporary connection section 104, only a single terminal plate 108a Article 110 is permanently connected to the terminal plate 108i via links.

临时连接条104可以在制造过程的后期去除。 Temporary connection bars 104 may be removed at a later stage of the manufacturing process. 临时连接条104仅必须在封装的电测试之前去除。 Only temporary connection bar 104 must be removed prior to packaging of electrical testing. 否则,临时连接条104将提供终端盘108之间不需要的电连接。 Otherwise, the temporary connection bars 104 provide unwanted between terminal plate 108 is electrically connected. 在可选实施方案中,在半导体元件安装到MLF基片102上之后,临时连接条104通过后刻蚀方法去除(随后讨论)。 After the alternative embodiment, the semiconductor element mounted on the MLF substrate 102, the temporary connection bars 104 after removing by etching method (discussed later).

优选地由环氧树脂、聚酰胺树脂、聚酯树脂等制成的粘合带(没有显示)可以贴附到MLF基片102的底表面上,以进一步使MLF基片102稳固。 Preferably the adhesive tape by an epoxy resin, a polyamide resin, a polyester resin or the like formed (not shown) may be attached to the bottom surface of the MLF substrate 102 to further MLF substrate 102 firmly. 粘合带是本领域技术人员已知的,因此不需要进一步公开。 The adhesive tape is known to the skilled person, thus, no further disclosure. 如果粘合带应用于MLF基片102上,优选地在将半导体元件安装到MLF基片102之前将它应用到MLF基片102上。 If the adhesive tape on the substrate is applied to MLF 102, preferably before the semiconductor element is mounted MLF substrate 102 to apply it to the MLF substrate 102.

在粘合带应用到MLF基片102的底面上(参见图8B)之后,半导体元件安装到MLF基片102的顶面上(参见图8B)。 After the adhesive tape was applied to the bottom surface of the MLF substrate 102 (see FIG. 8B), a semiconductor element is mounted onto the top surface of the MLF substrate 102 (see FIG. 8B). 本领域中已知有许多方法用于在封装中安装半导体元件。 There are many known in the art methods for mounting a semiconductor element in a package. 仅作为例子,MLF基片102可以按照与待安装到终端盘108上的无源元件的图案相对应的图案丝网印刷上焊锡膏。 Of example only, MLF substrate 102 may be mounted on the solder paste in accordance with the terminal plate 108 to the passive element pattern on the pattern corresponding screen printing. 然后,每个无源元件放置到相应的一对终端盘108上,并且使用常规表面安装技术回流焊锡。 Then, each of the passive components are placed on the respective pair of terminal plate 108, and using conventional surface mount technology reflow. 可选地,无源元件的安装表面可以印刷上焊锡膏,然后安装到一对终端盘108上。 Alternatively, the mounting surface of the passive elements can be printed on the solder paste, and then mounted on a terminal plate 108. 用于安装半导体元件的其他方法在本领域中是已知的,因此不需要进一步公开。 Other methods for mounting a semiconductor element are known in the art, and thus, no further disclosure.

图6说明无源元件布置在几个终端盘108之间的MLF基片102的一种实施方案。 6 illustrates a passive element is arranged between several terminal plate 108 MLF substrate 102 of an embodiment. 在该实施方案中,电阻器R1,R2,R3,R4布置在几个终端盘108之间。 In this embodiment, the resistors R1, R2, R3, R4 arranged in the disc 108 between the several terminals. 每个电阻器通过其引线电连接到终端盘108上。 Each resistor is connected to the terminal plate 108 through which the leads electrically. 例如,电阻器R1通过其引线E1连接到终端盘108a,并通过其引线E2连接到终端盘108g。 For example, the resistor R1 is connected by its lead E1 to the termination panel 108a, and connected to the terminal plate 108g by its lead E2. 类似地,电阻器R2通过其引线E1连接到终端盘108h,并通过其引线E2连接到终端盘108i。 Similarly, resistor R2 is connected via its lead E1 to the termination panel 108h, and 108i connected to the terminal plate through which the lead E2.

如先前所讨论的,终端盘108a和108i以及终端盘108g和108h每个都通过永久连接条110电连接到一起。 As previously discussed, the terminal plate 108a and 108i, and a terminal plate 108g and 108h are each coupled together permanently by electrically connecting bar 110. 电阻器R1将终端盘108a和108g电连接到一起。 Resistor R1 to the terminal plate 108a and 108g are electrically connected together. 电阻器R2将终端盘108h和108i电连接到一起。 Resistor R2 to terminal plate 108h and 108i are electrically connected together. 电阻器R1和R2因此电连接到一起。 Resistors R1 and R2 thus electrically connected together. 电阻器R3和R4类似地电连接到一起。 Resistors R3 and R4 is similarly electrically connected together.

在该实施方案中,无源元件不安装到终端盘108b,108c,108f,108l上。 In this embodiment, the passive element is not mounted on the terminal plate 108b, 108c, 108f, 108l. 这样,终端盘108b,108c,108f,108l提供焊线的安装表面。 Thus, the terminal plate 108b, 108c, 108f, 108l provide mounting surface weld lines. 焊线240如金线使用常规焊接方法连接在每个终端盘108b,108c,108f和108l跟半导体封装200的外部引线232(参见图7)之间。 Such as gold wire bonding wires 240 using a conventional welding method of each terminal plate is connected to 108b, 108c, 108f and 108l with the external lead 232 of the semiconductor 200 (see FIG. 7) between the package.

每个半导体单元片盘106适合于接收功率半导体单元片210(例如,MOSFET)或控制器器件212(例如,PWM控制器、控制器ASIC等)。 Each of the semiconductor die plate 106 is adapted to receive a power semiconductor die 210 (e.g., MOSFET) or controller device 212 (e.g., PWM controller, ASIC, etc.). 功率半导体单元片210和控制器器件212可以在无源元件(例如,R1-R4)安装到MLF基片102之前或之后安装到每个半导体单元片盘106上。 Power semiconductor die 210 and the controller device 212 may MLF substrate 102 before or after each of the semiconductor unit is mounted on the film spool 106 is mounted to the passive components (e.g., R1-R4). 如图7中所示,MLF基片102包括两个功率半导体单元片210,一个安装在半导体单元片盘106b上,而一个安装在半导体单元片盘106c上。 Shown in Figure 7, MLF substrate 102 includes two power semiconductor die 210, a semiconductor die mounted on the plate 106b, and a semiconductor die mounted on the plate 106c. 控制器器件212安装在半导体单元片盘106a上。 The controller device 212 is mounted on the semiconductor die plate 106a. 每个功率半导体单元片210包括焊接盘(没有显示)。 Each power semiconductor chip unit 210 includes a pad (not shown). 焊线240将功率半导体单元片210的焊接盘电连接到引线框230的引线232。 Bonding wires 240 bonding pads of the power semiconductor die 210 is electrically connected to the lead frame 230 of the lead 232. 图7中所示的实施方案只是说明性的。 Embodiment shown in FIG. 7 is illustrative only. 半导体封装200的配置可以根据封装的性能要求而改变。 Semiconductor package 200 may be configured in accordance with the performance requirements of the package is changed.

在无源元件、功率半导体单元片210和控制器器件212安装到MLF基片102上以及焊接完成之后,MLF基片102的顶面用模制料密封。 In the passive elements, the power semiconductor die 210 and the controller device 212 is mounted to the MLF substrate 102 and after welding is completed, the top surface of the MLF substrate 102 is molded with a sealing material. 在模制料固化之后,粘合带从MLF基片102的底面去除。 After the molding material cured, the adhesive tape is removed from the bottom surface of the MLF substrate 102.

如先前所讨论的,临时连接条104不一定要在模制料112应用到MLF基片102之后马上从MLF基片102中去除。 Immediately removed from the MLF substrate 102. As previously discussed, after the temporary connection bars 104 may not be applied to the MLF substrate 102 in the molding material 112. 在上面所讨论的所有制造步骤中临时连接条104可以保留在MLF基片102中。 In all the manufacturing steps as discussed above connecting bar 104 may be temporarily retained in the MLF substrate 102. 在可选实施方案中,在粘合带从MLF基片102去除之后去除临时连接条104。 In an alternative embodiment, the adhesive tape strip 104 is removed from the temporary connection after the MLF substrate 102 is removed. 在去除粘合带之后执行后刻蚀过程,以便从MLF基片102去除临时连接条104。 After the etching process is performed after removal of the adhesive tape, in order to remove the temporary connection bar 104 from the MLF substrate 102. 后刻蚀过程去除临时连接条104的地方在模制料112中形成孔洞。 After the etching process of removing the temporary connection bars 104 where holes are formed in the molding material 112. 优选地,通过将另外的模制料应用到MLF基片102的背面来填充孔洞。 Preferably, the back of the molding material additionally applied to the MLF substrate 102 to fill the holes.

图7说明包含MLF基片102的引线框封装200。 7 illustrates the lead frame 102 comprising MLF substrate package 200. 引线框封装200包括在其周边附近具有引线232的外壳230。 Leadframe package 200 includes a housing 232 having a lead in 230 near the periphery thereof. 材料片101最后分成单个单元,每个单元包括单个MLF基片102。 The last piece of material 101 into individual units, each comprising a single MLF substrate 102. 该方法在行业内通常称作单体化。 This method is commonly referred to in the industry of the monomer. 然后每个单元安装到外壳230上。 Each unit is then mounted to the housing 230. 引线框封装200优选地以这样的方式封装到封装体中,即每个引线232的底面至少有一部分从封装体的底部暴露,以便形成外部电连接。 Leadframe package 200 is preferably packaged in such a manner to the package body, i.e., the bottom surface 232 of each lead at least a portion exposed from the bottom of the package, so as to form an external electrical connection. 模制料已被去除,以便说明引线框封装200的内部。 A molding material has been removed to illustrate the interior 200 of the lead frame packages.

图7中所示的引线框封装200包括两个功率半导体单元片210。 FIG leadframe package 7 shown 200 comprises two power semiconductor die 210. 每个半导体单元片210可以用粘结剂如银膏贴附到半导体单元片盘106上,银膏在单元片贴附之后固化。 Each of the semiconductor die 210 may be attached with an adhesive such as silver paste on the semiconductor die plate 106, the silver paste after curing die attached. 每个半导体单元片210的有效表面包括多个焊接盘(没有显示)。 Each of the semiconductor die active surface 210 comprises a plurality of bonding pads (not shown). 每个焊接盘通过焊线240电连接到引线232。 Each weld plate connected to the lead 232 through 240 electrical wire bonding. 其上没有安装无源元件的终端盘108为焊线240提供安装表面。 It is not installed on the terminal plate 108 passive components to provide a mounting surface for bonding wire 240. 几个终端盘108显示为通过焊线240电连接到引线232。 Several terminal plate 108 shown connected to a lead 232 by bonding wires 240 electrically. 图7中所示的引线框封装200的配置可以改变,而不打算用来限制本发明的范围。 The lead frame shown in FIG. 7 of the package configuration 200 may vary, and are not intended to limit the scope of the invention. 封装200包括功率半导体元件和无源元件,然后可以安装到客户电路板上。 Package 200 includes a power semiconductor element and the passive element can then be mounted to the customer's board.

图8A-8C说明MLF基片的另一种实施方案。 Figure 8A-8C illustrate MLF substrate another embodiment. 在该实施方案中,MLF基片302直接安装到客户电路板上。 In this embodiment, MLF substrate 302 is mounted directly to the customer's board. MLF基片302的配置基本上类似于先前在图2-6中所示的MLF基片102。 Configuring MLF substrate 302 is substantially similar to previously MLF substrate 102 shown in Figure 2-6. 类似于MLF基片102的MLF基片302中的元件(例如,终端盘108、永久连接条110等)保持相同的参考数字。 Similar to the MLF substrate MLF substrate 302 of the element 102 (e.g., a terminal plate 108, a permanent connection bars 110, etc.) remain the same reference numerals.

类似于MLF基片102,MLF基片302包括来自材料片301的单体结构。 Similar to the MLF substrate 102, MLF substrate 302 includes a structure derived from a monomer material sheet 301. 不管制造过程如何,图8A中所示的每个MLF基片302包括将MLF基片302连接到单片材料301的外框架304(参见图9A)。 Regardless of how the manufacturing process, each MLF substrate 302 shown in Figure 8A includes the MLF substrate 302 is connected to the outer frame 301 of the single piece of material 304 (see FIG. 9A). 外框架304包括永久引线303和临时引线305。 Outer frame 304 includes permanent and temporary lead wire 303 305. 临时引线305固定MLF基片302,并且类似于临时连接条104最后在MLF基片302进行电测试之前从MLF基片302去除。 Temporary lead 305 MLF substrate 302 is fixed, and a temporary connection bar 104 similar to the previous MLF substrate 302 at final electrical tests of the substrate 302 is removed from the MLF. 临时连接条104和临时引线305可以同时或者在制造过程的不同阶段去除。 Temporary connection bars 104 and the temporary lead wire 305 can be removed simultaneously or at different stages of the manufacturing process. 如图8A和8C中所示,半导体单元片210和终端盘108经由至少一个焊线240直接电连接到永久引线303。 As shown in Fig. 8A and 8C, the semiconductor die 210 and the terminal plate 108 via at least one bonding wire 240 is electrically connected directly to the permanent leads 303.

从MLF基片302去除临时引线305实际上将MLF基片302转变成无引线封装(参见图8C)。 Removing the temporary lead wire 302 from the MLF substrate 305 will actually change MLF substrate 302 into a leadless package (see FIG. 8C). MLF基片302因此可以直接安装到客户电路板上。 MLF substrate 302 can be mounted directly to the customer on the board. 如先前所讨论的,模制料112填充到MLF基片的间隙中,并且不覆盖半导体单元片盘106的底面或终端盘108的底面。 As previously discussed, the molding material 112 is filled into the gap in MLF substrate, and does not cover the bottom surface of the bottom surface of the semiconductor disk or the terminal unit 106 of the spool 108. 在该实施方案中,MLF基片302具有基本上均匀的厚度,如图8B中h所示。 In this embodiment, MLF substrate 302 has a substantially uniform thickness, 8B in h as shown in Fig. 这样地,MLF基片302的整个底面310接触电路板。 This way, MLF entire bottom surface 310 of the substrate contact circuit board 302. MLF基片302的一个优点在于从每个功率半导体单元片210散发出的热量通过半导体单元片盘106直接从其底面转移到客户电路板上,提供低的热阻抗。 One advantage is that the MLF substrate 302 from each of the power semiconductor die 210 the heat emitted by a semiconductor die plate 106 is transferred to the customer directly from the bottom surface of the circuit board, to provide a low thermal impedance. 但是,缺点在于MLF基片302的不导电部分(例如,模制料112)也接触电路板。 However, a drawback in that the non-conductive portion of the MLF substrate 302 (e.g., the molding material 112) also contact the circuit board. 行业内的常规实践是跟踪沿着电路板顶面的轨道或轨迹,在该实施方案中电路板位于MLF基片302下面。 Conventional practice in the industry is to track along the track or tracks of the top surface of the circuit board, in this embodiment, the circuit board is located MLF substrate 302 below. MLF基片302的整个底面310接触电路板,当MLF基片安装到电路板上并且MLF基片302的底面310和电路板的顶面之间没有空间时,客户不能跟踪沿着电路板顶面的轨迹。 MLF substrate 310 contacts the entire bottom surface of the circuit board 302, when the MLF substrate is mounted on a circuit board and there is no space between the top surface of the bottom surface of the MLF substrate 302 and the circuit board 310, the customer can not track along the top surface of the circuit board trajectory.

图9A-9B说明MLF基片302的又一种实施方案。 Figure 9A-9B illustrate MLF substrate 302 of a further embodiment. 在该实施方案中,MLF基片310的底面310具有台阶特性,以便允许客户跟踪沿着电路板顶面的轨迹。 In this embodiment, the bottom surface 310 of the MLF substrate 310 has a step characteristic, to allow customers to track along the top surface of the circuit board tracks. 图9A说明在单片材料301中形成的四个MLF基片302。 Figure 9A illustrates four MLF substrate 301 is formed in the single sheet of material 302. 引线框模板300可以包括多于或少于四个MLF基片302。 Lead frame template 300 may include more or fewer than four MLF substrate 302. 仅作为例子,可以通过冲压、刻蚀、研磨或激光制造过程来形成每个MLF基片302。 Of example only, by stamping, etching, milling or laser manufacturing process to form each of the MLF substrate 302.

不管制造过程如何,图9A中所示的每个MLF基片302通过永久引线303和临时引线305连接到单片材料301。 Regardless of how the manufacturing process, each MLF substrate 302 shown in FIG. 9A through permanent and temporary lead wire 303 is connected to the single sheet of material 305 301. 与图8A-8C中所示的MLF基片302不同,图9B中所示的MLF基片在底部或接触面312上具有台阶特性。 FIG MLF substrate 302 shown in 8A-8C different, MLF substrate shown in FIG 9B has a step or a feature on the bottom contact surface 312. 在该实施方案中,当MLF基片302安装到电路板上时仅需要操作封装的盘(例如,永久引线303和半导体单元片盘106)接触电路板。 In this embodiment, when the MLF substrate 302 is mounted to the circuit board only need to operate the disc package (e.g., permanent leads 303 and semiconductor die plate 106) contact the circuit board. 优选地,当MLF基片302最初形成时形成MLF基片302的台阶特性。 Preferably, the step characteristics MLF substrate 302 is formed when the MLF substrate 302 is initially formed. 如图9B中所示,MLF基片302的底面312为半导体单元片盘106提供比模制料112延伸出更多的永久引线303。 As shown in Figure 9B, the bottom surface 302 of the MLF substrate 312 of the semiconductor die plate 106 provide molding material 112 extending over the lead 303 is more permanent. 当MLF基片302安装到电路板上时,在引线303之间形成间隙314,从而可以在其间跟踪轨迹。 When the MLF substrate 302 is mounted to the circuit board 303 is formed a gap between the lead 314, which can track the trajectory therebetween. 间隙314还提供清洗电路板的优点。 Advantages to clean the board 314 also provides clearance. 例如,MLF基片302的凸起底面允许用标准清洗设备清洗电路板,同时使MLF基片302下方的集水、溢出等的可能性达到最小,否则将导致电迁移等。 For example, MLF convex underside of the substrate 302 allows a standard cleaning equipment to clean the board, while the possibility of MLF substrate 302 below the catchment, overflow to a minimum, otherwise it will lead to electromigration.

本发明的一个方面提供一种引线框基片,包括:多个连接条;适合于接收半导体单元片的半导体单元片盘;通过所述多个连接条链接到一起并链接到所述半导体单元片盘的多个终端盘,所述多个终端盘的每个适合于接收无源元件和焊线;以及将所述半导体单元片盘、所述多个终端盘,以及所述多个连接条固定在一起的模制料。 One aspect of the invention there is provided a lead frame substrate, comprising: a plurality of connection bars; adapted to receive a semiconductor die in a semiconductor die plate; link via the plurality of connection bars together and linked to the semiconductor die plates of the plurality of terminals, each of said plurality of terminals adapted to receive the disc passive components and bonding wires; and the semiconductor die plate, said plurality of terminal plate, and said plurality of connecting bar fixed together molding material.

本发明的另一个方面提供一种引线框封装,包括:具有中心部分的外壳和位于所述外壳周边附近的多个引线;以及安装到所述中心部分上的引线框基片,所述引线框基片电连接到所述多个引线的至少一个并包括:多个连接条;适合于接收半导体单元片的半导体单元片盘;多个终端盘,所述多个终端盘的每个适合于接收无源元件和焊线,所述多个终端盘通过所述多个连接条链接到一起并链接到所述半导体单元片盘;以及将所述半导体单元片盘、所述多个终端盘,以及所述多个连接条固定在一起的模制料。 Another aspect of the invention there is provided a lead frame package, comprising: a housing having a central portion and a plurality of leads located around the periphery of said housing; and a lead frame mounted to the substrate on said central portion, said lead frame substrate is electrically connected to at least one of said plurality of leads and comprising: a plurality of connecting bar; adapted to receive a semiconductor die in a semiconductor die plate; a plurality of terminal plate, each of said plurality of terminals adapted to receive the disc passive components and wire bonding, the plurality of terminals through said plurality of discs connecting bar linked together and linked to the semiconductor die plate; and said semiconductor die plate, said plurality of terminal plate, and said plurality of connection strips secured together molding material.

本发明的又一个方面提供一种引线框封装,包括:具有中心部分的外壳和位于所述外壳周边附近的多个引线;安装到所述中心部分上的引线框基片,所述引线框基片电连接到所述多个引线的至少一个并包括:多个半导体单元片盘,所述多个半导体单元片盘的每个适合于接收半导体单元片;多个终端盘,所述多个终端盘的每个适合于接收无源元件和焊线;将所述多个终端盘和所述半导体单元片盘链接到一起的多个连接条;以及应用到所述引线框基片上的模制料,所述模制料将所述多个半导体单元片盘、所述多个终端盘,以及所述多个连接条固定在一起。 Yet another aspect of the present invention to provide a lead frame package, comprising: a housing having a central portion and a plurality of leads located around the periphery of said housing; mounted to the lead frame substrate on said central portion, said lead frame base chip electrically connected to at least one of said plurality of leads and comprising: a plurality of semiconductor die plate, each of the semiconductor die of the plurality of semiconductor die are adapted to receive the disc; a plurality of terminal plate, said plurality of terminals Each tray adapted to receive a passive element and bonding wires; disc and the plurality of terminals of the semiconductor die plate link together a plurality of connection bars; and applied to the lead frame molded material on the substrate secured together, the molding material for the plurality of semiconductor die plate, said plurality of terminal plate, and said plurality of connection bars.

本发明的另一个方面提供一种安装到电路板上的引线框基片,包括:位于引线框基片周边附近的多个引线;多个连接条;多个半导体单元片盘,所述多个半导体单元片盘的每个适合于接收半导体单元片;多个终端盘,所述多个终端盘的每个适合于接收无源元件和焊线,所述多个终端盘通过所述多个连接条链接到一起并链接到所述多个半导体单元片盘;以及将所述多个半导体单元片盘、所述多个终端盘、所述多个连接条,以及所述多个引线固定在一起的模制料。 Another aspect of the present invention to provide a lead frame mounted to the circuit board substrate, comprising: a plurality of leads of the lead frame located near the periphery of the substrate; a plurality of connection bars; a plurality of semiconductor die plate, said plurality of Each of the semiconductor die plate adapted to receive a semiconductor die; a plurality of terminal plate, each of said plurality of terminals adapted to receive the disc passive components and the bonding wire, said plurality of terminals connected via said plurality of disks secured together and to said plurality of semiconductor die plate, said plurality of terminal plate, said plurality of connecting strips, and said plurality of leads; strips linked together and linked to said plurality of semiconductor die plate The molding material.

本发明的又一个方面提供一种引线框封装,包括:具有包括导电和不导电部分的顶面的电路板;以及安装到所述电路板的所述顶面上的引线框基片,包括:位于所述引线框基片周边附近的多个引线;多个连接条; Yet another aspect of the present invention to provide a lead frame package, comprising: a conductive and non-conductive portion including a top surface of the circuit board; and a circuit board mounted to the lead frame of the top surface of a substrate, comprising: a plurality of leads located on the lead frame around the periphery of the substrate; a plurality of connecting bar;

适合于接收半导体单元片的半导体单元片盘;多个终端盘,所述多个终端盘的每个适合于接收无源元件和焊线,所述多个终端盘通过所述多个连接条链接到一起并链接到所述半导体单元片盘;以及将所述半导体单元片盘、所述多个终端盘、所述多个连接条,以及所述多个引线固定在一起的模制料。 Adapted to receive a semiconductor die of a semiconductor die plate; a plurality of terminal plate, each of said plurality of terminals adapted to receive the disc passive components and wire bonding, the plurality of terminals through said plurality of discs connecting bar links together and linked to the semiconductor die plate; and said semiconductor die plate, said plurality of terminal plate, said plurality of connecting strips, and the plurality of lead molding material secured together.

本发明的另一个方面提供一种制造引线框基片的方法,引线框基片被配置以接收半导体单元片和分立无源元件,该方法包括步骤:(a)在导电材料片中形成引线框,引线框基片包括至少一个半导体单元片盘、多个终端盘,以及将半导体单元片盘和多个终端盘链接到一起的多个临时和永久连接条;(b)将模制料应用到所述步骤(a)中所形成的引线框基片上,模制料将半导体单元片盘、多个终端盘,以及多个临时和永久连接条固定在一起;以及(c)从引线框基片中去除多个临时连接条。 Another aspect of the present invention to provide a manufacturing method of a lead frame substrate, the lead frame substrate is configured to receive a semiconductor die, and discrete passive components, the method comprising the steps of: (a) a conductive material in the lead frame sheet is formed , the lead frame substrate including at least one semiconductor die plate, a plurality of terminal plate, and the semiconductor die plate and a plurality of terminal plate link together a plurality of temporary and permanent connection bars; (b) will be applied to the molding material said step of the lead frame substrate (a) formed in the molding material of the semiconductor die plate, a plurality of terminal plate, and a plurality of temporary and permanent connection bars fastened together; and (c) from the lead frame substrate the removal of a number of temporary connection bars.

本发明的又一个方面提供一种将半导体元件安装到引线框基片上的方法,包括步骤:(a)在导电材料片中形成多个引线框基片,多个引线框基片的每个包括通过多个临时连接条和多个永久连接条链接到一起的至少一个半导体单元片盘和多个终端盘;(b)将模制料应用到所述步骤(a)中所形成的多个引线框基片的每个上;(c)从每个引线框基片中去除多个临时连接条;(d)将粘合带应用到每个引线框基片的背面;(e)将分立无源元件安装到终端盘上;(f)将半导体单元片安装到每个半导体单元片盘上;(g)形成焊接连接;以及(h)在所述步骤(a)中所形成的每个引线框基片上应用封装材料,封装材料将所述步骤(e)中所安装的分立无源元件、所述步骤(f)中所安装的半导体单元片,以及所述步骤(g)中所形成的焊接连接封装。 Yet another aspect of the invention there is provided a method of mounting a semiconductor element a lead frame substrate, comprising the steps of: (a) a plurality of conductive sheet material forming the lead frame substrate, each of the plurality of lead frame substrates include a plurality of leads (b) the molding material is applied to said step (a) is formed; link through a plurality of temporary connection bars and a plurality of permanent connection bars together at least one semiconductor die plate and a plurality of terminal plate Each frame on the substrate; (c) removing the lead frame from each of the plurality of temporary connection bars substrate; (d) the adhesive tape is applied to the back of each lead frame substrate; (e) the discrete non- source element is mounted on the terminal plate; (f) the semiconductor die is mounted on each of the semiconductor die plate; (g) forming a solder connection; and (h) each lead in said step (a) formed in the Application of the frame substrate packaging material, packaging material discrete passive components said step (e) is installed, the semiconductor die said step (f) are installed, and said step (g) formed in the welded connection package.

本发明的另一个方面提供一种将半导体元件安装到引线框基片上的方法,包括步骤:(a)在材料片中形成多个引线框基片,多个引线框基片的每个包括至少一个半导体单元片盘和多个终端盘,半导体单元片盘和多个终端盘通过多个临时连接条和多个永久连接条链接到一起;(b)将模制料应用到所述步骤(a)中所形成的多个引线框基片的每个上;(c)将粘合带应用到每个引线框基片的背面;(d)将分立无源元件安装到终端盘上;(e)将半导体单元片安装到每个半导体单元片盘上;(f)形成焊接连接;(g)在所述步骤(a)中所形成的每个引线框基片上应用封装材料,封装材料将所述步骤(e)中所安装的分立无源元件、所述步骤(f)中所安装的半导体单元片,以及所述步骤(g)中所形成的焊接连接封装;(h)去除在所述步骤(c)中应用的粘合带;以及(i)对每个引线框基片的背面应用刻蚀处理,以便去除多个临时连接条。 Another aspect of the invention there is provided a method of mounting a semiconductor element a lead frame substrate, comprising the steps of: (a) a plurality of lead frames in the film material forming the substrate, each of the plurality of lead frame substrates includes at least a semiconductor die plate and a plurality of terminal plate, a semiconductor die plate and a plurality of terminals through a plurality of disks and a plurality of temporary connection bars permanently connected strips linked together; (b) the molding material is applied to said step (a a plurality of lead frames on each of the substrate) is formed; (c) the adhesive tape is applied to the back of each lead frame substrate; (d) the discrete passive components mounted on the terminal plate; (e ) a semiconductor die mounted to each of the semiconductor die plate; (f) forming a solder connection; (g) Application of the encapsulating material on each lead frame substrate in said step (a) is formed, the packaging material discrete passive components of said step (e) is installed, the semiconductor die of the welding step (f) are installed, and said step (g) formed in the package is connected; (h) removing said step (c) the application of the adhesive tape; and (i) application of an etching treatment on the back of each lead frame substrate to remove the plurality of temporary connection bars.

本发明的又一个方面提供一种制造引线框基片的方法,引线框基片被配置以接收半导体单元片和分立无源元件,该方法包括步骤:(a)在材料片中形成引线框基片,引线框基片包括至少一个半导体单元片盘、多个终端盘、将半导体单元片盘和多个终端盘链接到一起的多个临时和永久连接条,以及多个永久和临时引线;(b)将模制料应用到步骤(a)中所形成的引线框基片上,模制料将半导体单元片盘、多个终端盘、多个临时和永久连接条,以及多个永久和临时引线固定在一起;以及(c)从引线框基片中去除多个临时连接条和临时引线。 Yet another aspect of the present invention to provide a manufacturing method of lead frame substrate, the lead frame substrate is configured to receive a semiconductor die, and discrete passive components, the method comprising the steps of: (a) in the lead frame base material sheet is formed sheet, the lead frame substrate including at least one semiconductor die plate, a plurality of terminal plate, a semiconductor die plate and a plurality of terminal plate link together a plurality of temporary and permanent connection bars, and a plurality of permanent and temporary leads; ( a lead frame substrate b) is applied to the molding material in step (a) formed in the molding material of the semiconductor die plate, a plurality of terminal plate, a plurality of temporary and permanent connection bars, and a plurality of permanent and temporary leads fastened together; and (c) removing a plurality of temporary connection bars and temporary leads from the lead frame substrate.

已为了说明和描述的目的提供本发明的优选实施方案的前面描述。 Purposes of illustration and description have been provided in front of a preferred embodiment of the present invention will be described. 它不打算做到无遗漏或者用来将本发明局限于所公开的精确形式。 It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. 显然地,本领域技术人员容易想到许多修改和改变。 Obviously, those skilled in the many modifications and changes will readily occur. 选择和描述实施方案,以便最好地说明本发明的原理及其实际应用,从而允许本领域其他人员理解适合于所考虑的实际应用的对应各种实施方案和具有各种修改的发明。 Embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby allowing other personnel to understand for those skilled in correspondence with the various embodiments and various modifications of the invention in the practical application considered. 本发明的范围打算由下面的权利要求及其等价物来定义。 The intended scope of the invention be defined by the following claims and their equivalents.

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