CN1722423A - Conducting wire frame for improving package reliability and its packaging structure - Google Patents
Conducting wire frame for improving package reliability and its packaging structure Download PDFInfo
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- CN1722423A CN1722423A CNA2004100690728A CN200410069072A CN1722423A CN 1722423 A CN1722423 A CN 1722423A CN A2004100690728 A CNA2004100690728 A CN A2004100690728A CN 200410069072 A CN200410069072 A CN 200410069072A CN 1722423 A CN1722423 A CN 1722423A
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- lead frame
- weld layer
- package reliability
- bonding wire
- raising
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/78—Apparatus for connecting with wire connectors
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Abstract
This invention relates to a wire frame and its packing structure for increasing packing quality, the wire frame comprises a chip seat and multiple pins around the seat, characterized in that: forming metal convex block or concave block such as irregular structure on the weld layer on wire frame allocation, in the procedure of packing, using packing glue to cover the chip, weld wire and part of wire frame, the irregular structure on the weld layer provides more contacting floor and bonding force with packing glue to avoid breaking the weld wire, which can improve the electricity quality and packing reliance.
Description
Technical field
The invention relates to a kind of lead frame and encapsulating structure thereof that improves package reliability, particularly about a kind of conducting wire frame structure of the gold thread soldering reliability between chip and lead frame and encapsulating structure of using this lead frame of improving.
Background technology
The conventional semiconductors chip be with lead frame (Lead Frame) as chip bearing member to form the semiconductor packaging part.This lead frame comprises a chip carrier and is formed on this chip carrier many pins on every side, after treating that semiconductor chip is bonded on the chip carrier and electrically connects this chip and pin with bonding wire, coat the inner segment of this chip, chip carrier, bonding wire and pin via a potting resin, thereby form the semiconductor package part of this tool lead frame.
With lead frame as the form of the semiconductor sealing of chip bearing member and of a great variety, as QFP semiconductor package part (Quad Flat Package), QFN (Quad-Flat Non-leaded) semiconductor package part, SOP semiconductor package part (Small Outline Package) or DIP semiconductor package part (Dual in-line Package) etc., for the radiating efficiency that improves semiconductor package part with take into account chip size packages (Chip Scale Package, CSP) small size requirement, many at present QFN semiconductor package part or dew cushion (Exposed Pad) semiconductor package parts that expose with the chip carrier bottom are the encapsulation main flow.
In addition, the semiconductor package part of conventional wires frame form is the electrical quality that further improves semiconductor package part, except that utilizing holding wire (Signal Wire) to electrically connect each pin, also can electrically connect the chip carrier of chip ground mat and this lead frame with earth connection (Ground Wire) on this semiconductor chip by downward routing (Down Bond) mode.Just this lead frame routing distributed area of providing bonding wire do to electrically connect is can comprise around this pin part and this chip carrier.
When providing semiconductor chip and lead frame to do to electrically connect; because of the material of this lead frame mainly is a copper; and the material of bonding wire mainly is a gold; because copper is not good with the zygosity of gold; therefore can on lead frame, to carry out the zone (for example pin) of routing usually and go up first preplating silver metal; when routing, utilize the silver in the routing zone of the gold of bonding wire and this lead frame to form eutectic structure, wire bonds is provided and is electrically connected on the lead frame.Because the tack of this silver metal and packing colloid is not good, in subsequent handling,, and then cause bonding wire rhegma or breakage problem easily because of thermal stress generation delamination problems.
Particularly for the QFN semiconductor package part, wherein be not provided with external pin, promptly be not formed with as the external pin in order to electrically connect with the external world in the existing QFP semiconductor package part, so, the size that can dwindle semiconductor package part.Shown in Figure 1A, chip carrier 11 bottom surfaces and pin one 2 bottom surfaces of this QFN semiconductor package part 1 lead frame 10 all are to expose outside packing colloid 15, make to connect to put on this chip carrier 11 and be electrically connected to the heat that the semiconductor chip 13 of pin one 2 produces to be transmitted to the external world effectively by bonding wire 14, and make this QFN semiconductor package part 1 can borrow these pin one 2 exposed surfaces directly with external device such as printed circuit board (PCB) (printed circuit board) (figure is mark) electric connection.
Other sees also the local enlarged diagram of the bonding wire in order to be electrically conducted semiconductor chip and lead frame shown in Figure 1B and Fig. 1 C, because this QFN lead frame is only coated with its packed colloid 15 in single surface, therefore in packaging process, very easily because be subjected to the influence of thermal stress, make and between the silver metal of packing colloid 15 and pin one 2 delamination problems takes place, and then cause bonding wire 14 rhegmas or fracture, have a strong impact on the reliability of operation.
In view of the foregoing, United States Patent (USP) the 6th, 208,020,6,338,984,6,483, No. 178 cases promptly are disclosed on the pin of lead frame, form groove or hole, improve the engaging force of this lead frame and packing colloid by this groove or hole.
See also Fig. 2, it is a United States Patent (USP) the 6th, 483, the lead frame encapsulation structure that No. 178 case disclosed.This lead frame encapsulation structure is a QFN semiconductor package part 2, it comprises the chip carrier 21 that bottom side surface exposes, be bonded on the chip 23 on this chip carrier, be arranged on this chip carrier many pin twos 2 on every side, be connected with the bonding wire 24 between this chip 23 and this pin two 2, and the packing colloid 25 that the outer surface of this pin two 2 and mode that bottom side surface exposes are coated this pin two 2, chip 23, bonding wire 24 and the part of this chip carrier 21 except that bottom side surface.Wherein this pin two 2 is provided with at least one keyhole 26a that runs through these pin two 2 thickness directions, and packing colloid 25 also can be filled in the middle of this keyhole 26a.This keyhole 26a is made up of two cylindrical hole 261a and 262a, and the axis projection sectional area that wherein is positioned at the through hole 261a at top place is the axis projection sectional area of the through hole 262a that thereunder locates less than the position, so that be filled in the interior packing colloid 25 of this keyhole 26a, can these pin 3 buckles be lived by the long-pending up-small and down-big section difference structure of its projecting section, pin two 2 can be fixed in the packing colloid 25.
Yet pursuing under the compact prerequisite of electronic installation, the lead frame that use has thin space and undersized mount structure form has become present industry main flow, therefore on the pin of small size, not only there is not sufficient room to form groove or hole, and its operation difficulty, moreover, being provided with of this groove or hole can make undersized mount structure rigidity reduce, difficulty increases when causing welding, it is outside the routing zone of pin that moreover existing these grooves and hole are provided with the position, there is no much benefiting for the silver layer in the solution routing zone and the delamination problems of packing colloid.
In addition, United States Patent (USP) the 5th, 960, No. 262 case then discloses a kind of at bonding wire tail end contact (Stitch Bond, be commonly referred to as two solder joints) on plant gold bump (Stud-Bond) and come the welded bonding wire interconnection technique of reinforcement, the integral manufacturing flow process of this technology sees also Fig. 3 A to Fig. 3 F.
Shown in Fig. 3 A and Fig. 3 B, at first, prepare a wire bonder (Wire Bonder), this wire bonder comprises that at least one holds the tip 34 of gold thread (bonding wire) 32, and the wire clamp 36 (Clamper) that provides gold thread 32 to fold up, wherein, the gold thread 32 of these tip 34 front ends is to form ball-type contact (Free Air Ball with burning playing skill art commonly used, FAB), with with semiconductor chip on each I/O tie point 300 corresponding crimping, thereby this ball-type contact (Ball Bond generally is called first solder joint) is soldered on the I/O tie point 300.Shown in Fig. 3 C, then, mobile tip 34 is moved gold thread 32 on pin (Lead) 31 predeterminated positions of lead frame to by the traction of tip 34, and being welded (Stitch Bond) and blocking becomes second solder joint.Shown in Fig. 3 D to Fig. 3 F, afterwards, the gold bump 37 (Stud) of after-culture one and these gold thread 32 same materials on second solder joint of this pin 31 is so as to strengthening welded intensity between second solder joint and pin 31 predeterminated positions.
Because the after-culture gold bump only can be strengthened engaging of solder joint and lead frame on second solder joint, makes the neck at the nearly solder joint of this gold thread place become the relative weakness of gold thread structural strength, and breakage problem easily takes place herein; Moreover, form the precision that this gold bump must strictly be controlled the tip translation, can make like this that activity time prolongs, cost increases and can improve difficulty in the operation; In addition, when the gold thread that connects projection was pulled apart, it is wayward and thread end length that cause remaining on the tip differs that the broken string place often is subject to translational movement, therefore also can have influence on the ball-type that burns ball (FAB) next time, makes that the size of ball-type contact can't homogeneous.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, main purpose of the present invention is to provide a kind of lead frame and encapsulating structure thereof that improves package reliability, avoid the stress between lead frame and the packing colloid to cause the wire bonds position that delamination or fracture take place, keep bonding wire connecting portion good electrical conductivity.
Another object of the present invention is to provide a kind of lead frame and encapsulating structure thereof that improves package reliability, can use traditional routing welding sequence, do not need accurately to control the fineness of operation,, can improve the reliability that encapsulates between packing colloid and lead frame simultaneously to shorten the routing spended time.
A further object of the present invention is to provide a kind of lead frame and encapsulating structure thereof that improves package reliability, precision that need not the translation of strict control wire bonder (Wire Bonder), make when solder sphere forms each time to stablize solder sphere (Ball Bond) operation, the ball-type of this solder sphere is kept homogeneous, can improve the reliability that encapsulates between packing colloid and lead frame simultaneously.
For taking off on reaching and other purpose, the lead frame of raising package reliability of the present invention comprises: a chip carrier and be distributed in many pins around this chip carrier, in its routing distributed area, be laid with weld layer at this lead frame, and meet the place of putting and be formed with relative concaveconvex structure at least one this weld layer for bonding wire.Wherein the material of this lead frame mainly is the copper metal, the routing distributed area of this lead frame can on the pin and/or this chip carrier around, and the material of weld layer is metal levels such as silver and nickel/palladium, this relative concaveconvex structure that is formed on the weld layer is the form of putting the metal coupling on this weld layer to plant, or to be formed on the form of the recess in this weld layer, by the out-of-flatness of this relative concaveconvex structure, improve engaging of follow-up packing colloid and this weld layer, and then avoid taking place delamination problems.
In addition, a kind of lead frame encapsulation structure that improves package reliability of the present invention comprises: a lead frame, it has a chip carrier and is distributed in this chip carrier many pins on every side, this lead frame is laid with weld layer in its routing distributed area, and meets the place of putting and be formed with relative concaveconvex structure for bonding wire at least one this weld layer; At least one semiconductor chip is to connect to put on this chip carrier; Many bonding wires are the routing distributed areas that electrically connect this semiconductor chip and lead frame; And a packing colloid, in order to coat the lead frame of this semiconductor chip, bonding wire and part.
Therefore, the lead frame of raising package reliability of the present invention and encapsulating structure thereof mainly be on the routing distributed area of lead frame will with weld layer that bonding wire connects on be formed with for example relative uneven whole structure such as metal coupling or recess, carry out in the packaging process follow-up, make packing colloid be coated on this chip, when bonding wire and part lead frame, make this out-of-flatness structure by this weld layer, itself and more contact area of packing colloid and engaging force can be provided, avoid weld layer and packing colloid to produce delamination and bonding wire breakage problem, so as to improving electrical quality and package reliability.On the other hand, compared with prior art, the present invention is by form the zygosity that the out-of-flatness structure improves lead frame and packing colloid on the weld layer in the routing distributed area of lead frame, do not need on the pin of small size, to form groove or hole, so avoid the difficulty rising of the reduction of mount structure rigidity and operation and routing operation, and can fully reduce the weld layer in the routing distributed area and the delamination problems of packing colloid; In addition, compare with the prior art of bonding wire pressure contact portion tip-in (Stud-bond), the present invention does not need the precision and the translational movement of strict control wire bonder, avoid because the translation departure, cause tip line tail remaining lengths different and cause the shortcoming that ball-type can't homogeneous, and the present invention does not need to use special parameter to control ball-type, thereby improves the operation fluency, and the neck generation breakage problem of avoiding the nearly solder joint of bonding wire place.
Description of drawings
Figure 1A is the generalized section of existing QFN semiconductor package part;
Figure 1B is the partial side view of bonding wire generation delamination and breakage problem in the existing QFN semiconductor package part;
Fig. 1 C is the partial top view of bonding wire generation delamination and breakage problem in the existing QFN semiconductor package part;
Fig. 2 is a United States Patent (USP) the 6th, 483, and No. 178 case forms reeded encapsulating structure schematic diagram on the pin of lead frame;
Fig. 3 A to Fig. 3 F is a United States Patent (USP) the 5th, 960, and No. 262 cases plant gold bump and come the welded bonding wire of reinforcement to connect the operation schematic diagram on bonding wire tail end contact;
Fig. 4 A and Fig. 4 B are the lead frame schematic diagrames of the raising package reliability of the embodiment of the invention 1;
Fig. 4 C is the schematic diagram that the weld layer in the routing distributed area of lead frame is provided with metal coupling;
Fig. 5 A and Fig. 5 B are the lead frame encapsulation structure schematic diagrames of the raising package reliability of the embodiment of the invention 1;
Fig. 6 A to Fig. 6 C is the weld layer jog operation schematic diagram of lead frame that forms the raising package reliability of the embodiment of the invention 2; And
Fig. 6 D is formed with the annular recessed portion structural representation that exposes outside this lead frame ground in the weld layer in the routing distributed area of lead frame.
Embodiment
Below (lead frame among the present invention is not limited thereto, also can be the conducting wire frame structure of other form for Quad-Flat Non-leaded, QFN) the detailed specific embodiments of the invention of the lead frame of packaging part to be applicable to the quadrangular plan non-pin now; Simultaneously, the accompanying drawing of following embodiment also only simply illustrates the modular construction relevant with implementation content, and actual included component count, size and layout is often complicated more.
Fig. 4 A and Fig. 4 B are the lead frame schematic diagrames of the raising package reliability of the embodiment of the invention 1.This lead frame 40 mainly comprises: a chip carrier 41 and be distributed in many pins 42 around this chip carrier, this lead frame 40 is laid with weld layer 43 in its routing distributed area, and do not meet the place of putting at least one this weld layer 43 and be formed with for example relative concaveconvex structure of metal coupling 441 for bonding wire, wherein, this concaveconvex structure is alternative or is arranged on the weld layer 43 of this lead frame 40 comprehensively, may be subjected to big thermal stress place (i.e. the position of the pin 42 at these lead frame 40 corner places and chip carrier 41 weld layers 43) selectivity on for example can weld layer 43 this concaveconvex structure is set, so as to preferable zygosity between weld layer 43 that this lead frame 40 is provided in the thermal environment of packaging process and packing colloid at this lead frame 40.
Wherein, the routing distributed area of this lead frame 40 can comprise around these pin 42 inside parts and this chip carrier 41, can put when this chip carrier 41 for follow-up chip is connect, except that utilizing signal bond wires (Signal Wire) to electrically connect each pin 42, also can utilize ground connection bonding wire (GroundWire) to electrically connect around the chip carrier 41 of chip ground mat and this lead frame 40 not by the occupied pre-defined access area (Grounding Region) that goes out of chip.The material of this lead frame mainly is the copper metal, the material of weld layer is metal levels such as silver, nickel/palladium, providing when utilizing bonding wire (gold thread) do to electrically connect between semiconductor chip and lead frame, weld layer (silver) by the routing distributed area of bonding wire (gold) and this lead frame forms eutectic structure, makes wire bonds and is electrically connected on the lead frame.
Other sees also Fig. 4 C, the relative concaveconvex structure that is arranged on the weld layer 43 in routing distributed area of this lead frame 40 can be to plant metal coupling 441 forms of putting on this weld layer 43, this metal coupling 441 is to utilize wire bonder (Wire Bonder) 45 to plant the gold bump (Stud) of putting with the bonding wire same material, the out-of-flatness structure that forms by this metal coupling 441 increases the adhesive force to packing colloid, avoid this weld layer (silver) 43 not good, cause follow-up delamination and bonding wire breakage problem with the tack of packing colloid.
In present embodiment 1, can be provided with at wire bonder tip place a thermofusion device (ElectricFlame-off, EFO), with discharge mode by high-tension electricity (about 4000 volts) etc., the bonding wire front end sinter into a ball-type contact (Free Air Ball, FAB).Then, mobile tip is crimped onto the ball-type contact of tip front end downwards on the weld layer, makes the ball-type contact fusion that connects bonding wire be engaged on the weld layer surface.With present embodiment 1 is example, and this ball-type contact is with after weld layer contacts, and the tip of wire bonder can be bestowed the downward pressure of about 100 grams of this ball-type contact, and produces the ultrasonic wave of the about 60-120kHz of frequency, makes ball-type contact and weld layer friction and produces and fuse.
Fig. 5 A and Fig. 5 B are the lead frame encapsulation structure schematic diagrames of the raising package reliability of the embodiment of the invention 1, this encapsulating structure comprises as the lead frame 40 as shown in Fig. 4 A and Fig. 4 B, this lead frame 40 has a chip carrier 41 and is distributed in this chip carrier 41 many pins 42 on every side, and in its routing distributed area, be laid with weld layer 43, meet the place of putting and be formed with relative concaveconvex structure for bonding wire on wherein at least one this weld layer 43, this relative concaveconvex structure can be the metal coupling 411 with this bonding wire same material; At least one semiconductor chip 51 is to connect to put on this chip carrier 41; Many bonding wires 52 are the weld layers 43 that electrically connect the routing distributed area of this semiconductor chip 51 and lead frame 40; And a packing colloid 53, in order to coat the lead frame 40 of this semiconductor chip 51, bonding wire 52 and part.
Wherein, this metal coupling 441 is can utilize wire bonder to plant in advance to put on the weld layer 43 in the routing distributed area of this lead frame 40, on the chip carrier 41 of this lead frame 40, connect again and put semiconductor chip 51, carry out the bonding wire operation with wire bonder more afterwards, this semiconductor chip 51 and lead frame 40 are electrically connected.In addition, also can be after semiconductor chip 51 be placed the chip carrier 41 of this lead frame, utilize wire bonder on the weld layer 43 in the routing distributed area of this lead frame 40, to form this metal coupling 441 earlier, utilize wire bonder to carry out the bonding wire operation simultaneously, not plant the space that is equipped with metal coupling 441 by routing distributed area on this semiconductor chip 51 of bonding wire 52 electric connections and this lead frame 40.
Fig. 6 A to Fig. 6 C is the operation schematic diagram for the weld layer jog of the lead frame of the raising package reliability that forms the embodiment of the invention 2.It is to utilize wire bonder to beat mode in the enterprising line space of weld layer, in this weld layer, to form recess, and then the alternative ground that exposes this lead frame, just in the tip of this wire bonder, be not equipped with bonding wire, and directly push this weld layer in the sky mode of beating, so as in this weld layer, being formed with concaveconvex structure.
At first, the wire bonder 45 that is not equipped with bonding wire in the tip 451 is placed on the weld layer 43 of lead frame 40 (as shown in Figure 6A).Then, move this tip 451, and make its to this weld layer 43 of lower compression to this lead frame ground part (shown in Fig. 6 B).Afterwards, remove this tip 451 (shown in Fig. 6 C figure).Whereby, shown in Fig. 6 D, can in this weld layer 43, be formed with the annular recessed portion structure 442 that exposes outside this lead frame ground, by this uneven whole structure to increase adhesive force to packing colloid.
Follow-up, when carrying out the semiconductor packages operation, be that the lead frame that is formed with recess structure in advance at weld layer can be provided, on the chip carrier of this lead frame, connect again and put semiconductor chip, then carry out the bonding wire operation with wire bonder again, this semiconductor chip and lead frame are electrically connected, utilize packing colloid to coat the lead frame of this semiconductor die, bonding wire and part afterwards.In addition, also can be after semiconductor chip be placed the chip carrier of lead frame, utilize the wire bonder that does not contain gold thread to beat earlier in the enterprising line space of weld layer in the routing distributed area of this lead frame, so as at least one this weld layer, forming recess structure, utilize the wire bonder that contains gold thread to carry out the bonding wire operation again, to electrically connect the space that routing distributed area on this semiconductor chip and this lead frame is not provided with recess structure by bonding wire, carry out the packing colloid operation again.
Therefore, the lead frame of raising package reliability of the present invention and encapsulating structure thereof mainly be on the routing distributed area of lead frame will with weld layer that bonding wire connects on be formed with for example relative uneven whole structure such as metal coupling or recess, carry out in the packaging process follow-up, make packing colloid be coated on this chip, when bonding wire and part lead frame, can make this out-of-flatness structure by this weld layer, itself and more contact area of packing colloid and engaging force are provided, avoid weld layer and packing colloid to produce delamination and bonding wire breakage problem, so as to improving electrical quality and package reliability.When the present invention simultaneously also can avoid prior art to form groove or hole on the pin of lead frame, the problem that causes the difficulty of reduction of mount structure rigidity and operation and routing operation to improve, and avoid the neck at complex procedures that prior art causes in the tip-in of bonding wire pressure contact portion and the nearly solder joint of bonding wire place that the problem of fracture takes place.
Claims (24)
1. a lead frame that improves package reliability is characterized in that, the lead frame of this raising package reliability comprises:
One chip carrier; And
Many the pins that are distributed in around this chip carrier;
This lead frame is laid with weld layer in its routing distributed area, and meets the place of putting and be formed with relative concaveconvex structure for bonding wire at least one this weld layer.
2. the lead frame of raising package reliability as claimed in claim 1 is characterized in that, this relative concaveconvex structure is to plant the metal coupling of putting on this weld layer surface.
3. the lead frame of raising package reliability as claimed in claim 1 is characterized in that, this relative concaveconvex structure is arranged on the recess structure in this weld layer.
4. the lead frame of raising package reliability as claimed in claim 1 is characterized in that, the routing distributed area of this lead frame is this pin inside part.
5. the lead frame of raising package reliability as claimed in claim 1 is characterized in that, the routing distributed area of this lead frame is around this chip carrier.
6. the lead frame of raising package reliability as claimed in claim 1 is characterized in that, the material of this lead frame mainly is the copper metal, and the material of this weld layer is a kind of in silver and the nickel/palladium metal.
7. the lead frame of raising package reliability as claimed in claim 2 is characterized in that, this metal coupling utilizes wire bonder to plant and puts, and increases the adhesive force of lead frame to packing colloid by this metal coupling out-of-flatness structure.
8. the lead frame of raising package reliability as claimed in claim 3, it is characterized in that, this recess structure utilizes wire bonder to form in the enterprising line space mode of beating of weld layer, increases the adhesive force of lead frame to packing colloid so as to be formed with the out-of-flatness structure in weld layer.
9. the lead frame of raising package reliability as claimed in claim 8 is characterized in that, this recess structure is optionally to expose the ground of this lead frame.
10. a lead frame encapsulation structure that improves package reliability is characterized in that, this lead frame encapsulation structure comprises:
One lead frame has a chip carrier and many and is distributed in pin around this chip carrier, and this lead frame is laid with weld layer in its routing distributed area, and meets the place of putting for bonding wire at least one this weld layer and be formed with relative concaveconvex structure;
At least one connects the semiconductor chip of putting on this chip carrier;
Many bonding wires are the routing distributed areas that electrically connect this semiconductor chip and lead frame; And
One packing colloid is in order to coat this semiconductor chip, bonding wire and part lead frame.
11. the lead frame encapsulation structure of raising package reliability as claimed in claim 10 is characterized in that, this relative concaveconvex structure is to plant the metal coupling of putting on this weld layer surface.
12. the lead frame encapsulation structure of raising package reliability as claimed in claim 10 is characterized in that, this relative concaveconvex structure is arranged on the recess structure in this weld layer.
13. the lead frame encapsulation structure of raising package reliability as claimed in claim 10 is characterized in that, the routing distributed area of this lead frame is this pin inside part.
14. the lead frame encapsulation structure of raising package reliability as claimed in claim 10 is characterized in that, the routing distributed area of this lead frame is around this chip carrier.
15. the lead frame encapsulation structure of raising package reliability as claimed in claim 10 is characterized in that, the material of this lead frame mainly is the copper metal, and the material of this weld layer is a kind of in silver and the nickel/palladium metal.
16. the lead frame encapsulation structure of raising package reliability as claimed in claim 11 is characterized in that, this metal coupling utilizes wire bonder to plant and puts, and increases the adhesive force of lead frame to packing colloid by the out-of-flatness structure of this metal coupling.
17. the lead frame encapsulation structure of raising package reliability as claimed in claim 16, it is characterized in that, this metal coupling is to utilize wire bonder to plant in advance to put on the weld layer in the routing distributed area of this lead frame, on the chip carrier of this lead frame, connect again and put semiconductor chip, carry out the bonding wire operation with wire bonder more afterwards, this semiconductor chip and lead frame are electrically connected.
18. the lead frame encapsulation structure of raising package reliability as claimed in claim 10, it is characterized in that, this encapsulating structure is after semiconductor chip is placed the chip carrier of this lead frame, utilize wire bonder to form this metal coupling earlier at the weld layer in the routing distributed area of this lead frame, utilize wire bonder to carry out the bonding wire operation simultaneously, electrically connect on this semiconductor chip and this lead frame routing distributed area by bonding wire and do not plant the space that is equipped with metal coupling.
19. the lead frame encapsulation structure of raising package reliability as claimed in claim 12, it is characterized in that, this recess structure utilizes wire bonder to form in the enterprising line space mode of beating of weld layer, increases the adhesive force of lead frame to packing colloid so as to be formed with the out-of-flatness structure in weld layer.
20. the lead frame encapsulation structure of raising package reliability as claimed in claim 19 is characterized in that, this recess structure is optionally to expose the ground of this lead frame.
21. the lead frame encapsulation structure of raising package reliability as claimed in claim 10, it is characterized in that, this encapsulating structure provides the lead frame that is formed with recess structure in advance at weld layer, on the chip carrier of this lead frame, connect again and put semiconductor chip, then carry out the bonding wire operation with wire bonder again, this semiconductor chip and lead frame are electrically connected.
22. the lead frame encapsulation structure of raising package reliability as claimed in claim 10, it is characterized in that, this encapsulating structure is after semiconductor chip is placed the chip carrier of lead frame, utilize the wire bonder that does not contain gold thread to beat earlier in the enterprising line space of weld layer in this lead frame routing distributed area, so as in this weld layer, forming recess structure, utilize the wire bonder contain gold thread to carry out the bonding wire operation again, to electrically connect the space that routing distributed area on this semiconductor chip and this lead frame is not provided with recess structure by bonding wire.
23. the lead frame encapsulation structure of raising package reliability as claimed in claim 10 is characterized in that, this bonding wire is a signal bond wires, is in order to electrically connect the pin of semiconductor chip and lead frame.
24. the lead frame encapsulation structure of raising package reliability as claimed in claim 10 is characterized in that, this bonding wire is the ground connection bonding wire, is in order to not occupied the pre-defined access area that goes out by chip around the chip carrier that electrically connects semiconductor chip and lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100690728A CN100424864C (en) | 2004-07-16 | 2004-07-16 | Conducting wire frame for improving package reliability and its packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100690728A CN100424864C (en) | 2004-07-16 | 2004-07-16 | Conducting wire frame for improving package reliability and its packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1722423A true CN1722423A (en) | 2006-01-18 |
| CN100424864C CN100424864C (en) | 2008-10-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100690728A Expired - Fee Related CN100424864C (en) | 2004-07-16 | 2004-07-16 | Conducting wire frame for improving package reliability and its packaging structure |
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| CN (1) | CN100424864C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100463156C (en) * | 2006-07-31 | 2009-02-18 | 宏茂微电子(上海)有限公司 | Chip packaging structure and manufacturing method therefor |
| US7683462B2 (en) | 2007-02-06 | 2010-03-23 | Chipmos Technologies (Bermuda) Ltd. | Chip package structure |
| CN106796896A (en) * | 2014-09-01 | 2017-05-31 | 株式会社电装 | Semiconductor device |
| CN108352330A (en) * | 2015-12-30 | 2018-07-31 | 德州仪器公司 | Printing adhesion deposition for mitigating integrated circuit layering |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100192760B1 (en) * | 1996-02-29 | 1999-06-15 | 황인길 | Method for manufacturing bga package using metal carrier frame |
| US6585905B1 (en) * | 1998-06-10 | 2003-07-01 | Asat Ltd. | Leadless plastic chip carrier with partial etch die attach pad |
| US6661083B2 (en) * | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
| JP4068336B2 (en) * | 2001-11-30 | 2008-03-26 | 株式会社東芝 | Semiconductor device |
| CN1512566A (en) * | 2002-12-27 | 2004-07-14 | 威宇科技测试封装（上海）有限公司 | Substrate for face down bonding |
-
2004
- 2004-07-16 CN CNB2004100690728A patent/CN100424864C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100463156C (en) * | 2006-07-31 | 2009-02-18 | 宏茂微电子(上海)有限公司 | Chip packaging structure and manufacturing method therefor |
| US7683462B2 (en) | 2007-02-06 | 2010-03-23 | Chipmos Technologies (Bermuda) Ltd. | Chip package structure |
| US8105881B2 (en) | 2007-02-06 | 2012-01-31 | Chipmos Technologies (Bermuda) Ltd. | Method of fabricating chip package structure |
| CN101241890B (en) * | 2007-02-06 | 2012-05-23 | 百慕达南茂科技股份有限公司 | Chip package structure and its making method |
| CN106796896A (en) * | 2014-09-01 | 2017-05-31 | 株式会社电装 | Semiconductor device |
| CN106796896B (en) * | 2014-09-01 | 2019-07-09 | 株式会社电装 | Semiconductor device |
| CN108352330A (en) * | 2015-12-30 | 2018-07-31 | 德州仪器公司 | Printing adhesion deposition for mitigating integrated circuit layering |
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| CN100424864C (en) | 2008-10-08 |
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