CN1722276A - 用于使用多个交错删除指针来检测和校正错误的技术 - Google Patents
用于使用多个交错删除指针来检测和校正错误的技术 Download PDFInfo
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- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
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Abstract
用于检测和校正在两级分组代码结构中形成的数据字节中的突发错误的技术。第二级解码器使用分组级检验字节来检测包含错误字节的、在两级分组代码结构中的列。第二级解码器产生删除指针,用于标识已经被突发错误影响的、在两级分组结构中的列。然后,第一级解码器使用码字检验字节来校正在通过删除指针而标识的列中的所有字节。释放第一级解码器以使用所有的码字检验字节来仅仅用于错误字节值计算。第一级解码器不需要使用任何码字检验字节来用于错误位置计算,因为由第二级解码器产生的删除指针提供了所有的必要错误位置。本技术加倍了第一级解码器的纠错能力。
Description
技术领域
本发明涉及用于检测和校正在存储介质上的错误的技术,具体涉及用于以多级综合交错格式使用多个交错删除指针来检测和校正在存储介质上的误差的技术。
背景技术
数据字节以被称为码字(扇区)的多个组被存储在磁介质上。通常,512个数据直接被存储在每个码字中。数据字节的码字可以包括多个交错字(即数据字节串或向量)和按字节交错(byte-interleaved)的对应的检验字节。
在以多个分组(block)记录在存储介质上的长字节串中检测和校正多字节错误。每个分组包括多个码字和从所述码字得到的多个分组级的检验字节。每个码字包括数据字节和按照线性纠错码从多个等长度数据字节串映射来的码字检验字节。
通过逻辑地求和数据字节串和通过将所述逻辑和与数据字节串映射为对应的码字来产生和记录每个分组。所述对应码字包括按照相同的线性纠错码的码字检验字节。接着,逻辑求和所述码字。所述码字和它们的逻辑和在被记录到存储器件等之前以预定的模式被交错。
在在此通过引用而并入的美国专利5,946,328中讨论了用于检测和校正错误字节的技术的其它细节。三个数据流m1(x)、m2(x)和m3(x)被用作示例。所述数据流中的两个m1(x)和m2(x)由第一里德-索罗蒙(RS)线性编码器编码,所述第一里德-索罗蒙(RS)线性编码器产生相应的码字c1(x)和c2(x)。这个第一RS编码器向每个码字附加2t1个检验字节。
第三数据流m3(x)在被第二RS编码器编码之前被修改以形成逻辑(模2)和m1(x)+m2(x)+m3(x)。这个第二RS编码器包括在逻辑求和的数据流的码字c’(x)内的2t1+2t2个检验字节。码字c3(x)表示三个码字的逻辑和c1(x)+c2(x)+c’(x)。第三码字c3(x)当以这种方式产生时包含2t2个共享的分组检验字节和2t1个独立检验字节。所述分组检验字节是RS码字的内部并且是其固有部分。
通过线性纠错编码相应的数据字节串m1(x)和m2(x)而产生码字中的两个c1(x)和c2(x)。码字c1(x)和c2(x)需要2t1检验字节。也通过线性编码m1(x)、m2(x)和m3(x)的模2和产生码字c’(x)。码字c’(x)需要2t1+2t2检验字节。数据字节串m1(x)和m2(x)被附加由φ(x)表示的2t2个零,以便保证相等的码字长度。然后,码字输出可以表达为:
c1(x)=x2t1+2t2m1(x)+(x)+r1(x)
c2(x)=x2t1+2t2m2(x)+(x)+r2(x)
c’(x)=x2t1+2t2[m1(x)+m2(x)+m3(x)]+r(x)
码字c’(x)被进一步处理以通过求三个码字c1(x)、c2(x)和c’(x)的模2和而产生修改的、第三码字c3(x),以使得:
c3(x)=[c1(x)+c2(x)]+c’(x)=x2t1+2t2m3(x)+rB(x)+r3(x)
检验字节rB(x)是由m1(x)、m2(x)和m3(x)共享的分组检验字节,而r3(x)是数据流m3(x)的独立检验字节。
检验字节r1(x)、r2(x)和r3(x)是第一级检验字节。这些检验字节可以仅仅用于分别校正在码字c1(x)、c2(x)和c3(x)内的数据字节中的t1个错误。在码字c3(x)内的检验字节rB(x)是第二(分组)级检验字节,可以用于校正在码字c1(x)、c2(x)和c3(x)的任何一个中的t1+t2个数据字节错误。
在这些计算后,码字c1(x)、c2(x)和c3(x)的一个综合的交错分组被写出到盘。随后,当盘必须执行读取或读取修改写入命令等时,一个被寻址的分组或多个码字的分组从它们在盘上的轨道位置流出(stream)。根据码字的校正子(syndrome)处理,在盘上的任何错误被即时地检测和校正。所述校正子是从所声称的码字和它们的逻辑和模2得到的。非零的校正子指示错误字节。任何非零的校正子在码字上被标识和处理以校正错误的字节。被更新的分组级非零校正子也被处理以定位和校正超出任何单个码字的校正能力的那个码字中的错误字节。
在此通过引用而并入的美国专利6,275,965描述了一种在两级代码结构中校正错误字节的系统。可以使用每码字2t1个检验字节来定位和校正在一个码字中的最多t1个错误字节。具有超出其t1个码字校正能力的错误字节的一个码字是一个突发子分组。可以使用B*(2t2)个分组级检验字节来在B个突发子分组中定位和校正最多t1+t2个错误字节。
一个后编码处理被提供来将所计算的码字“去交错”或重新分布为修改的码字,以使得在同一码字中定位数据向量和它们的码字检验字节。在码字中分布了分组级的检验字节。
在6,275,965专利中描述的技术用于校正在码字的随机位置发生的错误字节。但是,在码字中的错误字节的数量可以超过在6,275,965专利中描述的技术的校正能力。这些类型的错误被称为突发错误。突发错误可以例如作为在磁盘上的划痕或缺陷的结果而出现。
因此,期望提供用于检测和校正在两级分组代码结构中形成的数据字节中出现的突发错误的其它技术。
发明内容
本发明提供了用于检测和校正在两级分组代码结构中形成的数据字节中的突发错误的技术。按照本发明,第二级解码器使用分组级检验字节来检测包含错误字节的、在两级分组代码结构中的列。第二级解码器产生删除指针,用于标识已经被突发错误影响的、在两级分组结构中的列。
第一级解码器然后使用码字检验字节来校正在通过删除指针而标识的列中的所有字节。本发明释放了第一级解码器以使用所有的码字检验字节来仅仅用于错误字节值计算。第一级解码器不需要使用任何码字检验字节来用于错误位置计算,因为由第二级解码器产生的删除指针提供了所有的必要错误位置。第一级解码器的纠错能力被加倍,因为释放了所有的码字检验字节以仅仅用于错误值计算。
根据下面的详细说明和附图,本发明的其他目的、特征和优点将变得清楚,在全部附图中,类似的附图标号表示类似的功能部件。
附图说明
图1A是详细说明包括用于实现即时纠错码的即时纠错码(ECC)系统的缓冲硬盘驱动控制器的结构的方框图。
图1B是用于描述沿着图1A的硬盘驱动控制器的读取通道和写入通道的数据流的数据存储系统的方框图。
图2图解了按照本发明的两级分组代码结构。
图3图解了按照本发明的用于检测和校正随机错误的第一级解码器。
图4图解了按照本发明的技术的用于检测突发错误的第二级解码器。
图5图解了按照本发明的技术的用于校正突发错误的第一级解码器。
具体实施方式
图1A和图1B图解了用于读取和向磁硬盘上写入数据的硬盘驱动控制系统的一个示例。图1A-1B的硬盘驱动控制系统是可以实现上述的本发明的技术的硬盘驱动系统的一个示例。图1A-1B的硬盘驱动系统检测和校正在从盘读取的数据中的错误。图1A-1B的硬盘驱动系统可以用于实现本发明的纠错技术,下面详细讨论它们。
图1A图解了被缓冲的硬盘驱动控制器的示例结构。硬盘驱动控制器50配置成相对于磁硬盘14读取和写入数据。控制器50包括即时纠错码(ECC)系统100,用于实现即时纠错码。即时纠错码系统100包括ECC读取处理器163和ECC写入处理器167。
图1B是包括即时纠错码系统100的、图1A的硬盘驱动控制器50的方框图。当数字二进制数据序列要被写入在盘14上的时候,它们被暂时地布置在图1A所示的缓冲器165中,并且随后沿着写入路径或通道被处理和转换(167、169和157)。
硬盘驱动控制器50包括图1B所示的逻辑驱动电路105,用于格式化来自硬盘组件33的数据,例如从8比特到32比特。盘组件33由盘14和包括主轴电机的磁头组组件组成。先入先出寄存器110存储格式化数据,并且将其与扇区缓冲器120交换。ECC系统100从驱动逻辑电路105接收格式化数据,并且执行纠错编码算法。ECC系统100也可以执行本发明的所述技术和处理,下面详细说明。
缓冲管理器115控制在ECC系统100、扇区缓冲器(即随机存取存储器)120和微处理器125之间的数据通信。另一个先入先出检测器130存储数据和将其与扇区缓冲器120交换。序列控制器135连接在驱动逻辑电路105、微处理器125和主机接口140之间,用于控制通过硬盘驱动控制器50的数据通信和各种命令的序列操作。主机接口140提供了在硬盘驱动控制器50和主机60之间的接口。
首先,从缓冲器165去除和通过ECC写入处理器167流出在一个数据串中的预定数量的二进制数据元——也称为字节。在ECC写入处理器167中,数据字节被映射为从适当的线性分组或诸如里德-索罗蒙码的循环码得到的码字。接着,每个码字在写入路径信号整形单元169中被映射为游程长度受限的或其他带通的或频谱整形的代码,并且被改变为时变信号。所述时变信号通过接口读取/写入转换器接口157被施加,然后被施加到在磁致电阻(或其他适当的转换器头)中的写入元件,用于转换为磁通量分布图。
从来自缓冲器165的二进制数据元的移动开始直到当旋转的盘14在读取/写入头下通过时在所选择的盘轨道上写入磁通量分布图为止的所有措施被同步和流出。为了有效的数据传送,数据被一次降级(写出)或升级(读取)一个码字。
因此,必须在定义在转换器下移动的记录轨道长度单位的时间间隔内良好地进行将二进制数据映射为里德-索罗蒙码字和向产生时变信号的通量的转换。记录轨道长度的典型单位是512字节的相等固定长度字节的码字。
当要从盘14读取磁通量分布图的序列时,它们在读取路径或通道(157,159、161和163)中被处理,并且被写入到缓冲器165中。由转换器感测的时变信号通过读取/写入转换器接口157被传送到数字信号提取单元159。在此,检测所述信号,并且确定是否它应当被解析为二进制的1或0。当这些1和0流出信号提取单元159时,它们在格式化单元161中被排列为码字。
因为读取路径正在评估先前在盘14上记录的里德-索罗蒙码字的序列,因此在没有错误或删除的情况下,所述码字应当是相同的。为了测试是否是这样,每个码字从格式化器161通过一条路径被施加到ECC读取处理器163。
而且,来自ECC处理器163的输出被写入到缓冲器165。读取路径也以同步数据流出的方式工作,以使得在码字内及时地定位和校正任何所检测的错误,以使得ECC读取处理器163接收从盘轨道读取的下一个码字。微处理器125可以监视和控制缓冲器165和读写通道,以保证效能,其中引用的模式可以支配不去除路径,诸如顺序读取引用。
数据字节通常以码字被存储在数据存储盘中。码字的子集被分组为长分组。每个码字包括第一级CRC/ECC字节,每个分组包括第二级ECCB字节。
数据存储系统使用第一级CRC和ECC字节来定位和校正在码字内的数据字节中的错误。当在要由第一级ECC字节校正的数据字节中存在太多的错误时,所述数据存储系统使用第二级ECCB字节来如上详细所述地校正错误。ECCB字节用于校正在分组中的任何码字中的数据字节。当第一级和第二级CRC和ECC字节有错误时,会发生错误的误校正。
Asano等的、2003年8月7日公开的美国专利申请公开US 2003/0147167A1——在此通过引用将其并入——中进一步详细地讨论了用于数据存储或通信器件的编码和解码处理。
当在诸如磁盘的存储介质上的划痕或缺陷擦除了几个相邻的数据字节时出现突发错误(也称为硬错误)。因为数据字节以码字和数据字节分组彼此相邻地被存储在磁盘上,因此突发错误擦除在数据分组的码字内彼此相邻地定位的数据字节。
本发明提供了用于检测和校正由在存储介质上的突发错误损坏的数据字节的技术。本发明的技术利用事实:突发错误导致在分组的码字内彼此相邻地定位的被损坏的数据字节。
多个数据流被编码以产生码字,如上和在美国专利5,946,328和6,275,965中进一步详细所述。码字包括数据字节和检验字节。码字包括两级检验字节。每个码字c1、c2、c3、...分别包括第一级检验字节r1、r2、r3、...,它们可以用于校正t1个具有错误的数据字节。所述码字的一个或多个也包括多个第二(分组)级检验字节rB,它们可以用于校正在具有错误的码字的任何一个中的t1+t2个数据字节。
仅仅包括第一级检验字节的码字被称为第一级码字。包括第二级检验字节的码字被称为第二级码字。
在交错的格式中,第一和第二级码字以两级分组代码结构布置。可以表达所述分组以使得每个码字c1、c2、c3、...在图2所示的分组中是一行。第一级码字被嵌套而形成在分组中的第一代码C1,第二级码字被嵌套而形成在分组中的第二代码C2。
每个码字总共具有n个字节。在每个第一级码字中的数据字节的数量是k1。在每个第二级码字中的数据字节的数量是k2。每个第一级码字具有2t1个检验字节,每个第二级码字具有2t2个检验字节。B是可校正的突发码字的数量,m是数据向量的数量。
在两个码字之间的汉明距离是它们不一致的码元的数量。可以证明,为了校正T个字节错误,编码方案要求使用具有在码字之间的至少2T+1的汉明距离的码字。第一代码C1的汉明距离是d1=2t1+1。第二代码C2的汉明距离是d2=2t2+1,其中d1<d2。
图2所示的分组C包括代码C1和C2。分组C被应用到综合矩阵的逆矩阵V-1以重新分布数据向量、码字检验字节和分组级检验字节,如参照美国专利6,275,965的图5和6而进一步详细所述。综合矩阵如图2所示。
使用解码器来根据在形成交错分组的码字的任何一个中检测的校正子产生错误位置和校正值。在解码一个分组前,所述分组首先被去复用以分离出数据字节串、分组检验字节和码字检验字节,以便可以对它们进行有效性测试。校正子产生器产生用于在分组中的码字的校正子。校正子产生技术是本领域内的技术人员公知的。
从码字得到的校正子被应用到第一级里德-索罗蒙解码器。第一级里德-索罗蒙解码器可以检测和校正在任何单个码字中的具有错误的τ1个字节。里德-索罗蒙解码器是本领域内的技术人员公知的。
图3图解了包括四个码字c1、c2、c3、c4的分组200的一个示例。每个码字包括数据向量m和检验字节(阴影部分)。在分组200中存在四个数据向量m,并且B=1。码字ci被应用到第一级解码器201。
解码器201可以检测和校正在码字中的数据向量中出现的随机错误。解码器201使用校正子来检测和校正在四个码字的任何一个中的具有错误的τ1个字节。解码器201输出所校正的码字c’i。所校正的码字包括所校正的数据向量。被校正的错误的数量τi小于第一级汉明距离的一半(τi<d1/2)。
另一个校正子产生器根据在分组中的第二(分组)级检验字节而产生任何非零的校正子。这些校正子被修改以去除由第一级解码器定位的任何错误的效果。如果所更新的校正子是零,则由第一级解码器计算的校正被看作正确的。但是,如果所更新的校正子是非零的或如果第一级解码器检测到错误,则在故障阶段中的第一级校正子和第二级分组校正子被应用到第二级里德-索罗蒙解码器。
因此,如果第一级解码器201在校正码字之一中的错误时不成功,则第二级里德-索罗蒙解码器尝试校正有错误的字节。第二级里德-索罗蒙解码器使用码字检验字节和分组检验字节来校正有错误的字节,如图4所示。第二级解码器可以校正在所有码字的和中有错误的τ2个字节。
两级分组结构使得所有的交错的和是第二代码C2中的码字。在存在突发错误时,在码字中的相邻码元被删除。作为所有的交错的和来获得的、在第二级码字中的码元是在码字中的相邻码元的和。因此,由第二级解码器计算的错误位置是所有交错的自然删除位置。本发明利用这个事实来定位和校正突发错误。
码字ci被应用到图4所示的第二级解码器301。第二级解码器301可以定位已经被突发错误影响的、在两级分组代码结构中的列。解码器301接收从码字检验字节产生的校正子和从分组级检验字节产生的校正子。使用这些校正子,解码器301可以检测包括错误的列。
第二级解码器301输出删除指针Ei。删除指针指向包括错误的、在两级分组结构中的字节的列。因此,第二级代码C2仅仅用于检测在分组中的错误字节的位置。因为突发错误影响相邻的字节,因此通常擦除在一个分组中的字节的整个列。第二级代码C2(它包括分组级检验字节)标识具有错误的列。在突发错误情况下,有可能在被影响的列中的许多或所有字节包含错误。然后使用第一级代码C1来校正由删除指针标识的列中的所有字节。
例如,在图4中的分组300包括四个码字c1、c2、c3和c4。删除指针311、312和313指向在分组300中的第一、第三和第四字节列。可以校正的错误的数量τ2小于第二级汉明距离的一半(τ2<d2/2)。
删除指针Ei和码字ci然后被输入到第一级解码器401,如图5所示。第一级解码器401校正在由第二级解码器301预先处理的两级分组代码结构中的突发错误。解码器401将由第二级解码器301产生的删除指针解译为有错误的字节的位置。每个删除指针指向包含错误字节的一个分组列。第一级解码器401使用第一级码字检验字节来校正在由删除指针标识的列中的每个字节。第一级解码器401输出被校正的码字c’i。如果删除指针Ei的数量等于ρi,则τi和ρi的所有可能组合为真,诸如2τi+ρi<d1。
按照本发明,第二级解码器301仅仅使用分组级检验字节来检测包含错误字节的列。所述分组级检验字节不用于纠错。然后,第一级解码器401使用所述码字检验字节和删除指针来校正在所标识的列中的所有字节。
这种技术释放了第一级解码器将码字检验字节仅仅用于错误值计算,因为第一级解码器不需要使用任何码字检验字节来用于错误位置计算。第一级解码器的纠错能力加倍,因为释放了所有码字检验字节以用于错误字节值计算。现有技术系统使用第一级检验字节来用于错误检测和校正。
如上所述,在美国专利5,946,328和6,275,965中所述的现有技术用于校正在两级分组结构中组织的数据流中的随机错误。所述系统可能不能确定错误是否是随机错误或突发错误。因此,如果现有技术不能校正有错误的所有字节,则本发明的技术可以尝试校正有错误的字节。如果错误是突发错误,则本发明更可能能够校正有错误的所有字节。
虽然已经参照本发明的特定实施例在此说明了本发明,在本发明中意欲进行修改、各种改变和替代。在一些情况下,可以在不脱离所给出的本发明的范围的情况下不对应地使用其他特征而使用本发明的特征。因此,可以在不脱离本发明的必要范围和精神的情况下,使得许多修改适合所公开的特定配置或方法。意欲本发明不限于所公开的特定实施例,而是本发明将包括落入权利要求的范围内的所有实施例和等同内容。
Claims (17)
1.一种盘驱动控制器,用于校正在数据字节中的多个突发错误,所述盘驱动控制器包括:
第一级解码器;以及
第二级解码器,它使用分组级检验字节来检测在包含突发错误的数据字节的两级分组结构中的列,
其中,第二级解码器产生删除指针,用于标识在包含突发错误的两级分组结构中的列,
第一级解码器使用在所述两级分组结构中的码字检验字节来校正在由所述删除指针标识的列中的所有数据字节,以及
第一级解码器不将任何码字检验字节用于错误位置计算。
2.按照权利要求1的盘驱动控制器,其中,第一级解码器配置成使用码字检验字节来检测和校正在数据字节的两级分组结构中的随机错误。
3.按照权利要求2的盘驱动控制器,其中,如果第一级解码器未校正所有的随机错误,则第二级解码器使用分组级检验字节来校正在一个码字中的随机错误,以及
如果第一级和第二级解码器都未校正所有的随机错误,则第二级解码器仅仅产生删除指针。
4.按照权利要求1的盘驱动控制器,其中,盘驱动控制器去交错数据字节的两级分组结构,以分离出数据字节、分组级检验字节和码字检验字节。
5.按照权利要求1的盘驱动控制器,其中,盘驱动控制器产生校正子,用于在两级分组结构中的数据字节的纠错。
6.按照权利要求1的盘驱动控制器,其中,数据字节的两级分组结构被应用到综合矩阵的逆矩阵V-1,以重新分布数据字节、码字检验字节和分组级检验字节。
7.按照权利要求1的盘驱动控制器,其中,第一和第二级解码器是里德-索罗蒙解码器。
8.按照权利要求1的盘驱动控制器,其中,盘驱动控制器包括ECC读取处理器和ECC写入处理器。
9.一种盘驱动系统,用于校正在数据字节中的多个突发错误,所述盘系统包括:
盘组件,由盘和包括主轴电机的磁头组组件组成;以及
盘驱动控制器芯片组,它包括第一级和第二级解码器,
其中,第二级解码器使用分组级检验字节来检测在包括突发错误的数据字节的两级分组结构中的列,
第二级解码器产生删除指针,用于标识在包含突发错误的两级分组结构中的列,
第一级解码器使用在两级分组结构中的码字检验字节来校正在由删除指针标识的列中的所有数据字节。
10.按照权利要求9的盘驱动系统,其中,第一级解码器不将任何码字检验字节用于错误位置计算,第一级解码器使用用于错误值计算的所有码字检验字节。
11.按照权利要求10的盘驱动系统,其中,第一级解码器配置成在第二级解码器用于检测突发错误之前使用码字检验字节检测和校正在数据字节中出现的随机错误。
12.按照权利要求11的盘驱动系统,其中,如果第一级解码器未校正所有的随机错误,则第二级解码器使用分组级检验字节来校正在一个码字中的随机错误。
13.按照权利要求9的盘驱动系统,其中,盘驱动控制器去交错数据字节的两级分组结构,以分离出数据字节、分组级检验字节和码字检验字节。
14.按照权利要求9的盘驱动系统,其中,盘驱动控制器产生校正子,用于在两级分组结构中的数据字节的纠错。
15.按照权利要求9的盘驱动系统,其中,盘驱动控制器包括ECC读取处理器和ECC写入处理器。
16.按照权利要求9的盘驱动系统,其中,第一和第二级解码器是里德-索罗蒙解码器。
17.按照权利要求9的盘驱动系统,其中,数据字节的两级分组结构被应用到综合矩阵的逆矩阵V-1,以重新分布数据字节、码字检验字节和分组级检验字节。
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US5751733A (en) * | 1996-09-16 | 1998-05-12 | Cirrus Logic, Inc. | Interleaved redundancy sector for correcting an unrecoverable sector in a disc storage device |
CN1204120A (zh) * | 1997-05-08 | 1999-01-06 | 索尼株式会社 | 频率解调电路、光盘装置和预格式化装置 |
US5946328A (en) | 1997-11-17 | 1999-08-31 | International Business Machines Corporation | Method and means for efficient error detection and correction in long byte strings using integrated interleaved Reed-Solomon codewords |
US6275965B1 (en) | 1997-11-17 | 2001-08-14 | International Business Machines Corporation | Method and apparatus for efficient error detection and correction in long byte strings using generalized, integrated, interleaved reed-solomon codewords |
US6903887B2 (en) | 2002-01-03 | 2005-06-07 | International Business Machines Corporation | Multiple level (ML), integrated sector format (ISF), error correction code (ECC) encoding and decoding processes for data storage or communication devices and systems |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN103812511A (zh) * | 2012-11-15 | 2014-05-21 | 华为技术有限公司 | 一种译码方法及装置 |
WO2014075579A1 (zh) * | 2012-11-15 | 2014-05-22 | 华为技术有限公司 | 一种译码方法及装置 |
CN103812511B (zh) * | 2012-11-15 | 2017-04-26 | 华为技术有限公司 | 一种译码方法及装置 |
CN110851113A (zh) * | 2020-01-16 | 2020-02-28 | 江苏芯盛智能科技有限公司 | 字节序列随机性的检测方法、装置、存储介质及电子设备 |
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CN100474430C (zh) | 2009-04-01 |
US7231578B2 (en) | 2007-06-12 |
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