CN1700458A - 具有第一和第二导电凸点的半导体封装及其制造方法 - Google Patents
具有第一和第二导电凸点的半导体封装及其制造方法 Download PDFInfo
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- CN1700458A CN1700458A CNA2005100667995A CN200510066799A CN1700458A CN 1700458 A CN1700458 A CN 1700458A CN A2005100667995 A CNA2005100667995 A CN A2005100667995A CN 200510066799 A CN200510066799 A CN 200510066799A CN 1700458 A CN1700458 A CN 1700458A
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Abstract
在一实施例中，半导体封装包括基构架和电连接于基构架的下半导体芯片。下半导体芯片具有在其顶表面上的第一键合焊盘。该封装还包括在下半导体芯片上放置的上半导体芯片。上半导体芯片具有在其底表面上形成的第三键合焊盘。该封装包括共同地连接第一键合焊盘和第三键合焊盘的第一导电凸点和第二导电凸点。
Description
技术领域
本发明涉及半导体封装和制造其的方法，且更具体地涉及包括通过倒装片键合互连上和下半导体芯片的封装和制造其的方法。
背景技术
对更小电子设备的需求需要更薄和更小的半导体封装，其依次又需要更小的半导体器件。为了满足市场的需求，为制造半导体器件提出了芯片上系统(SOC)结构和封装中系统(SIP)机构。
SOC是一种半导体器件，其中多个半导体芯片被集成为单一半导体芯片。SIP是一种半导体器件，其中多个单独的半导体芯片被放在单一的半导体封装中。结合SIP工艺，在单一半导体封装内横向地或纵向地装入多个半导体芯片且具有典型的多芯片封装(MCP)构思。一般地，在MCP中横向地装入多个半导体芯片而在SIP中纵向地层叠多个半导体芯片。
在一般半导体设备的印刷电路板中，半导体器件与无源器件安装以改善半导体器件的噪音特性。无源器件包括电容、电阻和电感。安装无源器件尽可能地靠近半导体器件以改善半导体器件的特性。因此，已经开发了包括如电容的无源器件和如微处理器的半导体芯片的SIP。
使用硅晶片制造作为无源器件的电容器。使用硅晶片形成电容器的技术是众所周知的。在由Lucent Technology Co.Ltd申请的美国专利申请序列号9/386,660(申请于1999年8月31日)中公开了一示范性技术。
在授予VLSI Technology Inc.的美国专利第6,057,598号(于2000年5月2日公布、题目为“面对面倒装片集成，Face on Face Flip Chip Integration”)中公开了一种半导体封装和制造其的方法。在该专利中，通过倒装片键合技术互连上和下半导体芯片。
图1是传统的半导体封装260的剖面图。
请参考图1，在基构架262上层叠下半导体芯片212和上半导体芯片200，且通过倒装片键合用在下半导体芯片212和上半导体芯片200之间设置的焊料凸点210互连。在下半导体芯片的边缘上放置的键合焊盘226通过引线264电连接于基构架的引线(未显示)。用密封树脂266密封上和下半导体芯片200和212、引线264和基构架262的一部分。
图2至4是图示在传统的半导体封装内通过倒装片键合互连的下半导体芯片200和上半导体芯片212的剖面图。
请参考图2，在上半导体芯片200的下面形成焊料凸点210。上和下半导体芯片200和212在由箭头A指示的方向上被放在一起。上半导体芯片200具有电路区202和键合焊盘208。下半导体芯片212具有电路区214和相应于上半导体芯片200的键合焊盘208的键合焊盘224。另外，在下半导体芯片212的边缘上分开形成用于导线键合的附加的键合焊盘226。
图3是图示在传统的半导体封装中当在键合焊盘12上形成焊料凸点210时焊盘12的上层结构的剖面图。为了形成焊料凸点210，在通过其暴露键合焊盘12的钝化层14上附加形成如聚酰亚胺(polyimide)膜的绝缘层16。另外，应形成连接于键合焊盘12的凸点下冶金(Under Bump MetallurgyUBM)层18。附图标记10指示半导体芯片。
但是难以直接在一般构成键合焊盘12的铝层或铜层上形成焊料凸点210。为了解决该问题，UBM层18促进焊料凸点210和键合焊盘12的键合且防止焊料凸点的组分扩散入键合焊盘。UBM层18典型地是包括互连层、扩散阻挡层和浸润层的多金属层结构。
图4是在图1中的部分B的放大的剖面图。
请参考图4，在上半导体芯片200和下半导体芯片212的键合焊盘12和12’上分别形成UBM层18和另一UBM层18’以实现使用焊料凸点210的倒装片键合。在下半导体芯片212上形成UBM层18’以促进固定于上半导体芯片200的焊料凸点210的键合和防止焊料凸点210的扩散进入下半导体芯片212的键合焊盘12’。
使用焊料凸点210的倒装片键合技术可以优选地用于互连，因为在引线键合(wiring bonding)期间可能对半导体芯片施加在预定水平以上的压力，特别当在半导体芯片的中心部分放置键合焊盘时。这样，压力可以损伤在键合焊盘的下层部分上放置的半导体芯片的电路区。
图5是图示图1所示的半导体封装的引线键合于下半导体芯片212(图1的部分C)的剖面图。对另一设置在下半导体芯片212上的键合焊盘226(图1)形成促进引线键合的金属层19。金属层可以由Ni/Au、Ni/Ag或Ti/Cu/Ni/Au的复合层组成。
但是，在传统的半导体封装中，在下半导体芯片中附加形成UBM层，其非期望地延长了整体的SIP的制造工艺时间且增加了制造成本。
发明内容
本发明尤其提供了具有用于倒装片键合的新结构的半导体封装，由此消除在不具有焊料凸点的半导体芯片上的UBM层的需求。本发明还提供了制造如封装中系统(SIP)的制造新半导体封装的方法。
根据本发明的一个方面，提供一种半导体封装，包括：
基构架；
与所述基构架电连接的下半导体芯片，所述下半导体芯片具有在其顶表面上形成的第一键合焊盘；
在所述下半导体芯片之上的上半导体芯片，所述上半导体芯片具有在其底表面上形成的第三键合焊盘；
第一导电凸点和第二导电凸点，共同地连接所述第一键合焊盘和所述第三键合焊盘。
根据本发明的另一方面，提供一种制造封装的方法包括：
提供基构架；
提供下半导体芯片，所述下半导体芯片具有在所述下半导体芯片的中心部分上的第一键合焊盘和在所述下半导体芯片的周边部分上的第二键合焊盘；
在所述基构架上安装所述下半导体芯片；
提供上半导体芯片，所述上半导体芯片具有相应于所述半导体芯片的第一键合焊盘的第三键合焊盘；和
通过一起使用第一导电凸点和第二导电凸点连接所述第三键合焊盘和所述第一键合焊盘，在所述下半导体芯片上安装所述上半导体芯片。
根据本发明的再一个方面，提供一种制造封装的方法，该方法包括：
制备下半导体芯片，所述下半导体芯片具有在其中心部分的第一键合焊盘，和上半导体芯片，所述上半导体芯片具有相应于所述下半导体芯片的第一键合焊盘的第三键合焊盘；
一起使用第一导电凸点和第二导电凸点，电连接所述下半导体芯片的第一键合焊盘与所述上半导体芯片的第三键合焊盘；和
在所述基构架上安装所述电连接的上半导体芯片和下半导体芯片。
在一实施例中，半导体封装包括基构架和电连接于基构架的下半导体芯片。下半导体芯片具有在其顶表面上形成的第一键合焊盘。封装还包括放在下半导体芯片上的上半导体芯片。上半导体芯片具有在其底表面上形成的第三键合焊盘。封装包括共同地连接第一键合焊盘和第三键合焊盘的第一导电凸点和第二导电凸点。
附图说明
通过参考附图详细描述本发明的示范性实施例，本发明的上述和其它特征和优点将变得显而易见，其中：
图1是传统的半导体封装的剖面图；
图2至图4是图示在图1中所示的传统的半导体封装中通过倒装片键合互连的下半导体芯片和上半导体芯片的剖面图；
图5是图示在图1中所示的传统的半导体封装中引线键合于下半导体芯片的剖面图；
图6是图示本发明的实施例的半导体封装的剖面图；
图7是图示在图6中所示的半导体封装中通过倒装片互连的下半导体芯片和上半导体芯片的剖面图；
图8是图示在图6中所示的半导体封装中引线键合于下半导体芯片的剖面图；
图9是图示本发明的另一实施例的半导体封装的剖面图；
图10是图示在图9中所示的半导体封装中通过倒装片互连的下半导体芯片和上半导体芯片的剖面图；
图11是图示在图9中所示的半导体封装中引线键合于下半导体芯片的剖面图；
图12是图示本发明的再一实施例的半导体封装的剖面图；
图13是图示在图12中所示的半导体封装中通过倒装片互连的下半导体芯片和上半导体芯片的剖面图；
图14是图示在图12中所示的半导体封装中引线键合于下半导体芯片的剖面图；
图15是图示本发明的再一实施例的半导体封装的剖面图；
图16是图示在图15中所示的半导体封装中通过倒装片互连的下半导体芯片和上半导体芯片的剖面图；
图17是图示在图15中所示的半导体封装中引线键合于下半导体芯片的剖面图；
图18是图示本发明的实施例的半导体封装的基构架、下半导体芯片和上半导体芯片的结构的平面图；和
图19是图示本发明的实施例的半导体封装的剖面图。
具体实施方式
现在将参考附图更加全面地描述本发明。但是本发明可以以不同的形式具体表达且不应解释为限于在这里阐述的实施例；而是提供这些实施例以使本公开充分和完整，且全面地对本领域的技术人员传达本发明的构思。
请参考图6，本发明的实施例的半导体封装，例如SIP100A，包括基构架110。通过例如粘合剂160将下半导体芯片固定于基构架110的芯片焊盘。在下半导体芯片120的上表面的中心部分上形成第一键合焊盘122，用于倒装片互连，且在下半导体芯片120的上表面的边缘部分或周边区域上形成第二键合焊盘132。另外，下半导体芯片120包括导电凸点124，例如金凸点，其形成在第一键合焊盘122上。导电凸点124可以形成为按扣(stud)状或其它合适的结构用于互连。
SIP100A可以包括电连接下半导体芯片120的第二键合焊盘132至基构架110的引线130。而且，在下半导体芯片120上安装的上半导体芯片140包括另一导电凸点144，例如，设置在第三键合焊盘142上的焊料凸点，以连接于在下半导体芯片120的第一键合焊盘122上的金凸点124。密封树脂150可以紧密地密封一部分基构架110、引线130、下半导体芯片120和上半导体芯片140。
可以用密封树脂150，或未充满材料170，如环氧，填充在互连的下半导体芯片120和上半导体芯片140之间的空间以提供互连的可靠性。
在半导体组装工艺期间使用引线键合设备可以在第一键合焊盘122上容易地形成金凸点124。金凸点124消除了在第二键合焊盘132上的UBM层的需求。即，尽管采用传统的第一和第二键合焊盘122和132，但是不需要在下半导体芯片120上形成UBM层。由此，可以缩短整体的制造工艺的时间且降低制造成本。
图7是图示SIP中使用倒装片技术下半导体芯片120和上半导体芯片140的互连的剖面图。图8是图示引线130键合于下半导体芯片120的剖面图。
请参考图7和图8，本发明的该实施例的SIP100A中，通过连接按扣状金凸点124至焊料凸点144可以实现倒装片键合。具有焊料凸点144的上半导体芯片140经受UBM处理，其中形成绝缘层146和UBM层148。但是，在具有金凸点124的下半导体芯片120上不需UBM处理。而且，连接下半导体芯片120与基构架110的引线130直接连接于构成第二键合焊盘132的铝。引线130可以由Au、Ag或Cu组成。
请参考图6，现在将描述本发明的实施例的制造SIP110A的方法。
柔性印刷电路板(PCB)或刚性PCB可以用作基构架110。一般用于球栅阵列(BGA)的基构架可以用作基构架110。然后，优选地使用如粘接带或环氧的粘接剂160，在基构架110上安装下半导体芯片120。在下半导体芯片120的中心部分上形成适合倒装片键合的第一键合焊盘122，且在下半导体芯片120的边缘部分上形成用于引线键合的第二键合焊盘132。在第一键合焊盘122上形成金凸点124。下半导体芯片120可以用为微处理器、LSI或逻辑器件。
金凸点124可以在晶片制造工艺中形成，或者在基构架110上安装下半导体芯片120之后的半导体芯片状态中形成。
随后，通过如键合引线130的电连接装置将下半导体芯片120的第二键合焊盘132电连接于基构架110的键合指(图18的标号112)。引线键合可以在装入上半导体芯片140之后进行。
制备具有相应于下半导体芯片120的第一键合焊盘122的第三键合焊盘143的上半导体芯片140和在第三键合焊盘142上的焊料凸点144。上半导体芯片140的第三键合焊盘142形成有UBM层148和绝缘层146，以促进焊料凸点144的互连以及防止扩散。
然后，通过倒装片键合将下半导体芯片120的金凸点124设置为与上半导体芯片140的焊料凸点144接触，由此在下半导体芯片120上安装上半导体芯片140。在安装上半导体芯片140之后，在下半导体芯片120和上半导体芯片140之间填充如液态环氧的未充满材料以改进互连的可靠性，且固化形成未充满材料170。
因此，可以通过密封树脂150密封一部分基构架110、引线130以及下和上半导体芯片120和140。最后，将焊料球153固定于设置在基构架110下的焊料球焊盘(未显示)，且进行单独地分离以矩阵形成制造的SIP100A的单一化工艺。
请重新参考图6，现在将描述制造SIP的另一方法。这里，首先互连下半导体芯片120和上半导体芯片140，且然后在基构架110上安装互连的结构。
更具体地，以第一键合焊盘122在中心部分上和第二键合焊盘132在周边部分上形成下半导体芯片120。以相应于第一键合焊盘122的第三键合焊盘142在其上形成上半导体芯片140。在第一键合焊盘122上形成按扣状金凸点124，且在第三键合焊盘142上形成焊料凸点144。
下半导体芯片120的金凸点124和上半导体芯片140的焊料凸点144设置为互相接触。然后，使用粘接剂160在基构架110上安装共同互连的下半导体芯片120和上半导体芯片140。在紧接着互连下半导体芯片120与上半导体芯片140之后，或在紧接着基构架110上安装互连的下半导体芯片120和上半导体芯片140之后，下半导体芯片120和上半导体芯片140可以经受焊剂清除。
用液态环氧填充下半导体芯片120和上半导体芯片140之间的空间，环氧被固化以形成未充满材料170以改善互连的可靠性。
之后，通过引线130电连接下半导体芯片的第二键合焊盘132和基构架110。使用密封树脂150可以密封基构架110、引线130以及下和上半导体芯片120和140。最后，将焊料球152固定于设置在基构架110下的焊料球焊盘(未显示)，且进行单独分离以矩阵形成制造的SIP100A的单一化工艺。
现在将描述具有施加于上半导体芯片的按扣状的金凸点的另一实施例。图9是图示本发明的该实施例的SIP的剖面图。
请参考图9，SIP100B包括其上可以安装半导体芯片的基构架110。使用粘接剂160将下半导体芯片120固定于基构架芯片焊盘，且在下半导体芯片120的中心部分上形成用于倒装片键合的第一键合焊盘122和在下半导体芯片120的边缘部分上形成第二键合焊盘132。在下半导体芯片120的第一键合焊盘122上形成焊料凸点124。
SIP100B还包括电连接下半导体芯片120的第二键合焊盘132至基构架110的引线130，和在下半导体芯片120上层叠的上半导体芯片140。上半导体芯片140的第三键合焊盘142形成有金凸点144，以与下半导体芯片120的互连凸点124接触。
SIP100B还包括紧密地密封一部分基构架110、引线130、下半导体芯片120和上半导体芯片140。在下半导体芯片120与上半导体芯片140之间形成未充满材料170。以按扣状金凸点144形成的上半导体芯片140的第三键合焊盘142消除了UBM处理的需求。
图10是图示本发明的实施例的SIP中下半导体芯片120和上半导体芯片140的倒装片键合剖面图。图11是图示导线130键合于下半导体芯片120的剖面图。
请参考图10和图11，通过上半导体芯片140的按扣状金凸点144与在下半导体芯片120上形成的焊料凸点124接触获得倒装片键合。具有焊料凸点124的下半导体芯片120经受UBM处理。即，下半导体芯片120包括绝缘层126和UBM层128。
在UBM层128上形成金属层129以帮助促进引线键合工艺。金属层129可由Ni/Au、Ni/Ag或Ni/Pd的复合层组成。引线130可以是Au、Ag和Cu。
此后，将参考图9描述本发明的该实施例的制造SIP100B的方法。
柔性PCB或刚性PCB可以用作基构架110。然后，使用如粘接带或环氧的粘接剂160，下半导体芯片120固定于基构架110。在下半导体芯片120的中心部分上形成适合倒装片键合的第一键合焊盘122，且在下半导体芯片120的边缘部分上形成用于引线键合的第二键合焊盘132。在第一键合焊盘122上形成焊料凸点124。下半导体芯片120可以是微处理器、LSI或逻辑器件而上半导体芯片140可以是电容器器件。
随后，通过引线键合将下半导体芯片120的第二键合焊盘132电连接于基构架110的键合指112(见图18)。该工艺也可以在装入上半导体芯片140之后进行。
然后，制备具有相应于下半导体芯片120的第一键合焊盘122的第三键合焊盘143的上半导体芯片140和在第三键合焊盘142上的金凸点144。可以在晶片制造工艺中形成金凸点144。上半导体芯片140的第三键合焊盘142可以不包括UBM层。
然后，通过倒装片键合互连下半导体芯片120的焊料凸点124与上半导体芯片140的金凸点144，由此在下半导体芯片120上安装上半导体芯片140。在安装上半导体芯片140之后，在下半导体芯片120和上半导体芯片140之间填充如液态环氧，且固化形成未充满材料170的以改进互连的可靠性。
通过密封树脂150密封基构架110、引线130以及下和上半导体芯片120和140。最后，将焊料球152固定于设置在基构架110下层部分，且单一化以矩阵形成制造的SIP100B。
现在将参考图9描述本发明的另一实施例的制造SIP100B的方法。这时，首先互连下半导体芯片120和上半导体芯片140，且然后在基构架110上装入结果的结构。
更具体地，制备下半导体芯片120和上半导体芯片140。这时，下半导体芯片120具有在中心部分上的第一键合焊盘122和在周边部分的上第二键合焊盘132。上半导体芯片140具有以相应于第一键合焊盘122的第三键合焊盘142。在第一键合焊盘122上形成焊料凸点124，且在第三键合焊盘142上形成按扣状金凸点144。
下半导体芯片120的焊料凸点124和上半导体芯片140的金凸点144设置为互相接触。然后，使用粘接剂160在基构架110上安装共同互连的下半导体芯片120和上半导体芯片140。在紧接着互连之后或在紧接着基构架110上安装已经互连的下半导体芯片120和上半导体芯片140之后，下半导体芯片120和上半导体芯片140可以经受焊剂清除。
为了改善互连的可靠性，在下半导体芯片120和上半导体芯片140之间填充液态环氧，其然后被固化以形成未充满材料170。
之后，引线130电连接于包括金属层129的第二键合焊盘132用于促进对基构架110的引线键合。使用密封树脂150或其它适合的封装剂密封或封装基构架110、引线130以及下和上半导体芯片120和140。最后，将焊料球152固定于设置在基构架110的下层部分，且以矩阵形成制造的SIP100B被单一化，即，单独地分离。
现在将描述具有施加于下半导体芯片的电镀的金凸点的再一实施例。
图12是图示本发明的本方面的该实施例的SIP的剖面图。图13是图示下半导体芯片120和上半导体芯片140的倒装片键合的剖面图。图14是图示导线键合于下半导体芯片120的剖面图。
请参考图12、13、14，本发明的该实施例的SIP100C的结构和制造方法与上述的第一实施例相似。为了简明因此将省略相同部分的描述。
相对于所述的第一实施例，在第三实施例中的下半导体芯片120上设置的金凸点125由电镀(electroplating)形成。在下半导体芯片120的边缘上的第二键合焊盘132上以及下半导体芯片120的第一键合焊盘122上形成金凸点125。因此，在设置在第二键合焊盘132上的金凸点125上进行连接下半导体芯片120和基构架110的引线键合。因此，引线键合的金凸点134具有两个层叠的球键合的形状。
如所述的第一实施例，在上半导体芯片140上进行UBM处理，但不需对下半导体芯片120进行UBM处理。因此，简化了工艺且降低了制造成本。
现在将描述具有施加于上半导体芯片140的电镀金凸点的再一实施例。
图15是图示本发明的本方面的该实施例的SIP的剖面图。图16是图示下半导体芯片120和上半导体芯片140的倒装片键合的剖面图。图17是图示导线键合于下半导体芯片120的剖面图。
请参考图15、16、17，本发明的该实施例的SIP100C的结构和制造方法与图9相关描述的实施例相似。为了简明因此将省略相同部分的描述。
相对于图9所示的实施例，上半导体芯片140的第三键合焊盘142上设置的金凸点144由电镀形成。如图9的实施例，下半导体芯片120经受UBM处理，对上半导体芯片140未进行UBM处理。因此，简化了工艺且降低了制造成本。
图18是图示本发明的实施例的半导体封装的基构架、下半导体芯片和上半导体芯片的结构的平面图。
请参考图18，在基构架110上安装下半导体芯片120。在下半导体芯片120上安装上半导体芯片140。通过引线130在下半导体芯片120上设置的第二键合焊盘132电连接于在基构架110上的引线指针112。本发明的实施例的下和上半导体芯片120和140的倒装片互连150的材料和结构由焊料凸点和金凸点接触表征。
上半导体芯片140可以是用于改善半导体器件的噪音特性的无源器件。无源器件的制造方法是众所周知的，且为了简明省略了在美国专利申请序列号9/386,660(由Lucent Technology Co.Ltd申请于1999年8月31日)公开的这样的方法的例子的详细说明。
而且，在下半导体芯片120的中心部分上的第一键合焊盘122可以通过内部电路线121连接至第二键合焊盘132。可以在用于形成晶片级封装(WIP)的晶片制造工艺期间或之后形成连接第一和第二键合焊盘122和132的内部电路线121。
因此，作为电容器的上半导体芯片140的电源和接地端子可以通过第一键合焊盘122连接至第二键合焊盘132。而且，可以通过引线130将第二键合焊盘132连接至基构架110的键合指针112。键合指针112可以通过焊料球(未显示)外部地连接固定于基构架110的下层表面。
因此，可以邻近于作为微处理器、LSI器件或逻辑器件的下半导体芯片120装入作为电容器的上半导体芯片140，由此具体化能够改善下半导体芯片120的噪音特性的SIP。
在再一实施例中，可以使用引线构架作为基构架。
图19是本发明的一实施例的SIP的剖面图。在前述的实施例中，基构架110可以是柔性PCB或刚性PCB。但是，SIP100E包括替代在上述的实施例中包括的PCB的引线构架110’。引线构架110’包括芯片焊盘114和引线112。依据引线构架110’的形状，SIP100E可以使用不同的封装，如薄小外形封装(Thin Small Outline Package TSOP)、薄四方平封装(Thin Quad FlatPackage TQFP)和四方薄无引线封装(Quad Flat No-lead Package QFN)。在该情况中，在封装或密封之后，从密封树脂150外部地暴露的引线112可以被引线栅修整(lead bar trimmed)、引线镀或引线形成。另外，本发明可应用于针栅阵列(PGA)封装，其中取代使用焊料球针栅与基构架110的下表面连接。
如上所述，用本发明的实施例，不需要在具有金凸点的半导体芯片上进行UBM处理。因此，可以降低制造成本，且可以简化制造工艺。
当参考本发明的示范性实施例具体显示和描述本发明时，本领域的技术人员会理解在不背离由所附的权利要求界定的本发明的精神和范围内，可以在其内作不同的形式和细节的更动。
本申请要求于2004年4月30日申请的韩国专利申请第10-2004-0030468的优先权，其全部内容引入作为参考。
Claims (57)
1.一种半导体封装，包括：
基构架；
与所述基构架电连接的下半导体芯片，所述下半导体芯片具有在其顶表面上形成的第一键合焊盘；
在所述下半导体芯片之上的上半导体芯片，所述上半导体芯片具有在其底表面上形成的第三键合焊盘；
第一导电凸点和第二导电凸点，共同地连接所述第一键合焊盘和所述第三键合焊盘。
2.如权利要求1的封装，其中所述第一键合焊盘形成于所述下半导体芯片的中心部分上，且一第二键合焊盘形成在所述下半导体芯片的周边上，所述第二键合焊盘电连接于所述基构架。
3.如权利要求1的封装，其中在所述第一导电凸点内设置所述第二导电凸点。
4.如权利要求1的封装，其中所述第一导电凸点连接于所述第一键合焊盘，且所述第二导电凸点连接于所述第三键合焊盘。
5.如权利要求4的封装，其中所述第一导电凸点包括焊料且所述第二导电凸点包括金。
6.如权利要求5的封装，其中在所述第三键合焊盘上未形成UBM层。
7.如权利要求5的封装，还包括在所述第二键合焊盘的表面上形成的金属层。
8.如权利要求7的封装，其中所述金属层是Ni/Au、Ni/Ag或Ni/Pd的复合层。
9.如权利要求4的封装，其中所述第一导电凸点包括金且所述第二导电凸点包括焊料。
10.如权利要求9的封装，其中在所述第一和第二键合焊盘上未形成UBM层。
11.如权利要求1的封装，还包括
密封一部分所述基构架、所述下半导体芯片和所述上半导体芯片的密封树脂。
12.如权利要求1的封装，其中所述基构架是柔性印刷电路板(PCB)、刚性PCB或引线构架。
13.如权利要求1的封装，其中所述下半导体芯片和上半导体芯片之一作为电容器。
14.如权利要求1的封装，其中所述第一和第二导电凸点之一包括由电镀或散布(studding)形成的金凸点。
15.如权利要求1的封装，还包括填充在所述下半导体芯片和上半导体芯片之间的空间的未充满材料。
16.如权利要求1的封装，其中还包括固定于所述基构架的底表面的焊料球。
17.如权利要求1的封装，其中所述第一和第二键合焊盘彼此电连接。
18.一种制造封装的方法包括：
提供基构架；
提供下半导体芯片，所述下半导体芯片具有在所述下半导体芯片的中心部分上的第一键合焊盘和在所述下半导体芯片的周边部分上的第二键合焊盘；
在所述基构架上安装所述下半导体芯片；
提供上半导体芯片，所述上半导体芯片具有相应于所述半导体芯片的第一键合焊盘的第三键合焊盘；和
通过一起使用第一导电凸点和第二导电凸点连接所述第三键合焊盘和所述第一键合焊盘，在所述下半导体芯片上安装所述上半导体芯片。
19.如权利要求18的方法，还包括电连接所述第二键合焊盘与所述基构架。
20.如权利要求18的方法，其中在所述第一导电凸点内设置所述第二导电凸点。
21.如权利要求18的方法，还包括使用密封树脂密封一部分所述基构架以及所述上和下半导体芯片。
22.如权利要求18的方法，其中所述基构架是柔性PCB、刚性PCB或引线构架。
23.如权利要求18的方法，其中在所述基构架上安装所述下半导体芯片包括使用粘接带或环氧。
24.如权利要求18的方法，其中在所述上半导体芯片上形成所述第二导电凸点，且在所述下半导体芯片上形成所述第一导电凸点。
25.如权利要求24的方法，其中所述第二导电凸点包括焊料且所述第一导电凸点包括金。
26.如权利要求25的方法，其中在所述第一和第二键合焊盘上未形成UBM层。
27.如权利要求24的方法，其中所述第二导电凸点包括金且所述第一导电凸点包括焊料。
28.如权利要求27的方法，其中在所述第三键合焊盘上未形成UBM层。
29.如权利要求27的方法，还包括在所述第二键合焊盘的表面上形成金属层以促进引线键合。
30.如权利要求29的方法，其中所述金属层包括Ni/Au、Ni/Ag或Ni/Pd的复合层。
31.如权利要求18的方法，还包括，在所述下半导体芯片上安装所述上半导体芯片后：
在所述下半导体芯片和上半导体芯片之间填充液态未充满的材料；和
固化所述液态未充满材料。
32.如权利要求18的方法，其中所述下半导体芯片和上半导体芯片之一作为电容器。
33.如权利要求18的方法，其中所述第一和第二导电凸点之一包括由散布形成的金凸点。
34.如权利要求33的方法，其中在所述基构架上形成所述下半导体芯片之前在晶片制造工艺中形成所述金凸点。
35.如权利要求33的方法，其中在所述基构架上安装所述下半导体芯片之后形成所述金凸点。
36.如权利要求33的方法，其中通过电镀形成所述金凸点。
37.如权利要求33的方法，其中在所述第一和第二键合焊盘上形成所述电镀的金凸点。
38.如权利要求21的方法，还包括，在密封之后，固定焊料球于在所述基构架的下层表面上设置的焊料球焊盘。
39.如权利要求21的方法，还包括，在密封之后，处理从密封树脂外部暴露的引线。
40.一种制造封装的方法，该方法包括：
制备下半导体芯片，所述下半导体芯片具有在其中心部分的第一键合焊盘，和上半导体芯片，所述上半导体芯片具有相应于所述下半导体芯片的第一键合焊盘的第三键合焊盘；
一起使用第一导电凸点和第二导电凸点，电连接所述下半导体芯片的第一键合焊盘与所述上半导体芯片的第三键合焊盘；和
在所述基构架上安装所述电连接的上半导体芯片和下半导体芯片。
41.如权利要求40的方法，其中在所述下半导体芯片的边缘部分形成第二键合焊盘，还包括电连接所述第二键合焊盘与所述基构架。
42.如权利要求40的方法，还包括密封所述一部分的基构架、所述引线和所述下和上半导体芯片。
43.如权利要求40的方法，还包括在电连接所述下半导体芯片和上半导体芯片之后的焊剂清除。
44.如权利要求43的方法，还包括，在焊剂清除之后：
在所述下半导体芯片和上半导体芯片之间填充液态未充满材料；和
固化所述液态未充满材料。
45.如权利要求40的方法，其中所述基构架是柔性PCB、刚性PCB或引线构架。
46.如权利要求40的方法，其中在所述上半导体芯片上形成所述第二导电凸点，且在所述下半导体芯片上形成所述第一导电凸点。
47.如权利要求46的方法，其中所述第一导电凸点包括金且所述第二导电凸点包括焊料。
48.如权利要求47的方法，其中在所述第一和第二键合焊盘上未形成UBM层。
49.如权利要求46的方法，其中所述第一导电凸点包括焊料且所述第二导电凸点包括金。
50.如权利要求49的方法，其中在所述第三键合焊盘上未形成UBM层。
51.如权利要求49的方法，还包括在所述第二键合焊盘的表面上形成金属层以促进引线键合。
52.如权利要求51的方法，其中所述金属层包括Ni/Au、Ni/Ag或Ni/Pd的复合层。
53.如权利要求40的方法，其中所述下半导体芯片和上半导体芯片之一作为电容器。
54.如权利要求40的方法，其中所述第一和第二导电凸点之一包括由电镀或散布形成的金凸点。
55.如权利要求54的方法，其中在所述第一和第二键合焊盘上形成所述电镀的金凸点。
56.如权利要求42的方法，还包括，在密封之后，固定焊料球于在所述基构架的下层表面上设置的焊料球焊盘。
57.如权利要求42的方法，还包括，在密封之后，处理从密封树脂外部暴露的引线。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040030468A KR100604848B1 (ko) | 2004-04-30 | 2004-04-30 | 솔더 범프와 골드 범프의 접합을 갖는 시스템 인 패키지및 그 제조방법 |
| KR30468/04 | 2004-04-30 |
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| CN1700458A true CN1700458A (zh) | 2005-11-23 |
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| CNA2005100667995A Pending CN1700458A (zh) | 2004-04-30 | 2005-04-29 | 具有第一和第二导电凸点的半导体封装及其制造方法 |
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| US (1) | US20050242426A1 (zh) |
| JP (1) | JP2005317975A (zh) |
| KR (1) | KR100604848B1 (zh) |
| CN (1) | CN1700458A (zh) |
| DE (1) | DE102005020972A1 (zh) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8148819B2 (en) | 2008-05-19 | 2012-04-03 | Sharp Kabushiki Kaisha | Semiconductor device, method for mounting semiconductor device, and mounting structure of semiconductor device |
| CN102412208A (zh) * | 2010-09-21 | 2012-04-11 | 矽品精密工业股份有限公司 | 芯片尺寸封装件及其制法 |
| CN102769009A (zh) * | 2011-05-04 | 2012-11-07 | 三星半导体(中国)研究开发有限公司 | 半导体封装件 |
| CN103379736A (zh) * | 2012-04-13 | 2013-10-30 | 广达电脑股份有限公司 | 系统级封装组件、印刷电路板组件及其制作方法 |
| CN110323198A (zh) * | 2019-07-26 | 2019-10-11 | 广东气派科技有限公司 | 非接触式上下芯片封装结构及其封装方法 |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9299634B2 (en) * | 2006-05-16 | 2016-03-29 | Broadcom Corporation | Method and apparatus for cooling semiconductor device hot blocks and large scale integrated circuit (IC) using integrated interposer for IC packages |
| US9013035B2 (en) * | 2006-06-20 | 2015-04-21 | Broadcom Corporation | Thermal improvement for hotspots on dies in integrated circuit packages |
| DE102006034679A1 (de) * | 2006-07-24 | 2008-01-31 | Infineon Technologies Ag | Halbleitermodul mit Leistungshalbleiterchip und passiven Bauelement sowie Verfahren zur Herstellung desselben |
| JP5338029B2 (ja) * | 2007-01-26 | 2013-11-13 | 日亜化学工業株式会社 | 半導体レーザ素子、半導体レーザ装置及びその製造方法 |
| TWI364793B (en) * | 2007-05-08 | 2012-05-21 | Mutual Pak Technology Co Ltd | Package structure for integrated circuit device and method of the same |
| JP5331610B2 (ja) * | 2008-12-03 | 2013-10-30 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
| CN102691921A (zh) * | 2011-03-22 | 2012-09-26 | 展晶科技(深圳)有限公司 | 发光二极管灯条及其制造方法 |
| KR20140070057A (ko) * | 2012-11-30 | 2014-06-10 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
| KR102190382B1 (ko) | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | 반도체 패키지 |
| KR102053349B1 (ko) | 2013-05-16 | 2019-12-06 | 삼성전자주식회사 | 반도체 패키지 |
| KR101504011B1 (ko) | 2013-06-26 | 2015-03-18 | (주)인터플렉스 | 복합 직접회로소자 패키지 제조방법 |
| JP6386746B2 (ja) | 2014-02-26 | 2018-09-05 | 株式会社ジェイデバイス | 半導体装置 |
| CN104157617B (zh) | 2014-07-29 | 2017-11-17 | 华为技术有限公司 | 芯片集成模块、芯片封装结构及芯片集成方法 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5211875A (en) * | 1991-06-27 | 1993-05-18 | W. R. Grace & Co.-Conn. | Methods and compositions for oxygen scavenging |
| TW520816U (en) * | 1995-04-24 | 2003-02-11 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| US5889326A (en) * | 1996-02-27 | 1999-03-30 | Nec Corporation | Structure for bonding semiconductor device to substrate |
| US6057598A (en) * | 1997-01-31 | 2000-05-02 | Vlsi Technology, Inc. | Face on face flip chip integration |
| US6413797B2 (en) * | 1997-10-09 | 2002-07-02 | Rohm Co., Ltd. | Semiconductor device and method for making the same |
| US6369451B2 (en) * | 1998-01-13 | 2002-04-09 | Paul T. Lin | Solder balls and columns with stratified underfills on substrate for flip chip joining |
| SG93192A1 (en) * | 1999-01-28 | 2002-12-17 | United Microelectronics Corp | Face-to-face multi chip package |
| US6410415B1 (en) * | 1999-03-23 | 2002-06-25 | Polymer Flip Chip Corporation | Flip chip mounting technique |
| JP3597754B2 (ja) * | 2000-04-24 | 2004-12-08 | Ｎｅｃエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
| US7242099B2 (en) * | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
| US20020127747A1 (en) * | 2001-03-08 | 2002-09-12 | Motorola, Inc. | Lithography method and apparatus with simplified reticles |
| TW529141B (en) * | 2002-01-07 | 2003-04-21 | Advanced Semiconductor Eng | Stacking type multi-chip package and its manufacturing process |
-
2004
- 2004-04-30 KR KR1020040030468A patent/KR100604848B1/ko not_active IP Right Cessation
-
2005
- 2005-04-19 US US11/110,443 patent/US20050242426A1/en not_active Abandoned
- 2005-04-27 JP JP2005130543A patent/JP2005317975A/ja not_active Withdrawn
- 2005-04-29 DE DE102005020972A patent/DE102005020972A1/de not_active Ceased
- 2005-04-29 CN CNA2005100667995A patent/CN1700458A/zh active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8148819B2 (en) | 2008-05-19 | 2012-04-03 | Sharp Kabushiki Kaisha | Semiconductor device, method for mounting semiconductor device, and mounting structure of semiconductor device |
| CN102412208A (zh) * | 2010-09-21 | 2012-04-11 | 矽品精密工业股份有限公司 | 芯片尺寸封装件及其制法 |
| CN102412208B (zh) * | 2010-09-21 | 2014-08-13 | 矽品精密工业股份有限公司 | 芯片尺寸封装件及其制法 |
| CN102769009A (zh) * | 2011-05-04 | 2012-11-07 | 三星半导体(中国)研究开发有限公司 | 半导体封装件 |
| CN103379736A (zh) * | 2012-04-13 | 2013-10-30 | 广达电脑股份有限公司 | 系统级封装组件、印刷电路板组件及其制作方法 |
| CN110323198A (zh) * | 2019-07-26 | 2019-10-11 | 广东气派科技有限公司 | 非接触式上下芯片封装结构及其封装方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102005020972A1 (de) | 2006-01-05 |
| KR100604848B1 (ko) | 2006-07-31 |
| JP2005317975A (ja) | 2005-11-10 |
| US20050242426A1 (en) | 2005-11-03 |
| KR20050105361A (ko) | 2005-11-04 |
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